drm/radeon: replace udelay with mdelay for long timeouts
Some architectures require that delays longer than a few miliseconds are called through mdelay. This was triggered on ARM randconfig builds. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
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258f742635
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@ -2553,7 +2553,7 @@ static void r100_pll_errata_after_data(struct radeon_device *rdev)
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* or the chip could hang on a subsequent access
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*/
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if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
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udelay(5000);
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mdelay(5);
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}
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/* This function is required to workaround a hardware bug in some (all?)
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@ -2839,7 +2839,7 @@ void r600_rlc_stop(struct radeon_device *rdev)
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/* r7xx asics need to soft reset RLC before halting */
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WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
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RREG32(SRBM_SOFT_RESET);
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udelay(15000);
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mdelay(15);
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WREG32(SRBM_SOFT_RESET, 0);
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RREG32(SRBM_SOFT_RESET);
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}
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@ -407,7 +407,7 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
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RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
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RADEON_READ(R600_GRBM_SOFT_RESET);
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DRM_UDELAY(15000);
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mdelay(15);
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RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
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fw_data = (const __be32 *)dev_priv->me_fw->data;
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@ -500,7 +500,7 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
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RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
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RADEON_READ(R600_GRBM_SOFT_RESET);
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DRM_UDELAY(15000);
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mdelay(15);
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RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
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fw_data = (const __be32 *)dev_priv->pfp_fw->data;
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@ -1797,7 +1797,7 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev,
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RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
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RADEON_READ(R600_GRBM_SOFT_RESET);
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DRM_UDELAY(15000);
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mdelay(15);
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RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
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@ -633,7 +633,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
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tmp &= ~(R300_SCLK_FORCE_VAP);
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tmp |= RADEON_SCLK_FORCE_CP;
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WREG32_PLL(RADEON_SCLK_CNTL, tmp);
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udelay(15000);
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mdelay(15);
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tmp = RREG32_PLL(R300_SCLK_CNTL2);
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tmp &= ~(R300_SCLK_FORCE_TCL |
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@ -651,12 +651,12 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
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tmp |= (RADEON_ENGIN_DYNCLK_MODE |
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(0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
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WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
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udelay(15000);
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mdelay(15);
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tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
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tmp |= RADEON_SCLK_DYN_START_CNTL;
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WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
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udelay(15000);
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mdelay(15);
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/* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
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to lockup randomly, leave them as set by BIOS.
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@ -696,7 +696,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
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tmp |= RADEON_SCLK_MORE_FORCEON;
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}
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WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
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udelay(15000);
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mdelay(15);
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}
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/* RV200::A11 A12, RV250::A11 A12 */
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@ -709,7 +709,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
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tmp |= RADEON_TCL_BYPASS_DISABLE;
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WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
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}
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udelay(15000);
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mdelay(15);
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/*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */
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tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
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@ -722,14 +722,14 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
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RADEON_PIXCLK_TMDS_ALWAYS_ONb);
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WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
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udelay(15000);
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mdelay(15);
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tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
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tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
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RADEON_PIXCLK_DAC_ALWAYS_ONb);
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WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
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udelay(15000);
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mdelay(15);
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}
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} else {
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/* Turn everything OFF (ForceON to everything) */
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@ -861,7 +861,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
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}
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WREG32_PLL(RADEON_SCLK_CNTL, tmp);
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udelay(16000);
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mdelay(16);
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if ((rdev->family == CHIP_R300) ||
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(rdev->family == CHIP_R350)) {
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@ -870,7 +870,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
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R300_SCLK_FORCE_GA |
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R300_SCLK_FORCE_CBA);
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WREG32_PLL(R300_SCLK_CNTL2, tmp);
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udelay(16000);
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mdelay(16);
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}
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if (rdev->flags & RADEON_IS_IGP) {
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@ -878,7 +878,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
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tmp &= ~(RADEON_FORCEON_MCLKA |
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RADEON_FORCEON_YCLKA);
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WREG32_PLL(RADEON_MCLK_CNTL, tmp);
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udelay(16000);
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mdelay(16);
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}
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if ((rdev->family == CHIP_RV200) ||
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@ -887,7 +887,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
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tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
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tmp |= RADEON_SCLK_MORE_FORCEON;
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WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
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udelay(16000);
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mdelay(16);
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}
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tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
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@ -900,7 +900,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
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RADEON_PIXCLK_TMDS_ALWAYS_ONb);
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WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
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udelay(16000);
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mdelay(16);
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tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
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tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
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@ -2845,7 +2845,7 @@ bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
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case 4:
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val = RBIOS16(index);
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index += 2;
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udelay(val * 1000);
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mdelay(val);
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break;
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case 6:
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slave_addr = id & 0xff;
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@ -3044,7 +3044,7 @@ static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
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udelay(150);
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break;
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case 2:
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udelay(1000);
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mdelay(1);
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break;
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case 3:
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while (tmp--) {
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@ -3075,13 +3075,13 @@ static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
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/*mclk_cntl |= 0x00001111;*//* ??? */
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WREG32_PLL(RADEON_MCLK_CNTL,
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mclk_cntl);
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udelay(10000);
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mdelay(10);
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#endif
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WREG32_PLL
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(RADEON_CLK_PWRMGT_CNTL,
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tmp &
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~RADEON_CG_NO1_DEBUG_0);
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udelay(10000);
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mdelay(10);
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}
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break;
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default:
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@ -88,7 +88,7 @@ static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
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lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
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lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
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WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
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udelay(1000);
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mdelay(1);
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lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
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lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
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@ -101,7 +101,7 @@ static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
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(backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
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if (is_mac)
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lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
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udelay(panel_pwr_delay * 1000);
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mdelay(panel_pwr_delay);
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WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
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break;
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case DRM_MODE_DPMS_STANDBY:
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@ -118,10 +118,10 @@ static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
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WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
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lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
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}
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udelay(panel_pwr_delay * 1000);
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mdelay(panel_pwr_delay);
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WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
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WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
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udelay(panel_pwr_delay * 1000);
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mdelay(panel_pwr_delay);
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break;
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}
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@ -656,7 +656,7 @@ static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_enc
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WREG32(RADEON_DAC_MACRO_CNTL, tmp);
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udelay(2000);
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mdelay(2);
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if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
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found = connector_status_connected;
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@ -1499,7 +1499,7 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder
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tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
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WREG32(RADEON_DAC_CNTL2, tmp);
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udelay(10000);
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mdelay(10);
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if (ASIC_IS_R300(rdev)) {
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if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
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