Merge branch 'topic/mv_xor' into for-linus
Vinod Koul
commit
4dfc9afe0d
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@ -467,12 +467,90 @@ static int mv_xor_alloc_chan_resources(struct dma_chan *chan)
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return mv_chan->slots_allocated ? : -ENOMEM;
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}
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/*
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* Check if source or destination is an PCIe/IO address (non-SDRAM) and add
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* a new MBus window if necessary. Use a cache for these check so that
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* the MMIO mapped registers don't have to be accessed for this check
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* to speed up this process.
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*/
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static int mv_xor_add_io_win(struct mv_xor_chan *mv_chan, u32 addr)
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{
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struct mv_xor_device *xordev = mv_chan->xordev;
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void __iomem *base = mv_chan->mmr_high_base;
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u32 win_enable;
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u32 size;
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u8 target, attr;
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int ret;
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int i;
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/* Nothing needs to get done for the Armada 3700 */
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if (xordev->xor_type == XOR_ARMADA_37XX)
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return 0;
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/*
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* Loop over the cached windows to check, if the requested area
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* is already mapped. If this the case, nothing needs to be done
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* and we can return.
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*/
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for (i = 0; i < WINDOW_COUNT; i++) {
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if (addr >= xordev->win_start[i] &&
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addr <= xordev->win_end[i]) {
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/* Window is already mapped */
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return 0;
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}
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}
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/*
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* The window is not mapped, so we need to create the new mapping
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*/
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/* If no IO window is found that addr has to be located in SDRAM */
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ret = mvebu_mbus_get_io_win_info(addr, &size, &target, &attr);
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if (ret < 0)
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return 0;
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/*
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* Mask the base addr 'addr' according to 'size' read back from the
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* MBus window. Otherwise we might end up with an address located
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* somewhere in the middle of this area here.
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*/
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size -= 1;
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addr &= ~size;
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/*
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* Reading one of both enabled register is enough, as they are always
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* programmed to the identical values
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*/
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win_enable = readl(base + WINDOW_BAR_ENABLE(0));
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/* Set 'i' to the first free window to write the new values to */
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i = ffs(~win_enable) - 1;
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if (i >= WINDOW_COUNT)
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return -ENOMEM;
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writel((addr & 0xffff0000) | (attr << 8) | target,
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base + WINDOW_BASE(i));
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writel(size & 0xffff0000, base + WINDOW_SIZE(i));
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/* Fill the caching variables for later use */
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xordev->win_start[i] = addr;
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xordev->win_end[i] = addr + size;
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win_enable |= (1 << i);
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win_enable |= 3 << (16 + (2 * i));
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writel(win_enable, base + WINDOW_BAR_ENABLE(0));
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writel(win_enable, base + WINDOW_BAR_ENABLE(1));
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return 0;
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}
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static struct dma_async_tx_descriptor *
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mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
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unsigned int src_cnt, size_t len, unsigned long flags)
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{
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struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan);
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struct mv_xor_desc_slot *sw_desc;
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int ret;
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if (unlikely(len < MV_XOR_MIN_BYTE_COUNT))
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return NULL;
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@ -483,6 +561,11 @@ mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
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"%s src_cnt: %d len: %zu dest %pad flags: %ld\n",
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__func__, src_cnt, len, &dest, flags);
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/* Check if a new window needs to get added for 'dest' */
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ret = mv_xor_add_io_win(mv_chan, dest);
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if (ret)
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return NULL;
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sw_desc = mv_chan_alloc_slot(mv_chan);
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if (sw_desc) {
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sw_desc->type = DMA_XOR;
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@ -490,8 +573,13 @@ mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
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mv_desc_init(sw_desc, dest, len, flags);
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if (mv_chan->op_in_desc == XOR_MODE_IN_DESC)
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mv_desc_set_mode(sw_desc);
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while (src_cnt--)
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while (src_cnt--) {
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/* Check if a new window needs to get added for 'src' */
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ret = mv_xor_add_io_win(mv_chan, src[src_cnt]);
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if (ret)
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return NULL;
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mv_desc_set_src_addr(sw_desc, src_cnt, src[src_cnt]);
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}
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}
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dev_dbg(mv_chan_to_devp(mv_chan),
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@ -956,6 +1044,7 @@ mv_xor_channel_add(struct mv_xor_device *xordev,
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mv_chan->op_in_desc = XOR_MODE_IN_DESC;
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dma_dev = &mv_chan->dmadev;
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mv_chan->xordev = xordev;
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/*
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* These source and destination dummy buffers are used to implement
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@ -1083,6 +1172,10 @@ mv_xor_conf_mbus_windows(struct mv_xor_device *xordev,
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dram->mbus_dram_target_id, base + WINDOW_BASE(i));
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writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
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/* Fill the caching variables for later use */
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xordev->win_start[i] = cs->base;
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xordev->win_end[i] = cs->base + cs->size - 1;
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win_enable |= (1 << i);
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win_enable |= 3 << (16 + (2 * i));
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}
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@ -80,12 +80,17 @@
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#define WINDOW_BAR_ENABLE(chan) (0x40 + ((chan) << 2))
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#define WINDOW_OVERRIDE_CTRL(chan) (0xA0 + ((chan) << 2))
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#define WINDOW_COUNT 8
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struct mv_xor_device {
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void __iomem *xor_base;
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void __iomem *xor_high_base;
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struct clk *clk;
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struct mv_xor_chan *channels[MV_XOR_MAX_CHANNELS];
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int xor_type;
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u32 win_start[WINDOW_COUNT];
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u32 win_end[WINDOW_COUNT];
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};
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/**
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@ -127,6 +132,8 @@ struct mv_xor_chan {
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char dummy_dst[MV_XOR_MIN_BYTE_COUNT];
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dma_addr_t dummy_src_addr, dummy_dst_addr;
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u32 saved_config_reg, saved_int_mask_reg;
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struct mv_xor_device *xordev;
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};
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/**
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@ -11,6 +11,8 @@
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#ifndef __LINUX_MBUS_H
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#define __LINUX_MBUS_H
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#include <linux/errno.h>
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struct resource;
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struct mbus_dram_target_info
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@ -55,6 +57,8 @@ struct mbus_dram_target_info
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#ifdef CONFIG_PLAT_ORION
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extern const struct mbus_dram_target_info *mv_mbus_dram_info(void);
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extern const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void);
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int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
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u8 *attr);
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#else
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static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
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{
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@ -64,14 +68,24 @@ static inline const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(vo
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{
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return NULL;
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}
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static inline int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size,
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u8 *target, u8 *attr)
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{
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/*
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* On all ARM32 MVEBU platforms with MBus support, this stub
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* function will not get called. The real function from the
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* MBus driver is called instead. ARM64 MVEBU platforms like
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* the Armada 3700 could use the mv_xor device driver which calls
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* into this function
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*/
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return -EINVAL;
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}
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#endif
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int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr);
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void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
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void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
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int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr);
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int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
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u8 *attr);
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int mvebu_mbus_add_window_remap_by_id(unsigned int target,
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unsigned int attribute,
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phys_addr_t base, size_t size,
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