drm/armada: clean up SPU_ADV_REG
Rather than writing all bits of SPU_ADV_REG on modeset, only write what we need to change, and initialise the register in the variant initialisation. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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@ -27,6 +27,10 @@ static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev)
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/* Lower the watermark so to eliminate jitter at higher bandwidths */
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armada_updatel(0x20, (1 << 11) | 0xff, dcrtc->base + LCD_CFG_RDREG4F);
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/* Initialise SPU register */
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writel_relaxed(ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,
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dcrtc->base + LCD_SPU_ADV_REG);
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return 0;
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}
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@ -77,7 +81,6 @@ static int armada510_crtc_compute_clock(struct armada_crtc *dcrtc,
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const struct armada_variant armada510_ops = {
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.has_spu_adv_reg = true,
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.spu_adv_reg = ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,
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.init = armada510_crtc_init,
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.compute_clock = armada510_crtc_compute_clock,
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};
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@ -463,17 +463,15 @@ static void armada_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
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adj->crtc_htotal;
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dcrtc->v[1].spu_v_porch = tm << 16 | bm;
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val = adj->crtc_hsync_start;
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dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
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dcrtc->variant->spu_adv_reg;
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dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN;
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if (interlaced) {
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/* Odd interlaced frame */
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val -= adj->crtc_htotal / 2;
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dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN;
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dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
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(1 << 16);
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dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
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val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
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dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
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dcrtc->variant->spu_adv_reg;
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} else {
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dcrtc->v[0] = dcrtc->v[1];
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}
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@ -486,11 +484,10 @@ static void armada_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
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armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
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LCD_SPUT_V_H_TOTAL);
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if (dcrtc->variant->has_spu_adv_reg) {
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if (dcrtc->variant->has_spu_adv_reg)
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armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
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ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
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ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
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}
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val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
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armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
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@ -42,7 +42,6 @@ struct armada_private;
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struct armada_variant {
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bool has_spu_adv_reg;
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uint32_t spu_adv_reg;
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int (*init)(struct armada_crtc *, struct device *);
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int (*compute_clock)(struct armada_crtc *,
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const struct drm_display_mode *,
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