drm/radeon: put UVD PLLs in bypass mode
Just power down the PLL when we get a VCLK or DCLK of zero. Enabling the bypass mode early should also allow us to switch UVD clocks on the fly. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -189,6 +189,20 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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unsigned vco_freq;
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int r;
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/* bypass vclk and dclk with bclk */
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WREG32_P(CG_UPLL_FUNC_CNTL_2,
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VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
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~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
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/* put PLL in bypass mode */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
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if (!vclk || !dclk) {
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/* keep the Bypass mode, put PLL to sleep */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
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return 0;
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}
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/* loop through vco from low to high */
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for (vco_freq = 125000; vco_freq <= 250000; vco_freq += 100) {
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unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384;
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@ -236,14 +250,6 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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mdelay(1);
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/* bypass vclk and dclk with bclk */
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WREG32_P(CG_UPLL_FUNC_CNTL_2,
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VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
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~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
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/* put PLL in bypass mode */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
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r = evergreen_uvd_send_upll_ctlreq(rdev);
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if (r)
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return r;
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@ -100,6 +100,17 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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if (rdev->family == CHIP_RV740)
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return evergreen_set_uvd_clocks(rdev, vclk, dclk);
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/* bypass vclk and dclk with bclk */
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WREG32_P(CG_UPLL_FUNC_CNTL_2,
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VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
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~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
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if (!vclk || !dclk) {
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/* keep the Bypass mode, put PLL to sleep */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
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return 0;
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}
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/* loop through vco from low to high */
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vco_min = max(max(vco_min, vclk), dclk);
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for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 500) {
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@ -139,16 +150,11 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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}
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}
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/* bypass vclk and dclk with bclk */
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WREG32_P(CG_UPLL_FUNC_CNTL_2,
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VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
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~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
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/* set UPLL_FB_DIV to 0x50000 */
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WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
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/* deassert UPLL_RESET */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
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/* deassert UPLL_RESET and UPLL_SLEEP */
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WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));
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/* assert BYPASS EN and FB_DIV[0] <- ??? why? */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
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@ -4680,6 +4680,20 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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unsigned vco_freq;
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int r;
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/* bypass vclk and dclk with bclk */
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WREG32_P(CG_UPLL_FUNC_CNTL_2,
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VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
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~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
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/* put PLL in bypass mode */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
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if (!vclk || !dclk) {
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/* keep the Bypass mode, put PLL to sleep */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
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return 0;
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}
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/* loop through vco from low to high */
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for (vco_freq = 125000; vco_freq <= 250000; vco_freq += 100) {
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unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384;
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@ -4730,14 +4744,6 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
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mdelay(1);
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/* bypass vclk and dclk with bclk */
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WREG32_P(CG_UPLL_FUNC_CNTL_2,
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VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
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~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
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/* put PLL in bypass mode */
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WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
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r = si_uvd_send_upll_ctlreq(rdev);
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if (r)
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return r;
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