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Three fixes for the Qualcomm clk driver, two for regressions this merge 

window and one for a long standing problem that only popped up now that
 eMMC is being used.
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmBbg6ARHHNib3lkQGtl
 cm5lbC5vcmcACgkQrQKIl8bklSUSnBAAz9crwEFRI5iZu+yubSStfNCNdXbH6eev
 UEMfi0G21EodS5D5qG2YcPmT4gDkpdkMGO/UosJWrTeFA09dImmmj0TeQ8S2KwHH
 GcOfoWCnMkC/qg/v8aSLVtbj6IORup/fq+oMyd9LdNRcNXg5DZrifzoJWcCXpXMX
 Q1dLYj1aL/JeLh842HxUH0YQI7CxlO/R2hLhYmCjO/ZFHDWpBUbjefv79P40ykV/
 jjCrU1roNPJipmS40puYbyMvPQTaGcXKAKq9n+fdBzuFUP5Sp4/bNPgA3rGO6ABw
 bSenFTfEuvEvSLds6oczSZk/hRhpBmcd865ryLG9ZiAerDX9cb21us0kIkvI6hwZ
 ywLzqRbWDPBrxXHZuUzoLbu4yIqY5wGCqpLmxH5CYoGcit7edlkdnaJPTCXBIen7
 +whoapOFGf5Mgh6hi7zKR9m53GtKTUt5MScVx3nk/iBmQ+OPKQ+DnukhYXXXggEj
 E7XzF8RWqEMMHd//V39RSAAJqNCS7K1t8XKpr0wYc1FP8YsPoiHP/tMNFnqoeptY
 hBQunoVkrDLIyKm/bL3VWFUJaOqEZajkrTvG9jKry+mzIVFjCboNFwDMZ5srEWuu
 XzqdoVvQEjOh1arLdK2KY2Y9xGPQAM/nrIMY8h/6CLHB10tniEP+Dl5y1r1yxtn3
 SJTAjGvN8GQ=
 =e9G9
 -----END PGP SIGNATURE-----

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "Three fixes for the Qualcomm clk driver: two for regressions this
  merge window and one for a long-standing problem that only popped up
  now that eMMC is being used"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: qcom: gcc-sc7180: Use floor ops for the correct sdcc1 clk
  clk: qcom: rcg2: Rectify clk_gfx3d rate rounding without mux division
  clk: qcom: rpmh: Update the XO clock source for SC7280
rM2-mainline
Linus Torvalds 2021-03-24 11:26:50 -07:00
parent a0a4df6a9e 148ddaa89d
commit 4ee998b0ef
3 changed files with 16 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/clk/qcom/clk-rcg2.c
View File

@ -730,7 +730,8 @@ static int clk_gfx3d_determine_rate(struct clk_hw *hw,
struct clk_rate_request parent_req = { };
struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw);
struct clk_hw *xo, *p0, *p1, *p2;
unsigned long request, p0_rate;
unsigned long p0_rate;
u8 mux_div = cgfx->div;
int ret;
p0 = cgfx->hws[0];
@ -750,14 +751,15 @@ static int clk_gfx3d_determine_rate(struct clk_hw *hw,
return 0;
}
request = req->rate;
if (cgfx->div > 1)
parent_req.rate = request = request * cgfx->div;
if (mux_div == 0)
mux_div = 1;
parent_req.rate = req->rate * mux_div;
/* This has to be a fixed rate PLL */
p0_rate = clk_hw_get_rate(p0);
if (request == p0_rate) {
if (parent_req.rate == p0_rate) {
req->rate = req->best_parent_rate = p0_rate;
req->best_parent_hw = p0;
return 0;
@ -765,7 +767,7 @@ static int clk_gfx3d_determine_rate(struct clk_hw *hw,
if (req->best_parent_hw == p0) {
/* Are we going back to a previously used rate? */
if (clk_hw_get_rate(p2) == request)
if (clk_hw_get_rate(p2) == parent_req.rate)
req->best_parent_hw = p2;
else
req->best_parent_hw = p1;
@ -780,8 +782,7 @@ static int clk_gfx3d_determine_rate(struct clk_hw *hw,
return ret;
req->rate = req->best_parent_rate = parent_req.rate;
if (cgfx->div > 1)
req->rate /= cgfx->div;
req->rate /= mux_div;
return 0;
}

7
drivers/clk/qcom/clk-rpmh.c
View File

@ -510,9 +510,12 @@ static const struct clk_rpmh_desc clk_rpmh_sm8350 = {
.num_clks = ARRAY_SIZE(sm8350_rpmh_clocks),
};
/* Resource name must match resource id present in cmd-db */
DEFINE_CLK_RPMH_ARC(sc7280, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 4);
static struct clk_hw *sc7280_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
[RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
[RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
[RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
[RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,

4
drivers/clk/qcom/gcc-sc7180.c
View File

@ -620,7 +620,7 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = 5,
.ops = &clk_rcg2_ops,
.ops = &clk_rcg2_floor_ops,
},
};
@ -642,7 +642,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
.name = "gcc_sdcc1_ice_core_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = 4,
.ops = &clk_rcg2_floor_ops,
.ops = &clk_rcg2_ops,
},
};