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drm/amd/powerplay: update ppatomctrl.c (v2) 

used for calculating memory clocks in powerplay.

v2: handle endian swapping of atom data (Alex)

Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hifive-unleashed-5.1
Eric Huang 2017-11-17 11:21:02 -05:00 committed by Alex Deucher
parent ee38fbf3bf
commit 4eeed17e71
2 changed files with 41 additions and 0 deletions
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31
drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c
View File

@ -23,6 +23,7 @@
#include "pp_debug.h"
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include "atom.h"
#include "ppatomctrl.h"
#include "atombios.h"
@ -314,6 +315,36 @@ int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
return result;
}
int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr,
uint32_t clock_value,
pp_atomctrl_memory_clock_param_ai *mpll_param)
{
struct amdgpu_device *adev = hwmgr->adev;
COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 mpll_parameters = {0};
int result;
mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value);
result = amdgpu_atom_execute_table(adev->mode_info.atom_context,
GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam),
(uint32_t *)&mpll_parameters);
/* VEGAM's mpll takes sometime to finish computing */
udelay(10);
if (!result) {
mpll_param->ulMclk_fcw_int =
le16_to_cpu(mpll_parameters.usMclk_fcw_int);
mpll_param->ulMclk_fcw_frac =
le16_to_cpu(mpll_parameters.usMclk_fcw_frac);
mpll_param->ulClock =
le32_to_cpu(mpll_parameters.ulClock.ulClock);
mpll_param->ulPostDiv = mpll_parameters.ulClock.ucPostDiv;
}
return result;
}
int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
uint32_t clock_value,
pp_atomctrl_clock_dividers_kong *dividers)

10
drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h
View File

@ -146,6 +146,14 @@ struct pp_atomctrl_memory_clock_param {
};
typedef struct pp_atomctrl_memory_clock_param pp_atomctrl_memory_clock_param;
struct pp_atomctrl_memory_clock_param_ai {
uint32_t ulClock;
uint32_t ulPostDiv;
uint16_t ulMclk_fcw_frac;
uint16_t ulMclk_fcw_int;
};
typedef struct pp_atomctrl_memory_clock_param_ai pp_atomctrl_memory_clock_param_ai;
struct pp_atomctrl_internal_ss_info {
uint32_t speed_spectrum_percentage; /* in 1/100 percentage */
uint32_t speed_spectrum_rate; /* in KHz */
@ -295,6 +303,8 @@ extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, ui
extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);
extern int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr,
uint32_t clock_value, pp_atomctrl_memory_clock_param_ai *mpll_param);
extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
uint32_t clock_value,
pp_atomctrl_clock_dividers_kong *dividers);