drm/radeon: fix const IB handling v2
Const IBs are executed on the CE not the CP, so we can't fence them in the normal way. So submit them directly before the IB instead, just as the documentation says. v2: keep the extra documentation Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3693,7 +3693,7 @@ int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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ib.ptr[6] = PACKET2(0);
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ib.ptr[7] = PACKET2(0);
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ib.length_dw = 8;
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r = radeon_ib_schedule(rdev, &ib);
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r = radeon_ib_schedule(rdev, &ib, NULL);
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if (r) {
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radeon_scratch_free(rdev, scratch);
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radeon_ib_free(rdev, &ib);
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@ -2619,7 +2619,7 @@ int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
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ib.ptr[2] = 0xDEADBEEF;
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ib.length_dw = 3;
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r = radeon_ib_schedule(rdev, &ib);
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r = radeon_ib_schedule(rdev, &ib, NULL);
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if (r) {
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radeon_scratch_free(rdev, scratch);
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radeon_ib_free(rdev, &ib);
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@ -751,7 +751,8 @@ struct si_rlc {
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int radeon_ib_get(struct radeon_device *rdev, int ring,
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struct radeon_ib *ib, unsigned size);
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void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
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int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
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int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
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struct radeon_ib *const_ib);
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int radeon_ib_pool_init(struct radeon_device *rdev);
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void radeon_ib_pool_fini(struct radeon_device *rdev);
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int radeon_ib_ring_tests(struct radeon_device *rdev);
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@ -354,7 +354,7 @@ static int radeon_cs_ib_chunk(struct radeon_device *rdev,
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}
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radeon_cs_sync_rings(parser);
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parser->ib.vm_id = 0;
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r = radeon_ib_schedule(rdev, &parser->ib);
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r = radeon_ib_schedule(rdev, &parser->ib, NULL);
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if (r) {
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DRM_ERROR("Failed to schedule IB !\n");
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}
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@ -452,25 +452,24 @@ static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
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}
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radeon_cs_sync_rings(parser);
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parser->ib.vm_id = vm->id;
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/* ib pool is bind at 0 in virtual address space,
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* so gpu_addr is the offset inside the pool bo
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*/
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parser->ib.gpu_addr = parser->ib.sa_bo->soffset;
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if ((rdev->family >= CHIP_TAHITI) &&
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(parser->chunk_const_ib_idx != -1)) {
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parser->const_ib.vm_id = vm->id;
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/* ib pool is bind at 0 in virtual address space to gpu_addr is the
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* offset inside the pool bo
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/* ib pool is bind at 0 in virtual address space,
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* so gpu_addr is the offset inside the pool bo
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*/
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parser->const_ib.gpu_addr = parser->const_ib.sa_bo->soffset;
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r = radeon_ib_schedule(rdev, &parser->const_ib);
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if (r)
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goto out;
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r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
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} else {
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r = radeon_ib_schedule(rdev, &parser->ib, NULL);
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}
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parser->ib.vm_id = vm->id;
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/* ib pool is bind at 0 in virtual address space to gpu_addr is the
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* offset inside the pool bo
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*/
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parser->ib.gpu_addr = parser->ib.sa_bo->soffset;
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parser->ib.is_const_ib = false;
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r = radeon_ib_schedule(rdev, &parser->ib);
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out:
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if (!r) {
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if (vm->fence) {
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@ -74,7 +74,8 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
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radeon_fence_unref(&ib->fence);
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}
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int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
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int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
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struct radeon_ib *const_ib)
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{
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struct radeon_ring *ring = &rdev->ring[ib->ring];
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bool need_sync = false;
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@ -105,6 +106,10 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
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if (!need_sync) {
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radeon_semaphore_free(rdev, &ib->semaphore, NULL);
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}
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if (const_ib) {
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radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
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radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);
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}
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radeon_ring_ib_execute(rdev, ib->ring, ib);
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r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
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if (r) {
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@ -112,6 +117,9 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
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radeon_ring_unlock_undo(rdev, ring);
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return r;
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}
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if (const_ib) {
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const_ib->fence = radeon_fence_ref(ib->fence);
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}
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radeon_ring_unlock_commit(rdev, ring);
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return 0;
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}
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