crypto: caam - add crypto_engine support for HASH algorithms
Add crypto_engine support for HASH algorithms, to make use of
the engine queue.
The requests, with backlog flag, will be listed into crypto-engine
queue and processed by CAAM when free.
Only the backlog request are sent to crypto-engine since the others
can be handled by CAAM, if free, especially since JR has up to 1024
entries (more than the 10 entries from crypto-engine).
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
(cherry picked from commit 21b014f038)
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Iuliana Prodan
parent
5c868ea249
commit
4f0ce1c618
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@ -65,6 +65,7 @@
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#include "sg_sw_sec4.h"
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#include "key_gen.h"
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#include "caamhash_desc.h"
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#include <crypto/engine.h>
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#define CAAM_CRA_PRIORITY 3000
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@ -86,6 +87,7 @@ static struct list_head hash_list;
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/* ahash per-session context */
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struct caam_hash_ctx {
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struct crypto_engine_ctx enginectx;
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u32 sh_desc_update[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
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u32 sh_desc_update_first[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
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u32 sh_desc_fin[DESC_HASH_MAX_USED_LEN] ____cacheline_aligned;
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@ -112,10 +114,13 @@ struct caam_hash_state {
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u8 buf_1[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
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int buflen_1;
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u8 caam_ctx[MAX_CTX_LEN] ____cacheline_aligned;
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int (*update)(struct ahash_request *req);
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int (*update)(struct ahash_request *req) ____cacheline_aligned;
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int (*final)(struct ahash_request *req);
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int (*finup)(struct ahash_request *req);
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int current_buf;
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struct ahash_edesc *edesc;
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void (*ahash_op_done)(struct device *jrdev, u32 *desc, u32 err,
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void *context);
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};
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struct caam_export_state {
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@ -553,6 +558,7 @@ static int acmac_setkey(struct crypto_ahash *ahash, const u8 *key,
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* @sec4_sg_dma: physical mapped address of h/w link table
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* @src_nents: number of segments in input scatterlist
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* @sec4_sg_bytes: length of dma mapped sec4_sg space
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* @bklog: stored to determine if the request needs backlog
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* @hw_desc: the h/w job descriptor followed by any referenced link tables
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* @sec4_sg: h/w link table
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*/
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@ -560,6 +566,7 @@ struct ahash_edesc {
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dma_addr_t sec4_sg_dma;
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int src_nents;
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int sec4_sg_bytes;
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bool bklog;
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u32 hw_desc[DESC_JOB_IO_LEN_MAX / sizeof(u32)] ____cacheline_aligned;
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struct sec4_sg_entry sec4_sg[0];
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};
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@ -601,6 +608,7 @@ static inline void ahash_done_cpy(struct device *jrdev, u32 *desc, u32 err,
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void *context, enum dma_data_direction dir)
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{
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struct ahash_request *req = context;
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struct caam_drv_private_jr *jrp = dev_get_drvdata(jrdev);
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struct ahash_edesc *edesc;
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struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
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int digestsize = crypto_ahash_digestsize(ahash);
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@ -610,7 +618,8 @@ static inline void ahash_done_cpy(struct device *jrdev, u32 *desc, u32 err,
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dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
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edesc = container_of(desc, struct ahash_edesc, hw_desc[0]);
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edesc = state->edesc;
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if (err)
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ecode = caam_jr_strstatus(jrdev, err);
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@ -622,7 +631,14 @@ static inline void ahash_done_cpy(struct device *jrdev, u32 *desc, u32 err,
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DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
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ctx->ctx_len, 1);
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req->base.complete(&req->base, ecode);
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/*
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* If no backlog flag, the completion of the request is done
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* by CAAM, not crypto engine.
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*/
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if (!edesc->bklog)
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req->base.complete(&req->base, ecode);
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else
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crypto_finalize_hash_request(jrp->engine, req, ecode);
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}
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static void ahash_done(struct device *jrdev, u32 *desc, u32 err,
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@ -641,6 +657,7 @@ static inline void ahash_done_switch(struct device *jrdev, u32 *desc, u32 err,
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void *context, enum dma_data_direction dir)
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{
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struct ahash_request *req = context;
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struct caam_drv_private_jr *jrp = dev_get_drvdata(jrdev);
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struct ahash_edesc *edesc;
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struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
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struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
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@ -650,7 +667,7 @@ static inline void ahash_done_switch(struct device *jrdev, u32 *desc, u32 err,
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dev_dbg(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
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edesc = container_of(desc, struct ahash_edesc, hw_desc[0]);
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edesc = state->edesc;
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if (err)
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ecode = caam_jr_strstatus(jrdev, err);
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@ -666,7 +683,15 @@ static inline void ahash_done_switch(struct device *jrdev, u32 *desc, u32 err,
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DUMP_PREFIX_ADDRESS, 16, 4, req->result,
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digestsize, 1);
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req->base.complete(&req->base, ecode);
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/*
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* If no backlog flag, the completion of the request is done
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* by CAAM, not crypto engine.
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*/
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if (!edesc->bklog)
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req->base.complete(&req->base, ecode);
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else
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crypto_finalize_hash_request(jrp->engine, req, ecode);
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}
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static void ahash_done_bi(struct device *jrdev, u32 *desc, u32 err,
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@ -691,6 +716,7 @@ static struct ahash_edesc *ahash_edesc_alloc(struct ahash_request *req,
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{
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struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
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struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
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struct caam_hash_state *state = ahash_request_ctx(req);
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gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
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GFP_KERNEL : GFP_ATOMIC;
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struct ahash_edesc *edesc;
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@ -702,6 +728,8 @@ static struct ahash_edesc *ahash_edesc_alloc(struct ahash_request *req,
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return NULL;
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}
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state->edesc = edesc;
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init_job_desc_shared(edesc->hw_desc, sh_desc_dma, desc_len(sh_desc),
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HDR_SHARE_DEFER | HDR_REVERSE);
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@ -744,6 +772,62 @@ static int ahash_edesc_add_src(struct caam_hash_ctx *ctx,
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return 0;
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}
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static int ahash_do_one_req(struct crypto_engine *engine, void *areq)
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{
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struct ahash_request *req = ahash_request_cast(areq);
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struct caam_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
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struct caam_hash_state *state = ahash_request_ctx(req);
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struct device *jrdev = ctx->jrdev;
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u32 *desc = state->edesc->hw_desc;
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int ret;
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state->edesc->bklog = true;
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ret = caam_jr_enqueue(jrdev, desc, state->ahash_op_done, req);
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if (ret != -EINPROGRESS) {
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ahash_unmap(jrdev, state->edesc, req, 0);
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kfree(state->edesc);
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} else {
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ret = 0;
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}
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return ret;
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}
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static int ahash_enqueue_req(struct device *jrdev,
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void (*cbk)(struct device *jrdev, u32 *desc,
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u32 err, void *context),
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struct ahash_request *req,
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int dst_len, enum dma_data_direction dir)
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{
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struct caam_drv_private_jr *jrpriv = dev_get_drvdata(jrdev);
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struct caam_hash_state *state = ahash_request_ctx(req);
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struct ahash_edesc *edesc = state->edesc;
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u32 *desc = edesc->hw_desc;
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int ret;
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state->ahash_op_done = cbk;
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/*
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* Only the backlog request are sent to crypto-engine since the others
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* can be handled by CAAM, if free, especially since JR has up to 1024
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* entries (more than the 10 entries from crypto-engine).
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*/
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if (req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)
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ret = crypto_transfer_hash_request_to_engine(jrpriv->engine,
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req);
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else
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ret = caam_jr_enqueue(jrdev, desc, cbk, req);
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if ((ret != -EINPROGRESS) && (ret != -EBUSY)) {
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ahash_unmap_ctx(jrdev, edesc, req, dst_len, dir);
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kfree(edesc);
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}
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return ret;
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}
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/* submit update job descriptor */
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static int ahash_update_ctx(struct ahash_request *req)
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{
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@ -857,9 +941,8 @@ static int ahash_update_ctx(struct ahash_request *req)
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DUMP_PREFIX_ADDRESS, 16, 4, desc,
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desc_bytes(desc), 1);
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ret = caam_jr_enqueue(jrdev, desc, ahash_done_bi, req);
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if (ret != -EINPROGRESS)
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goto unmap_ctx;
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ret = ahash_enqueue_req(jrdev, ahash_done_bi, req,
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ctx->ctx_len, DMA_BIDIRECTIONAL);
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} else if (*next_buflen) {
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scatterwalk_map_and_copy(buf + *buflen, req->src, 0,
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req->nbytes, 0);
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@ -933,10 +1016,8 @@ static int ahash_final_ctx(struct ahash_request *req)
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DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc),
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1);
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ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_src, req);
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if (ret == -EINPROGRESS)
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return ret;
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return ahash_enqueue_req(jrdev, ahash_done_ctx_src, req,
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digestsize, DMA_BIDIRECTIONAL);
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unmap_ctx:
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ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_BIDIRECTIONAL);
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kfree(edesc);
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@ -1009,10 +1090,8 @@ static int ahash_finup_ctx(struct ahash_request *req)
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DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc),
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1);
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ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_src, req);
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if (ret == -EINPROGRESS)
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return ret;
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return ahash_enqueue_req(jrdev, ahash_done_ctx_src, req,
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digestsize, DMA_BIDIRECTIONAL);
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unmap_ctx:
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ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_BIDIRECTIONAL);
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kfree(edesc);
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@ -1081,13 +1160,8 @@ static int ahash_digest(struct ahash_request *req)
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DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc),
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1);
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ret = caam_jr_enqueue(jrdev, desc, ahash_done, req);
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if (ret != -EINPROGRESS) {
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ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_FROM_DEVICE);
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kfree(edesc);
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}
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return ret;
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return ahash_enqueue_req(jrdev, ahash_done, req, digestsize,
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DMA_FROM_DEVICE);
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}
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/* submit ahash final if it the first job descriptor */
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@ -1131,18 +1205,12 @@ static int ahash_final_no_ctx(struct ahash_request *req)
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DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc),
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1);
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ret = caam_jr_enqueue(jrdev, desc, ahash_done, req);
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if (ret != -EINPROGRESS) {
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ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_FROM_DEVICE);
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kfree(edesc);
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}
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return ret;
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return ahash_enqueue_req(jrdev, ahash_done, req,
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digestsize, DMA_FROM_DEVICE);
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unmap:
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ahash_unmap(jrdev, edesc, req, digestsize);
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kfree(edesc);
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return -ENOMEM;
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}
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/* submit ahash update if it the first job descriptor after update */
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@ -1249,10 +1317,10 @@ static int ahash_update_no_ctx(struct ahash_request *req)
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DUMP_PREFIX_ADDRESS, 16, 4, desc,
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desc_bytes(desc), 1);
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ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_dst, req);
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if (ret != -EINPROGRESS)
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goto unmap_ctx;
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ret = ahash_enqueue_req(jrdev, ahash_done_ctx_dst, req,
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ctx->ctx_len, DMA_TO_DEVICE);
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if ((ret != -EINPROGRESS) && (ret != -EBUSY))
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return ret;
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state->update = ahash_update_ctx;
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state->finup = ahash_finup_ctx;
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state->final = ahash_final_ctx;
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@ -1343,13 +1411,8 @@ static int ahash_finup_no_ctx(struct ahash_request *req)
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DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc),
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1);
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ret = caam_jr_enqueue(jrdev, desc, ahash_done, req);
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if (ret != -EINPROGRESS) {
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ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_FROM_DEVICE);
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kfree(edesc);
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}
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return ret;
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return ahash_enqueue_req(jrdev, ahash_done, req,
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digestsize, DMA_FROM_DEVICE);
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unmap:
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ahash_unmap(jrdev, edesc, req, digestsize);
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kfree(edesc);
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@ -1440,10 +1503,10 @@ static int ahash_update_first(struct ahash_request *req)
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DUMP_PREFIX_ADDRESS, 16, 4, desc,
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desc_bytes(desc), 1);
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ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_dst, req);
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if (ret != -EINPROGRESS)
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goto unmap_ctx;
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ret = ahash_enqueue_req(jrdev, ahash_done_ctx_dst, req,
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ctx->ctx_len, DMA_TO_DEVICE);
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if ((ret != -EINPROGRESS) && (ret != -EBUSY))
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return ret;
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state->update = ahash_update_ctx;
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state->finup = ahash_finup_ctx;
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state->final = ahash_final_ctx;
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@ -1755,6 +1818,8 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm)
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HASH_MSG_LEN + SHA256_DIGEST_SIZE,
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HASH_MSG_LEN + 64,
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HASH_MSG_LEN + SHA512_DIGEST_SIZE };
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const size_t sh_desc_update_offset = offsetof(struct caam_hash_ctx,
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sh_desc_update);
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dma_addr_t dma_addr;
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struct caam_drv_private *priv;
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@ -1807,7 +1872,8 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm)
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}
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dma_addr = dma_map_single_attrs(ctx->jrdev, ctx->sh_desc_update,
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offsetof(struct caam_hash_ctx, key),
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offsetof(struct caam_hash_ctx, key) -
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sh_desc_update_offset,
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ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
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if (dma_mapping_error(ctx->jrdev, dma_addr)) {
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dev_err(ctx->jrdev, "unable to map shared descriptors\n");
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@ -1825,11 +1891,16 @@ static int caam_hash_cra_init(struct crypto_tfm *tfm)
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ctx->sh_desc_update_dma = dma_addr;
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ctx->sh_desc_update_first_dma = dma_addr +
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offsetof(struct caam_hash_ctx,
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sh_desc_update_first);
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sh_desc_update_first) -
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sh_desc_update_offset;
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ctx->sh_desc_fin_dma = dma_addr + offsetof(struct caam_hash_ctx,
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sh_desc_fin);
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sh_desc_fin) -
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sh_desc_update_offset;
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ctx->sh_desc_digest_dma = dma_addr + offsetof(struct caam_hash_ctx,
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sh_desc_digest);
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sh_desc_digest) -
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sh_desc_update_offset;
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ctx->enginectx.op.do_one_request = ahash_do_one_req;
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crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
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sizeof(struct caam_hash_state));
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@ -1846,7 +1917,8 @@ static void caam_hash_cra_exit(struct crypto_tfm *tfm)
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struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
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dma_unmap_single_attrs(ctx->jrdev, ctx->sh_desc_update_dma,
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offsetof(struct caam_hash_ctx, key),
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offsetof(struct caam_hash_ctx, key) -
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offsetof(struct caam_hash_ctx, sh_desc_update),
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ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
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if (ctx->key_dir != DMA_NONE)
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dma_unmap_single_attrs(ctx->jrdev, ctx->adata.key_dma,
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