serial: pl011: implement workaround for CTS clear event issue
Problem Observed:
- interrupt status is set by rising or falling edge on CTS line
- interrupt status is cleared on a .0. to .1. transition of the
interrupt-clear register bit 1.
- interrupt-clear register is reset by hardware once the interrupt
status is .0..
Remark: It seems not possible to read this register back by the
CPU though, but internally this register exists.
- when simultaneous set and reset event on the interrupt status
happens, then the set-event has priority and the status remains
.1.. As a result the interrupt-clear register is not reset to
.0., and no new .0. to .1. transition can be detected on it when
writing a .1. to it.
This implies race condition, the clear must be performed at least
one UARTCLK the riding edge of CTS RIS interrupt.
Fix:
Instead of resetting UART as done in commit
c16d51a32b
"amba pl011: workaround for uart registers lockup" do the
following:
write .0. and then .1. to the interrupt-clear register to make
sure that this transition is detected. According to the datasheet
writing a .0. does not have any effect, but actually it allows to
reset the internal interrupt-clear register.
Take into account:
The .0. needs to last at least for one clk_uart clock period
(~ 38 MHz, 26.08ns)
This way we can do away with the tasklet and keep only a tiny
fix triggered by the variant flag introduced in this patch.
Signed-off-by: Guillaume Jaunet <guillaume.jaunet@stericsson.com>
Signed-off-by: Christophe Arnal <christophe.arnal@stericsson.com>
Signed-off-by: Matthias Locher <Matthias.Locher@stericsson.com>
Signed-off-by: Rajanikanth H.V <rajanikanth.hv@stericsson.com>
Reviewed-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
hifive-unleashed-5.1
Rajanikanth H.V
Greg Kroah-Hartman
parent
e695b28664
commit
4fd0690bb0
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@ -67,30 +67,6 @@
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#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
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#define UART_DUMMY_DR_RX (1 << 16)
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#define UART_WA_SAVE_NR 14
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static void pl011_lockup_wa(unsigned long data);
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static const u32 uart_wa_reg[UART_WA_SAVE_NR] = {
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ST_UART011_DMAWM,
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ST_UART011_TIMEOUT,
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ST_UART011_LCRH_RX,
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UART011_IBRD,
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UART011_FBRD,
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ST_UART011_LCRH_TX,
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UART011_IFLS,
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ST_UART011_XFCR,
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ST_UART011_XON1,
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ST_UART011_XON2,
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ST_UART011_XOFF1,
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ST_UART011_XOFF2,
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UART011_CR,
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UART011_IMSC
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};
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static u32 uart_wa_regdata[UART_WA_SAVE_NR];
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static DECLARE_TASKLET(pl011_lockup_tlet, pl011_lockup_wa, 0);
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/* There is by now at least one vendor with differing details, so handle it */
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struct vendor_data {
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unsigned int ifls;
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@ -100,6 +76,7 @@ struct vendor_data {
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bool oversampling;
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bool interrupt_may_hang; /* vendor-specific */
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bool dma_threshold;
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bool cts_event_workaround;
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};
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static struct vendor_data vendor_arm = {
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@ -109,6 +86,7 @@ static struct vendor_data vendor_arm = {
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.lcrh_rx = UART011_LCRH,
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.oversampling = false,
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.dma_threshold = false,
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.cts_event_workaround = false,
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};
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static struct vendor_data vendor_st = {
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@ -119,6 +97,7 @@ static struct vendor_data vendor_st = {
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.oversampling = true,
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.interrupt_may_hang = true,
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.dma_threshold = true,
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.cts_event_workaround = true,
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};
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static struct uart_amba_port *amba_ports[UART_NR];
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@ -1054,69 +1033,6 @@ static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
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#define pl011_dma_flush_buffer NULL
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#endif
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/*
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* pl011_lockup_wa
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* This workaround aims to break the deadlock situation
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* when after long transfer over uart in hardware flow
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* control, uart interrupt registers cannot be cleared.
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* Hence uart transfer gets blocked.
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*
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* It is seen that during such deadlock condition ICR
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* don't get cleared even on multiple write. This leads
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* pass_counter to decrease and finally reach zero. This
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* can be taken as trigger point to run this UART_BT_WA.
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*
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*/
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static void pl011_lockup_wa(unsigned long data)
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{
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struct uart_amba_port *uap = amba_ports[0];
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void __iomem *base = uap->port.membase;
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struct circ_buf *xmit = &uap->port.state->xmit;
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struct tty_struct *tty = uap->port.state->port.tty;
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int buf_empty_retries = 200;
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int loop;
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/* Stop HCI layer from submitting data for tx */
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tty->hw_stopped = 1;
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while (!uart_circ_empty(xmit)) {
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if (buf_empty_retries-- == 0)
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break;
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udelay(100);
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}
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/* Backup registers */
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for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
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uart_wa_regdata[loop] = readl(base + uart_wa_reg[loop]);
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/* Disable UART so that FIFO data is flushed out */
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writew(0x00, uap->port.membase + UART011_CR);
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/* Soft reset UART module */
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if (uap->port.dev->platform_data) {
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struct amba_pl011_data *plat;
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plat = uap->port.dev->platform_data;
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if (plat->reset)
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plat->reset();
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}
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/* Restore registers */
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for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
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writew(uart_wa_regdata[loop] ,
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uap->port.membase + uart_wa_reg[loop]);
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/* Initialise the old status of the modem signals */
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uap->old_status = readw(uap->port.membase + UART01x_FR) &
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UART01x_FR_MODEM_ANY;
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if (readl(base + UART011_MIS) & 0x2)
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printk(KERN_EMERG "UART_BT_WA: ***FAILED***\n");
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/* Start Tx/Rx */
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tty->hw_stopped = 0;
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}
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static void pl011_stop_tx(struct uart_port *port)
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{
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struct uart_amba_port *uap = (struct uart_amba_port *)port;
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@ -1245,12 +1161,26 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
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unsigned long flags;
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unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
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int handled = 0;
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unsigned int dummy_read;
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spin_lock_irqsave(&uap->port.lock, flags);
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status = readw(uap->port.membase + UART011_MIS);
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if (status) {
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do {
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if (uap->vendor->cts_event_workaround) {
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/* workaround to make sure that all bits are unlocked.. */
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writew(0x00, uap->port.membase + UART011_ICR);
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/*
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* WA: introduce 26ns(1 uart clk) delay before W1C;
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* single apb access will incur 2 pclk(133.12Mhz) delay,
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* so add 2 dummy reads
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*/
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dummy_read = readw(uap->port.membase + UART011_ICR);
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dummy_read = readw(uap->port.membase + UART011_ICR);
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}
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writew(status & ~(UART011_TXIS|UART011_RTIS|
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UART011_RXIS),
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uap->port.membase + UART011_ICR);
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@ -1267,11 +1197,8 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
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if (status & UART011_TXIS)
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pl011_tx_chars(uap);
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if (pass_counter-- == 0) {
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if (uap->interrupt_may_hang)
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tasklet_schedule(&pl011_lockup_tlet);
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if (pass_counter-- == 0)
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break;
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}
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status = readw(uap->port.membase + UART011_MIS);
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} while (status != 0);
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