Renesas ARM based SoC updates for v3.13
* Add support for r8a7791 SoC * Rename DU device in clock lookups list of r8a7779 SoC * USB and SSI/SRU clock support for r8a7778 SoC * USB phy power control function support for r8a7778 SoC -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJSSSgvAAoJENfPZGlqN0++QqkP/2qVDvTbeSNq0KpG6nLekj9J lNl5A5H78q1KxNWMXjxuxU/sTTnEHug0dFXpXTawk4AuunD4hELSaFcqDQc/UKTx yeSX296yhDDTQo/ZlwwSTLTXI696rYX+WliQ4GgaYEY+Ssl2WtzjML9YI4G+BuO2 DwuBIvbo8V0JLxdoMLFqHAkQiqHFVJlWrnYa4Yp+re5IUzUIbUheHHn2Wu5XjwoJ BzN+Scsm1uGxSvMXzQ1AwJNBGJpjUQFK353Hp7g54L1kZ/0d9yP9oO5+/7b8r3ev O2diXHzfwdE9/rTONeLs/B/KpEB6KhIMTqwsdDWijfhIbofRJ8mLj074Abh4zqra NQTMRX4HfI9qmQrVZFRatKvcR/PgRofSNNaoiIz2Flp0uh8bAgDxTjGegDQUSkyo l6vTA+Bfrw2LNlvhZLPB8VrlHNJAoP5XgdObUjswFMtwP0E1upx1YW50naVp3Ear otz700svMBRXqAs6mPsXkgLk/ueqbuPANc26+AHr2q8psOFpcZQKROrHRrxyPxVl 4ZqgEssDB9534A6nct1B0u0eB9pCb95ZcZjuOtdEApXH7hkwp+N40u2orWkSvjhO cQBdclyk1f9SDVlRVbl5p/iXSUxa3za6dObDKKHSb8OWAOKINIKRcmHEaXtWJycs yobGmXG8yyAyImBTKxHg =GB2b -----END PGP SIGNATURE----- Merge tag 'renesas-soc-for-v3.13' into dt2-base Renesas ARM based SoC updates for v3.13 * Add support for r8a7791 SoC * Rename DU device in clock lookups list of r8a7779 SoC * USB and SSI/SRU clock support for r8a7778 SoC * USB phy power control function support for r8a7778 SoChifive-unleashed-5.1
Simon Horman
commit
50128df2c0
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@ -0,0 +1,41 @@
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/*
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* Device Tree Source for the r8a7791 SoC
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2013 Renesas Solutions Corp.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/ {
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compatible = "renesas,r8a7791";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1300000000>;
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};
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>,
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<0 0xf1002000 0 0x1000>,
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<0 0xf1004000 0 0x2000>,
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<0 0xf1006000 0 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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};
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@ -101,6 +101,12 @@ config ARCH_R8A7790
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select SH_CLK_CPG
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select RENESAS_IRQC
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config ARCH_R8A7791
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bool "R-Car M2 (R8A77910)"
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select ARM_GIC
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select CPU_V7
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select SH_CLK_CPG
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config ARCH_EMEV2
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bool "Emma Mobile EV2"
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select ARCH_WANT_OPTIONAL_GPIOLIB
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@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o
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obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o
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obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o
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obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o
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obj-$(CONFIG_ARCH_R8A7791) += setup-r8a7791.o
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obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o
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# Clock objects
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@ -27,6 +28,7 @@ obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o
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obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
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obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
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obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o
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obj-$(CONFIG_ARCH_R8A7791) += clock-r8a7791.o
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obj-$(CONFIG_ARCH_EMEV2) += clock-emev2.o
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endif
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@ -69,6 +69,15 @@ static struct clk extal_clk = {
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.mapping = &cpg_mapping,
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};
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static struct clk audio_clk_a = {
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};
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static struct clk audio_clk_b = {
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};
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static struct clk audio_clk_c = {
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};
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/*
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* clock ratio of these clock will be updated
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* on r8a7778_clock_init()
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@ -100,18 +109,23 @@ static struct clk *main_clks[] = {
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&p_clk,
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&g_clk,
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&z_clk,
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&audio_clk_a,
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&audio_clk_b,
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&audio_clk_c,
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};
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enum {
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MSTP331,
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MSTP323, MSTP322, MSTP321,
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MSTP311, MSTP310,
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MSTP309, MSTP308, MSTP307,
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MSTP114,
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MSTP110, MSTP109,
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MSTP100,
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MSTP030,
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MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
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MSTP016, MSTP015,
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MSTP007,
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MSTP016, MSTP015, MSTP012, MSTP011, MSTP010,
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MSTP009, MSTP008, MSTP007,
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MSTP_NR };
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static struct clk mstp_clks[MSTP_NR] = {
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@ -119,6 +133,11 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
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[MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
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[MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
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[MSTP311] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 11, 0), /* SSI4 */
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[MSTP310] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 10, 0), /* SSI5 */
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[MSTP309] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 9, 0), /* SSI6 */
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[MSTP308] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 8, 0), /* SSI7 */
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[MSTP307] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 7, 0), /* SSI8 */
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[MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
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[MSTP110] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 10, 0), /* VIN0 */
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[MSTP109] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 9, 0), /* VIN1 */
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@ -135,11 +154,20 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */
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[MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */
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[MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */
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[MSTP012] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 12, 0), /* SSI0 */
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[MSTP011] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 11, 0), /* SSI1 */
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[MSTP010] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 10, 0), /* SSI2 */
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[MSTP009] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 9, 0), /* SSI3 */
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[MSTP008] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 8, 0), /* SRU */
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[MSTP007] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 7, 0), /* HSPI */
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};
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static struct clk_lookup lookups[] = {
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/* main */
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CLKDEV_CON_ID("audio_clk_a", &audio_clk_a),
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CLKDEV_CON_ID("audio_clk_b", &audio_clk_b),
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CLKDEV_CON_ID("audio_clk_c", &audio_clk_c),
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CLKDEV_CON_ID("audio_clk_internal", &s1_clk),
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CLKDEV_CON_ID("shyway_clk", &s_clk),
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CLKDEV_CON_ID("peripheral_clk", &p_clk),
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@ -153,6 +181,7 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */
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CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
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CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
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CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */
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CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
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CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
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CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
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@ -168,6 +197,17 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
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CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
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CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
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CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */
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CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]),
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CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP011]),
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CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP010]),
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CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP009]),
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CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP311]),
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CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP310]),
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CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]),
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CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]),
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CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]),
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};
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void __init r8a7778_clock_init(void)
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@ -200,7 +200,7 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
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CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
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CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
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CLKDEV_DEV_ID("rcar-du.0", &mstp_clks[MSTP103]), /* DU */
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CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */
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};
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void __init r8a7779_clock_init(void)
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@ -182,7 +182,7 @@ static struct clk div6_clks[DIV6_NR] = {
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/* MSTP */
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enum {
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MSTP813,
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MSTP721, MSTP720,
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MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
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MSTP717, MSTP716,
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MSTP522,
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MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
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@ -193,6 +193,11 @@ enum {
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
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[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
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[MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
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[MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
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[MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */
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[MSTP722] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 22, 0), /* DU2 */
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[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
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[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
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[MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
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@ -251,6 +256,11 @@ static struct clk_lookup lookups[] = {
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CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
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/* MSTP */
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CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
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CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
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CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
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CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
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CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
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CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
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CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
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CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
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@ -0,0 +1,237 @@
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/*
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* r8a7791 clock framework support
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/sh_clk.h>
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#include <linux/clkdev.h>
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#include <mach/clock.h>
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#include <mach/common.h>
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/*
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* MD EXTAL PLL0 PLL1 PLL3
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* 14 13 19 (MHz) *1 *1
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*---------------------------------------------------
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* 0 0 0 15 x 1 x172/2 x208/2 x106
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* 0 0 1 15 x 1 x172/2 x208/2 x88
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* 0 1 0 20 x 1 x130/2 x156/2 x80
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* 0 1 1 20 x 1 x130/2 x156/2 x66
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* 1 0 0 26 / 2 x200/2 x240/2 x122
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* 1 0 1 26 / 2 x200/2 x240/2 x102
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* 1 1 0 30 / 2 x172/2 x208/2 x106
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* 1 1 1 30 / 2 x172/2 x208/2 x88
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*
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* *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
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* see "p1 / 2" on R8A7791_CLOCK_ROOT() below
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*/
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#define MD(nr) (1 << nr)
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#define CPG_BASE 0xe6150000
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#define CPG_LEN 0x1000
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#define SMSTPCR0 0xE6150130
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#define SMSTPCR1 0xE6150134
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#define SMSTPCR2 0xe6150138
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#define SMSTPCR3 0xE615013C
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#define SMSTPCR5 0xE6150144
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#define SMSTPCR7 0xe615014c
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#define SMSTPCR8 0xE6150990
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#define SMSTPCR9 0xE6150994
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#define SMSTPCR10 0xE6150998
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#define SMSTPCR11 0xE615099C
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#define MODEMR 0xE6160060
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#define SDCKCR 0xE6150074
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#define SD2CKCR 0xE6150078
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#define SD3CKCR 0xE615007C
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#define MMC0CKCR 0xE6150240
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#define MMC1CKCR 0xE6150244
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#define SSPCKCR 0xE6150248
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#define SSPRSCKCR 0xE615024C
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static struct clk_mapping cpg_mapping = {
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.phys = CPG_BASE,
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.len = CPG_LEN,
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};
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static struct clk extal_clk = {
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/* .rate will be updated on r8a7791_clock_init() */
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.mapping = &cpg_mapping,
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};
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static struct sh_clk_ops followparent_clk_ops = {
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.recalc = followparent_recalc,
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};
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static struct clk main_clk = {
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/* .parent will be set r8a73a4_clock_init */
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.ops = &followparent_clk_ops,
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};
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/*
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* clock ratio of these clock will be updated
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* on r8a7791_clock_init()
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*/
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SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
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/* fixed ratio clock */
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||||
SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
|
||||
SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2);
|
||||
|
||||
SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
|
||||
SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
|
||||
SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
|
||||
SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
|
||||
SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
|
||||
|
||||
static struct clk *main_clks[] = {
|
||||
&extal_clk,
|
||||
&extal_div2_clk,
|
||||
&main_clk,
|
||||
&pll1_clk,
|
||||
&pll1_div2_clk,
|
||||
&pll3_clk,
|
||||
&hp_clk,
|
||||
&p_clk,
|
||||
&rclk_clk,
|
||||
&mp_clk,
|
||||
&cp_clk,
|
||||
};
|
||||
|
||||
/* MSTP */
|
||||
enum {
|
||||
MSTP721, MSTP720,
|
||||
MSTP719, MSTP718, MSTP715, MSTP714,
|
||||
MSTP216, MSTP207, MSTP206,
|
||||
MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107,
|
||||
MSTP124,
|
||||
MSTP_NR
|
||||
};
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
|
||||
[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
|
||||
[MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */
|
||||
[MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */
|
||||
[MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */
|
||||
[MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */
|
||||
[MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
|
||||
[MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
|
||||
[MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
|
||||
[MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
|
||||
[MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
|
||||
[MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
|
||||
[MSTP1105] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 5, 0), /* SCIFA3 */
|
||||
[MSTP1106] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 6, 0), /* SCIFA4 */
|
||||
[MSTP1107] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 7, 0), /* SCIFA5 */
|
||||
[MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("extal", &extal_clk),
|
||||
CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
|
||||
CLKDEV_CON_ID("main", &main_clk),
|
||||
CLKDEV_CON_ID("pll1", &pll1_clk),
|
||||
CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
|
||||
CLKDEV_CON_ID("pll3", &pll3_clk),
|
||||
CLKDEV_CON_ID("hp", &hp_clk),
|
||||
CLKDEV_CON_ID("p", &p_clk),
|
||||
CLKDEV_CON_ID("rclk", &rclk_clk),
|
||||
CLKDEV_CON_ID("mp", &mp_clk),
|
||||
CLKDEV_CON_ID("cp", &cp_clk),
|
||||
CLKDEV_CON_ID("peripheral_clk", &hp_clk),
|
||||
|
||||
/* MSTP */
|
||||
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
|
||||
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
|
||||
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */
|
||||
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]), /* SCIFB1 */
|
||||
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), /* SCIFB2 */
|
||||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]), /* SCIFA2 */
|
||||
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]), /* SCIF0 */
|
||||
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), /* SCIF1 */
|
||||
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP719]), /* SCIF2 */
|
||||
CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP718]), /* SCIF3 */
|
||||
CLKDEV_DEV_ID("sh-sci.10", &mstp_clks[MSTP715]), /* SCIF4 */
|
||||
CLKDEV_DEV_ID("sh-sci.11", &mstp_clks[MSTP714]), /* SCIF5 */
|
||||
CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1105]), /* SCIFA3 */
|
||||
CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
|
||||
CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
|
||||
CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
|
||||
};
|
||||
|
||||
#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
|
||||
extal_clk.rate = e * 1000 * 1000; \
|
||||
main_clk.parent = m; \
|
||||
SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
|
||||
if (mode & MD(19)) \
|
||||
SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
|
||||
else \
|
||||
SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
|
||||
|
||||
|
||||
void __init r8a7791_clock_init(void)
|
||||
{
|
||||
void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
|
||||
u32 mode;
|
||||
int k, ret = 0;
|
||||
|
||||
BUG_ON(!modemr);
|
||||
mode = ioread32(modemr);
|
||||
iounmap(modemr);
|
||||
|
||||
switch (mode & (MD(14) | MD(13))) {
|
||||
case 0:
|
||||
R8A7791_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
|
||||
break;
|
||||
case MD(13):
|
||||
R8A7791_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
|
||||
break;
|
||||
case MD(14):
|
||||
R8A7791_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
|
||||
break;
|
||||
case MD(13) | MD(14):
|
||||
R8A7791_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
|
||||
break;
|
||||
}
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
if (!ret)
|
||||
shmobile_clk_init();
|
||||
else
|
||||
goto epanic;
|
||||
|
||||
return;
|
||||
|
||||
epanic:
|
||||
panic("failed to setup r8a7791 clocks\n");
|
||||
}
|
||||
|
|
@ -35,4 +35,6 @@ extern void r8a7778_clock_init(void);
|
|||
extern void r8a7778_init_irq_extpin(int irlm);
|
||||
extern void r8a7778_pinmux_init(void);
|
||||
|
||||
extern int r8a7778_usb_phy_power(bool enable);
|
||||
|
||||
#endif /* __ASM_R8A7778_H__ */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,8 @@
|
|||
#ifndef __ASM_R8A7791_H__
|
||||
#define __ASM_R8A7791_H__
|
||||
|
||||
void r8a7791_add_dt_devices(void);
|
||||
void r8a7791_clock_init(void);
|
||||
void r8a7791_init_early(void);
|
||||
|
||||
#endif /* __ASM_R8A7791_H__ */
|
||||
|
|
@ -95,29 +95,46 @@ static struct sh_timer_config sh_tmu1_platform_data __initdata = {
|
|||
&sh_tmu##idx##_platform_data, \
|
||||
sizeof(sh_tmu##idx##_platform_data))
|
||||
|
||||
/* USB */
|
||||
static struct usb_phy *phy;
|
||||
int r8a7778_usb_phy_power(bool enable)
|
||||
{
|
||||
static struct usb_phy *phy = NULL;
|
||||
int ret = 0;
|
||||
|
||||
if (!phy)
|
||||
phy = usb_get_phy(USB_PHY_TYPE_USB2);
|
||||
|
||||
if (IS_ERR(phy)) {
|
||||
pr_err("kernel doesn't have usb phy driver\n");
|
||||
return PTR_ERR(phy);
|
||||
}
|
||||
|
||||
if (enable)
|
||||
ret = usb_phy_init(phy);
|
||||
else
|
||||
usb_phy_shutdown(phy);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* USB */
|
||||
static int usb_power_on(struct platform_device *pdev)
|
||||
{
|
||||
if (IS_ERR(phy))
|
||||
return PTR_ERR(phy);
|
||||
int ret = r8a7778_usb_phy_power(true);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
pm_runtime_get_sync(&pdev->dev);
|
||||
|
||||
usb_phy_init(phy);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void usb_power_off(struct platform_device *pdev)
|
||||
{
|
||||
if (IS_ERR(phy))
|
||||
if (r8a7778_usb_phy_power(false))
|
||||
return;
|
||||
|
||||
usb_phy_shutdown(phy);
|
||||
|
||||
pm_runtime_put_sync(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
}
|
||||
|
|
@ -353,8 +370,6 @@ void __init r8a7778_add_standard_devices(void)
|
|||
|
||||
void __init r8a7778_init_late(void)
|
||||
{
|
||||
phy = usb_get_phy(USB_PHY_TYPE_USB2);
|
||||
|
||||
platform_device_register_full(&ehci_info);
|
||||
platform_device_register_full(&ohci_info);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,149 @@
|
|||
/*
|
||||
* r8a7791 processor support
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Electronics Corporation
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
* Copyright (C) 2013 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/r8a7791.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#define SCIF_COMMON(scif_type, baseaddr, irq) \
|
||||
.type = scif_type, \
|
||||
.mapbase = baseaddr, \
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
|
||||
.irqs = SCIx_IRQ_MUXED(irq)
|
||||
|
||||
#define SCIFA_DATA(index, baseaddr, irq) \
|
||||
[index] = { \
|
||||
SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
|
||||
.scbrr_algo_id = SCBRR_ALGO_4, \
|
||||
.scscr = SCSCR_RE | SCSCR_TE, \
|
||||
}
|
||||
|
||||
#define SCIFB_DATA(index, baseaddr, irq) \
|
||||
[index] = { \
|
||||
SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
|
||||
.scbrr_algo_id = SCBRR_ALGO_4, \
|
||||
.scscr = SCSCR_RE | SCSCR_TE, \
|
||||
}
|
||||
|
||||
#define SCIF_DATA(index, baseaddr, irq) \
|
||||
[index] = { \
|
||||
SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
|
||||
.scbrr_algo_id = SCBRR_ALGO_2, \
|
||||
.scscr = SCSCR_RE | SCSCR_TE, \
|
||||
}
|
||||
|
||||
#define HSCIF_DATA(index, baseaddr, irq) \
|
||||
[index] = { \
|
||||
SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
|
||||
.scbrr_algo_id = SCBRR_ALGO_6, \
|
||||
.scscr = SCSCR_RE | SCSCR_TE, \
|
||||
}
|
||||
|
||||
enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
|
||||
SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 };
|
||||
|
||||
static const struct plat_sci_port scif[] __initconst = {
|
||||
SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
|
||||
SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
|
||||
SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
|
||||
SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
|
||||
SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
|
||||
SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
|
||||
SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
|
||||
SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
|
||||
SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */
|
||||
SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */
|
||||
SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */
|
||||
SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */
|
||||
SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */
|
||||
SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */
|
||||
SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */
|
||||
};
|
||||
|
||||
static inline void r8a7791_register_scif(int idx)
|
||||
{
|
||||
platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
|
||||
sizeof(struct plat_sci_port));
|
||||
}
|
||||
|
||||
static const struct sh_timer_config cmt00_platform_data __initconst = {
|
||||
.name = "CMT00",
|
||||
.timer_bit = 0,
|
||||
.clockevent_rating = 80,
|
||||
};
|
||||
|
||||
static const struct resource cmt00_resources[] __initconst = {
|
||||
DEFINE_RES_MEM(0xffca0510, 0x0c),
|
||||
DEFINE_RES_MEM(0xffca0500, 0x04),
|
||||
DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
|
||||
};
|
||||
|
||||
#define r8a7791_register_cmt(idx) \
|
||||
platform_device_register_resndata(&platform_bus, "sh_cmt", \
|
||||
idx, cmt##idx##_resources, \
|
||||
ARRAY_SIZE(cmt##idx##_resources), \
|
||||
&cmt##idx##_platform_data, \
|
||||
sizeof(struct sh_timer_config))
|
||||
|
||||
void __init r8a7791_add_dt_devices(void)
|
||||
{
|
||||
r8a7791_register_scif(SCIFA0);
|
||||
r8a7791_register_scif(SCIFA1);
|
||||
r8a7791_register_scif(SCIFB0);
|
||||
r8a7791_register_scif(SCIFB1);
|
||||
r8a7791_register_scif(SCIFB2);
|
||||
r8a7791_register_scif(SCIFA2);
|
||||
r8a7791_register_scif(SCIF0);
|
||||
r8a7791_register_scif(SCIF1);
|
||||
r8a7791_register_scif(SCIF2);
|
||||
r8a7791_register_scif(SCIF3);
|
||||
r8a7791_register_scif(SCIF4);
|
||||
r8a7791_register_scif(SCIF5);
|
||||
r8a7791_register_scif(SCIFA3);
|
||||
r8a7791_register_scif(SCIFA4);
|
||||
r8a7791_register_scif(SCIFA5);
|
||||
r8a7791_register_cmt(00);
|
||||
}
|
||||
|
||||
void __init r8a7791_init_early(void)
|
||||
{
|
||||
#ifndef CONFIG_ARM_ARCH_TIMER
|
||||
shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USE_OF
|
||||
static const char *r8a7791_boards_compat_dt[] __initdata = {
|
||||
"renesas,r8a7791",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
|
||||
.init_early = r8a7791_init_early,
|
||||
.dt_compat = r8a7791_boards_compat_dt,
|
||||
MACHINE_END
|
||||
#endif /* CONFIG_USE_OF */
|
||||
Loading…
Reference in New Issue