Blackfin: BF51x: fix handling of PH8 (the "internal" SPI0SEL4 pin)
Even though the PH8 pin is only internal to the processor packaging, it can be controlled like any other GPIO pin. Now that we have a proper GPIO define, we can fix the SPI0 CS4 define for the internal SPI flash. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
parent
306208f40c
commit
502c8a0e07
|
@ -7,7 +7,7 @@
|
||||||
#ifndef _MACH_GPIO_H_
|
#ifndef _MACH_GPIO_H_
|
||||||
#define _MACH_GPIO_H_
|
#define _MACH_GPIO_H_
|
||||||
|
|
||||||
#define MAX_BLACKFIN_GPIOS 40
|
#define MAX_BLACKFIN_GPIOS 41
|
||||||
|
|
||||||
#define GPIO_PF0 0
|
#define GPIO_PF0 0
|
||||||
#define GPIO_PF1 1
|
#define GPIO_PF1 1
|
||||||
|
@ -49,6 +49,7 @@
|
||||||
#define GPIO_PH5 37
|
#define GPIO_PH5 37
|
||||||
#define GPIO_PH6 38
|
#define GPIO_PH6 38
|
||||||
#define GPIO_PH7 39
|
#define GPIO_PH7 39
|
||||||
|
#define GPIO_PH8 40
|
||||||
|
|
||||||
#define PORT_F GPIO_PF0
|
#define PORT_F GPIO_PF0
|
||||||
#define PORT_G GPIO_PG0
|
#define PORT_G GPIO_PG0
|
||||||
|
|
|
@ -95,7 +95,7 @@
|
||||||
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
|
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
|
||||||
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
|
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
|
||||||
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
|
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
|
||||||
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
|
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
|
||||||
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
|
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
|
||||||
|
|
||||||
#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
|
#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
|
||||||
|
|
Loading…
Reference in a new issue