drm/i915: Drop ORIGIN_GTT for untracked GTT writes
If FBC is set on a framebuffer that is unmapped, all GTT faults will be from a partial mapping. Writes by the user through the partial VMA are then untracked by the FBC and so we must use the ORIGIN_CPU when flushing the I915_GEM_DOMAIN_GTT. v2: Keep ORIGIN_CPU for set-to-domain(.write=CPU) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: "Zanoni, Paulo R" <paulo.r.zanoni@intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20160818161718.27187-25-chris@chris-wilson.co.uk
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@ -2198,6 +2198,7 @@ struct drm_i915_gem_object {
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unsigned int cache_dirty:1;
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unsigned int cache_dirty:1;
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atomic_t frontbuffer_bits;
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atomic_t frontbuffer_bits;
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unsigned int frontbuffer_ggtt_origin; /* write once */
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/** Current tiling stride for the object, if it's tiled. */
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/** Current tiling stride for the object, if it's tiled. */
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unsigned int tiling_and_stride;
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unsigned int tiling_and_stride;
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@ -2205,7 +2206,6 @@ struct drm_i915_gem_object {
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#define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
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#define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
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#define STRIDE_MASK (~TILING_MASK)
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#define STRIDE_MASK (~TILING_MASK)
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unsigned int has_wc_mmap;
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/** Count of VMA actually bound by this object */
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/** Count of VMA actually bound by this object */
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unsigned int bind_count;
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unsigned int bind_count;
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unsigned int pin_display;
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unsigned int pin_display;
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@ -1497,8 +1497,8 @@ err:
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static inline enum fb_op_origin
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static inline enum fb_op_origin
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write_origin(struct drm_i915_gem_object *obj, unsigned domain)
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write_origin(struct drm_i915_gem_object *obj, unsigned domain)
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{
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{
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return domain == I915_GEM_DOMAIN_GTT && !obj->has_wc_mmap ?
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return (domain == I915_GEM_DOMAIN_GTT ?
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ORIGIN_GTT : ORIGIN_CPU;
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obj->frontbuffer_ggtt_origin : ORIGIN_CPU);
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}
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}
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/**
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/**
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@ -1658,7 +1658,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
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up_write(&mm->mmap_sem);
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up_write(&mm->mmap_sem);
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/* This may race, but that's ok, it only gets set */
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/* This may race, but that's ok, it only gets set */
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WRITE_ONCE(obj->has_wc_mmap, true);
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WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU);
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}
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}
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i915_gem_object_put_unlocked(obj);
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i915_gem_object_put_unlocked(obj);
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if (IS_ERR((void *)addr))
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if (IS_ERR((void *)addr))
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@ -1761,6 +1761,11 @@ int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf)
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if (chunk_size >= obj->base.size >> PAGE_SHIFT)
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if (chunk_size >= obj->base.size >> PAGE_SHIFT)
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view.type = I915_GGTT_VIEW_NORMAL;
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view.type = I915_GGTT_VIEW_NORMAL;
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/* Userspace is now writing through an untracked VMA, abandon
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* all hope that the hardware is able to track future writes.
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*/
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obj->frontbuffer_ggtt_origin = ORIGIN_CPU;
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vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
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vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE);
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}
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}
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if (IS_ERR(vma)) {
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if (IS_ERR(vma)) {
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@ -4093,6 +4098,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
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obj->ops = ops;
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obj->ops = ops;
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obj->frontbuffer_ggtt_origin = ORIGIN_GTT;
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obj->madv = I915_MADV_WILLNEED;
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obj->madv = I915_MADV_WILLNEED;
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i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
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i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size);
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