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dmaengine: sun6i: Correct setting of clock autogating register for A83T/H3 

The H83T uses a compatible string different from the A23, but requires
the same clock autogating register setting.

The H3 also requires setting the clock autogating register, but has
the register at a different offset.

Add three suitable callbacks for the existing controller generations
and set it in the controller config structure.

Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
hifive-unleashed-5.1
Stefan Brüns 2017-09-28 03:49:18 +02:00 committed by Vinod Koul
parent 8f3b00347b
commit 50b1249754
1 changed files with 23 additions and 5 deletions
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28
drivers/dma/sun6i-dma.c
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@ -48,6 +48,9 @@
#define SUN8I_DMA_GATE 0x20
#define SUN8I_DMA_GATE_ENABLE 0x4
#define SUNXI_H3_SECURE_REG 0x20
#define SUNXI_H3_DMA_GATE 0x28
#define SUNXI_H3_DMA_GATE_ENABLE 0x4
/*
* Channels specific registers
*/
@ -90,6 +93,9 @@
#define NORMAL_WAIT 8
#define DRQ_SDRAM 1
/* forward declaration */
struct sun6i_dma_dev;
/*
* Hardware channels / ports representation
*
@ -111,7 +117,7 @@ struct sun6i_dma_config {
* however these SoCs really have and need this bit, as seen in the
* BSP kernel source code.
*/
bool gate_needed;
void (*clock_autogate_enable)(struct sun6i_dma_dev *);
};
/*
@ -267,6 +273,16 @@ static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
return addr_width >> 1;
}
static void sun6i_enable_clock_autogate_a23(struct sun6i_dma_dev *sdev)
{
writel(SUN8I_DMA_GATE_ENABLE, sdev->base + SUN8I_DMA_GATE);
}
static void sun6i_enable_clock_autogate_h3(struct sun6i_dma_dev *sdev)
{
writel(SUNXI_H3_DMA_GATE_ENABLE, sdev->base + SUNXI_H3_DMA_GATE);
}
static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan)
{
struct sun6i_desc *txd = pchan->desc;
@ -1020,13 +1036,14 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = {
.nr_max_channels = 8,
.nr_max_requests = 24,
.nr_max_vchans = 37,
.gate_needed = true,
.clock_autogate_enable = sun6i_enable_clock_autogate_a23,
};
static struct sun6i_dma_config sun8i_a83t_dma_cfg = {
.nr_max_channels = 8,
.nr_max_requests = 28,
.nr_max_vchans = 39,
.clock_autogate_enable = sun6i_enable_clock_autogate_a23,
};
/*
@ -1038,6 +1055,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = {
.nr_max_channels = 12,
.nr_max_requests = 27,
.nr_max_vchans = 34,
.clock_autogate_enable = sun6i_enable_clock_autogate_h3,
};
/*
@ -1049,7 +1067,7 @@ static struct sun6i_dma_config sun8i_v3s_dma_cfg = {
.nr_max_channels = 8,
.nr_max_requests = 23,
.nr_max_vchans = 24,
.gate_needed = true,
.clock_autogate_enable = sun6i_enable_clock_autogate_a23,
};
static const struct of_device_id sun6i_dma_match[] = {
@ -1197,8 +1215,8 @@ static int sun6i_dma_probe(struct platform_device *pdev)
goto err_dma_unregister;
}
if (sdc->cfg->gate_needed)
writel(SUN8I_DMA_GATE_ENABLE, sdc->base + SUN8I_DMA_GATE);
if (sdc->cfg->clock_autogate_enable)
sdc->cfg->clock_autogate_enable(sdc);
return 0;