spi: spi-fsl-dspi: Fix code alignment
This is a cosmetic patch that changes nothing except makes sure the code is aligned to the same column, which makes it easier to the eye. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Link: https://lore.kernel.org/r/20190818180115.31114-2-olteanv@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>alistair/sunxi64-5.4-dsi
Vladimir Oltean
Mark Brown
parent
43004f31eb
commit
50fcd84764
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@ -28,7 +28,7 @@
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#include <linux/spi/spi_bitbang.h>
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#include <linux/time.h>
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#define DRIVER_NAME "fsl-dspi"
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#define DRIVER_NAME "fsl-dspi"
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#ifdef CONFIG_M5441x
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#define DSPI_FIFO_SIZE 16
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@ -37,101 +37,101 @@
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#endif
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#define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024)
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#define SPI_MCR 0x00
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#define SPI_MCR_MASTER (1 << 31)
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#define SPI_MCR_PCSIS (0x3F << 16)
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#define SPI_MCR_CLR_TXF (1 << 11)
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#define SPI_MCR_CLR_RXF (1 << 10)
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#define SPI_MCR_XSPI (1 << 3)
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#define SPI_MCR 0x00
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#define SPI_MCR_MASTER (1 << 31)
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#define SPI_MCR_PCSIS (0x3F << 16)
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#define SPI_MCR_CLR_TXF (1 << 11)
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#define SPI_MCR_CLR_RXF (1 << 10)
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#define SPI_MCR_XSPI (1 << 3)
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#define SPI_TCR 0x08
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#define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16)
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#define SPI_TCR 0x08
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#define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16)
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#define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4))
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#define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
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#define SPI_CTAR_CPOL(x) ((x) << 26)
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#define SPI_CTAR_CPHA(x) ((x) << 25)
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#define SPI_CTAR_LSBFE(x) ((x) << 24)
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#define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22)
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#define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
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#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
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#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
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#define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12)
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#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
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#define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
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#define SPI_CTAR_BR(x) ((x) & 0x0000000f)
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#define SPI_CTAR_SCALE_BITS 0xf
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#define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4))
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#define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
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#define SPI_CTAR_CPOL(x) ((x) << 26)
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#define SPI_CTAR_CPHA(x) ((x) << 25)
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#define SPI_CTAR_LSBFE(x) ((x) << 24)
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#define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22)
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#define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
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#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
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#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
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#define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12)
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#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
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#define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
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#define SPI_CTAR_BR(x) ((x) & 0x0000000f)
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#define SPI_CTAR_SCALE_BITS 0xf
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#define SPI_CTAR0_SLAVE 0x0c
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#define SPI_CTAR0_SLAVE 0x0c
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#define SPI_SR 0x2c
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#define SPI_SR_EOQF 0x10000000
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#define SPI_SR_TCFQF 0x80000000
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#define SPI_SR_CLEAR 0x9aaf0000
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#define SPI_SR 0x2c
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#define SPI_SR_EOQF 0x10000000
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#define SPI_SR_TCFQF 0x80000000
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#define SPI_SR_CLEAR 0x9aaf0000
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#define SPI_RSER_TFFFE BIT(25)
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#define SPI_RSER_TFFFD BIT(24)
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#define SPI_RSER_RFDFE BIT(17)
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#define SPI_RSER_RFDFD BIT(16)
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#define SPI_RSER_TFFFE BIT(25)
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#define SPI_RSER_TFFFD BIT(24)
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#define SPI_RSER_RFDFE BIT(17)
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#define SPI_RSER_RFDFD BIT(16)
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#define SPI_RSER 0x30
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#define SPI_RSER_EOQFE 0x10000000
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#define SPI_RSER_TCFQE 0x80000000
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#define SPI_RSER 0x30
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#define SPI_RSER_EOQFE 0x10000000
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#define SPI_RSER_TCFQE 0x80000000
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#define SPI_PUSHR 0x34
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#define SPI_PUSHR_CMD_CONT (1 << 15)
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#define SPI_PUSHR_CONT (SPI_PUSHR_CMD_CONT << 16)
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#define SPI_PUSHR_CMD_CTAS(x) (((x) & 0x0003) << 12)
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#define SPI_PUSHR_CTAS(x) (SPI_PUSHR_CMD_CTAS(x) << 16)
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#define SPI_PUSHR_CMD_EOQ (1 << 11)
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#define SPI_PUSHR_EOQ (SPI_PUSHR_CMD_EOQ << 16)
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#define SPI_PUSHR_CMD_CTCNT (1 << 10)
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#define SPI_PUSHR_CTCNT (SPI_PUSHR_CMD_CTCNT << 16)
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#define SPI_PUSHR_CMD_PCS(x) ((1 << x) & 0x003f)
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#define SPI_PUSHR_PCS(x) (SPI_PUSHR_CMD_PCS(x) << 16)
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#define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff)
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#define SPI_PUSHR 0x34
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#define SPI_PUSHR_CMD_CONT (1 << 15)
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#define SPI_PUSHR_CONT (SPI_PUSHR_CMD_CONT << 16)
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#define SPI_PUSHR_CMD_CTAS(x) (((x) & 0x0003) << 12)
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#define SPI_PUSHR_CTAS(x) (SPI_PUSHR_CMD_CTAS(x) << 16)
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#define SPI_PUSHR_CMD_EOQ (1 << 11)
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#define SPI_PUSHR_EOQ (SPI_PUSHR_CMD_EOQ << 16)
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#define SPI_PUSHR_CMD_CTCNT (1 << 10)
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#define SPI_PUSHR_CTCNT (SPI_PUSHR_CMD_CTCNT << 16)
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#define SPI_PUSHR_CMD_PCS(x) ((1 << x) & 0x003f)
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#define SPI_PUSHR_PCS(x) (SPI_PUSHR_CMD_PCS(x) << 16)
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#define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff)
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#define SPI_PUSHR_SLAVE 0x34
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#define SPI_PUSHR_SLAVE 0x34
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#define SPI_POPR 0x38
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#define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff)
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#define SPI_POPR 0x38
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#define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff)
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#define SPI_TXFR0 0x3c
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#define SPI_TXFR1 0x40
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#define SPI_TXFR2 0x44
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#define SPI_TXFR3 0x48
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#define SPI_RXFR0 0x7c
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#define SPI_RXFR1 0x80
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#define SPI_RXFR2 0x84
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#define SPI_RXFR3 0x88
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#define SPI_TXFR0 0x3c
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#define SPI_TXFR1 0x40
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#define SPI_TXFR2 0x44
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#define SPI_TXFR3 0x48
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#define SPI_RXFR0 0x7c
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#define SPI_RXFR1 0x80
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#define SPI_RXFR2 0x84
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#define SPI_RXFR3 0x88
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#define SPI_CTARE(x) (0x11c + (((x) & 0x3) * 4))
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#define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16)
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#define SPI_CTARE_DTCP(x) ((x) & 0x7ff)
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#define SPI_CTARE(x) (0x11c + (((x) & 0x3) * 4))
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#define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16)
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#define SPI_CTARE_DTCP(x) ((x) & 0x7ff)
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#define SPI_SREX 0x13c
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#define SPI_SREX 0x13c
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#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
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#define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf)
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#define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
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#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
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#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
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#define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf)
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#define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
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#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
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#define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
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#define SPI_FRAME_EBITS_MASK SPI_CTARE_FMSZE(1)
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#define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
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#define SPI_FRAME_EBITS_MASK SPI_CTARE_FMSZE(1)
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/* Register offsets for regmap_pushr */
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#define PUSHR_CMD 0x0
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#define PUSHR_TX 0x2
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#define PUSHR_CMD 0x0
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#define PUSHR_TX 0x2
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#define SPI_CS_INIT 0x01
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#define SPI_CS_ASSERT 0x02
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#define SPI_CS_DROP 0x04
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#define SPI_CS_INIT 0x01
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#define SPI_CS_ASSERT 0x02
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#define SPI_CS_DROP 0x04
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#define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
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#define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
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struct chip_data {
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u32 ctar_val;
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u16 void_write_data;
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u32 ctar_val;
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u16 void_write_data;
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};
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enum dspi_trans_mode {
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@ -141,75 +141,75 @@ enum dspi_trans_mode {
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};
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struct fsl_dspi_devtype_data {
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enum dspi_trans_mode trans_mode;
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u8 max_clock_factor;
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bool xspi_mode;
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enum dspi_trans_mode trans_mode;
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u8 max_clock_factor;
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bool xspi_mode;
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};
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static const struct fsl_dspi_devtype_data vf610_data = {
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.trans_mode = DSPI_DMA_MODE,
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.max_clock_factor = 2,
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.trans_mode = DSPI_DMA_MODE,
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.max_clock_factor = 2,
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};
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static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
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.trans_mode = DSPI_TCFQ_MODE,
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.max_clock_factor = 8,
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.xspi_mode = true,
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.trans_mode = DSPI_TCFQ_MODE,
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.max_clock_factor = 8,
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.xspi_mode = true,
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};
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static const struct fsl_dspi_devtype_data ls2085a_data = {
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.trans_mode = DSPI_TCFQ_MODE,
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.max_clock_factor = 8,
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.trans_mode = DSPI_TCFQ_MODE,
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.max_clock_factor = 8,
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};
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static const struct fsl_dspi_devtype_data coldfire_data = {
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.trans_mode = DSPI_EOQ_MODE,
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.max_clock_factor = 8,
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.trans_mode = DSPI_EOQ_MODE,
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.max_clock_factor = 8,
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};
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struct fsl_dspi_dma {
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/* Length of transfer in words of DSPI_FIFO_SIZE */
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u32 curr_xfer_len;
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u32 curr_xfer_len;
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u32 *tx_dma_buf;
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struct dma_chan *chan_tx;
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dma_addr_t tx_dma_phys;
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struct completion cmd_tx_complete;
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struct dma_async_tx_descriptor *tx_desc;
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u32 *tx_dma_buf;
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struct dma_chan *chan_tx;
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dma_addr_t tx_dma_phys;
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struct completion cmd_tx_complete;
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struct dma_async_tx_descriptor *tx_desc;
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u32 *rx_dma_buf;
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struct dma_chan *chan_rx;
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dma_addr_t rx_dma_phys;
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struct completion cmd_rx_complete;
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struct dma_async_tx_descriptor *rx_desc;
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u32 *rx_dma_buf;
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struct dma_chan *chan_rx;
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dma_addr_t rx_dma_phys;
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struct completion cmd_rx_complete;
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struct dma_async_tx_descriptor *rx_desc;
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};
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struct fsl_dspi {
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struct spi_master *master;
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struct platform_device *pdev;
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struct spi_master *master;
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struct platform_device *pdev;
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struct regmap *regmap;
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struct regmap *regmap_pushr;
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int irq;
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struct clk *clk;
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struct regmap *regmap;
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struct regmap *regmap_pushr;
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int irq;
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struct clk *clk;
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struct spi_transfer *cur_transfer;
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struct spi_message *cur_msg;
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struct chip_data *cur_chip;
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size_t len;
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const void *tx;
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void *rx;
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void *rx_end;
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u16 void_write_data;
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u16 tx_cmd;
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u8 bits_per_word;
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u8 bytes_per_word;
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const struct fsl_dspi_devtype_data *devtype_data;
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struct spi_transfer *cur_transfer;
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struct spi_message *cur_msg;
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struct chip_data *cur_chip;
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size_t len;
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const void *tx;
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void *rx;
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void *rx_end;
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u16 void_write_data;
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u16 tx_cmd;
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u8 bits_per_word;
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u8 bytes_per_word;
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const struct fsl_dspi_devtype_data *devtype_data;
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wait_queue_head_t waitq;
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u32 waitflags;
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wait_queue_head_t waitq;
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u32 waitflags;
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struct fsl_dspi_dma *dma;
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struct fsl_dspi_dma *dma;
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};
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static u32 dspi_pop_tx(struct fsl_dspi *dspi)
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@ -338,7 +338,7 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
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}
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time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
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DMA_COMPLETION_TIMEOUT);
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DMA_COMPLETION_TIMEOUT);
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if (time_left == 0) {
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dev_err(dev, "DMA tx timeout\n");
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dmaengine_terminate_all(dma->chan_tx);
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@ -347,7 +347,7 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
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}
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time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
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DMA_COMPLETION_TIMEOUT);
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DMA_COMPLETION_TIMEOUT);
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if (time_left == 0) {
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dev_err(dev, "DMA rx timeout\n");
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dmaengine_terminate_all(dma->chan_tx);
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@ -421,14 +421,14 @@ static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
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}
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dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
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&dma->tx_dma_phys, GFP_KERNEL);
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&dma->tx_dma_phys, GFP_KERNEL);
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if (!dma->tx_dma_buf) {
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ret = -ENOMEM;
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goto err_tx_dma_buf;
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}
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dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
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&dma->rx_dma_phys, GFP_KERNEL);
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&dma->rx_dma_phys, GFP_KERNEL);
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if (!dma->rx_dma_buf) {
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ret = -ENOMEM;
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goto err_rx_dma_buf;
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@ -501,14 +501,14 @@ static void dspi_release_dma(struct fsl_dspi *dspi)
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}
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static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
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unsigned long clkrate)
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unsigned long clkrate)
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{
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/* Valid baud rate pre-scaler values */
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int pbr_tbl[4] = {2, 3, 5, 7};
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int brs[16] = { 2, 4, 6, 8,
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16, 32, 64, 128,
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256, 512, 1024, 2048,
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4096, 8192, 16384, 32768 };
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16, 32, 64, 128,
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256, 512, 1024, 2048,
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4096, 8192, 16384, 32768 };
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int scale_needed, scale, minscale = INT_MAX;
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int i, j;
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@ -538,7 +538,7 @@ static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
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}
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static void ns_delay_scale(char *psc, char *sc, int delay_ns,
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unsigned long clkrate)
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unsigned long clkrate)
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{
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int pscale_tbl[4] = {1, 3, 5, 7};
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int scale_needed, scale, minscale = INT_MAX;
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@ -546,7 +546,7 @@ static void ns_delay_scale(char *psc, char *sc, int delay_ns,
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u32 remainder;
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scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
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&remainder);
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&remainder);
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if (remainder)
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scale_needed++;
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@ -661,7 +661,7 @@ static void dspi_eoq_read(struct fsl_dspi *dspi)
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}
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static int dspi_transfer_one_message(struct spi_master *master,
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struct spi_message *message)
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struct spi_message *message)
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{
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struct fsl_dspi *dspi = spi_master_get_devdata(master);
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struct spi_device *spi = message->spi;
|
||||
|
|
@ -677,7 +677,7 @@ static int dspi_transfer_one_message(struct spi_master *master,
|
|||
dspi->cur_chip = spi_get_ctldata(spi);
|
||||
/* Prepare command word for CMD FIFO */
|
||||
dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
|
||||
SPI_PUSHR_CMD_PCS(spi->chip_select);
|
||||
SPI_PUSHR_CMD_PCS(spi->chip_select);
|
||||
if (list_is_last(&dspi->cur_transfer->transfer_list,
|
||||
&dspi->cur_msg->transfers)) {
|
||||
/* Leave PCS activated after last transfer when
|
||||
|
|
@ -718,8 +718,8 @@ static int dspi_transfer_one_message(struct spi_master *master,
|
|||
SPI_FRAME_BITS(transfer->bits_per_word));
|
||||
if (dspi->devtype_data->xspi_mode)
|
||||
regmap_write(dspi->regmap, SPI_CTARE(0),
|
||||
SPI_FRAME_EBITS(transfer->bits_per_word)
|
||||
| SPI_CTARE_DTCP(1));
|
||||
SPI_FRAME_EBITS(transfer->bits_per_word) |
|
||||
SPI_CTARE_DTCP(1));
|
||||
|
||||
trans_mode = dspi->devtype_data->trans_mode;
|
||||
switch (trans_mode) {
|
||||
|
|
@ -733,8 +733,8 @@ static int dspi_transfer_one_message(struct spi_master *master,
|
|||
break;
|
||||
case DSPI_DMA_MODE:
|
||||
regmap_write(dspi->regmap, SPI_RSER,
|
||||
SPI_RSER_TFFFE | SPI_RSER_TFFFD |
|
||||
SPI_RSER_RFDFE | SPI_RSER_RFDFD);
|
||||
SPI_RSER_TFFFE | SPI_RSER_TFFFD |
|
||||
SPI_RSER_RFDFE | SPI_RSER_RFDFD);
|
||||
status = dspi_dma_xfer(dspi);
|
||||
break;
|
||||
default:
|
||||
|
|
@ -746,7 +746,7 @@ static int dspi_transfer_one_message(struct spi_master *master,
|
|||
|
||||
if (trans_mode != DSPI_DMA_MODE) {
|
||||
if (wait_event_interruptible(dspi->waitq,
|
||||
dspi->waitflags))
|
||||
dspi->waitflags))
|
||||
dev_err(&dspi->pdev->dev,
|
||||
"wait transfer complete fail!\n");
|
||||
dspi->waitflags = 0;
|
||||
|
|
@ -785,10 +785,10 @@ static int dspi_setup(struct spi_device *spi)
|
|||
|
||||
if (!pdata) {
|
||||
of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
|
||||
&cs_sck_delay);
|
||||
&cs_sck_delay);
|
||||
|
||||
of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
|
||||
&sck_cs_delay);
|
||||
&sck_cs_delay);
|
||||
} else {
|
||||
cs_sck_delay = pdata->cs_sck_delay;
|
||||
sck_cs_delay = pdata->sck_cs_delay;
|
||||
|
|
@ -829,7 +829,7 @@ static void dspi_cleanup(struct spi_device *spi)
|
|||
struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
|
||||
|
||||
dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
|
||||
spi->master->bus_num, spi->chip_select);
|
||||
spi->master->bus_num, spi->chip_select);
|
||||
|
||||
kfree(chip);
|
||||
}
|
||||
|
|
@ -939,16 +939,16 @@ static const struct regmap_range dspi_volatile_ranges[] = {
|
|||
};
|
||||
|
||||
static const struct regmap_access_table dspi_volatile_table = {
|
||||
.yes_ranges = dspi_volatile_ranges,
|
||||
.n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
|
||||
.yes_ranges = dspi_volatile_ranges,
|
||||
.n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
|
||||
};
|
||||
|
||||
static const struct regmap_config dspi_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.max_register = 0x88,
|
||||
.volatile_table = &dspi_volatile_table,
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.max_register = 0x88,
|
||||
.volatile_table = &dspi_volatile_table,
|
||||
};
|
||||
|
||||
static const struct regmap_range dspi_xspi_volatile_ranges[] = {
|
||||
|
|
@ -959,24 +959,24 @@ static const struct regmap_range dspi_xspi_volatile_ranges[] = {
|
|||
};
|
||||
|
||||
static const struct regmap_access_table dspi_xspi_volatile_table = {
|
||||
.yes_ranges = dspi_xspi_volatile_ranges,
|
||||
.n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges),
|
||||
.yes_ranges = dspi_xspi_volatile_ranges,
|
||||
.n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges),
|
||||
};
|
||||
|
||||
static const struct regmap_config dspi_xspi_regmap_config[] = {
|
||||
{
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.max_register = 0x13c,
|
||||
.volatile_table = &dspi_xspi_volatile_table,
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.max_register = 0x13c,
|
||||
.volatile_table = &dspi_xspi_volatile_table,
|
||||
},
|
||||
{
|
||||
.name = "pushr",
|
||||
.reg_bits = 16,
|
||||
.val_bits = 16,
|
||||
.reg_stride = 2,
|
||||
.max_register = 0x2,
|
||||
.name = "pushr",
|
||||
.reg_bits = 16,
|
||||
.val_bits = 16,
|
||||
.reg_stride = 2,
|
||||
.max_register = 0x2,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1160,12 +1160,12 @@ static int dspi_remove(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
static struct platform_driver fsl_dspi_driver = {
|
||||
.driver.name = DRIVER_NAME,
|
||||
.driver.of_match_table = fsl_dspi_dt_ids,
|
||||
.driver.owner = THIS_MODULE,
|
||||
.driver.pm = &dspi_pm,
|
||||
.probe = dspi_probe,
|
||||
.remove = dspi_remove,
|
||||
.driver.name = DRIVER_NAME,
|
||||
.driver.of_match_table = fsl_dspi_dt_ids,
|
||||
.driver.owner = THIS_MODULE,
|
||||
.driver.pm = &dspi_pm,
|
||||
.probe = dspi_probe,
|
||||
.remove = dspi_remove,
|
||||
};
|
||||
module_platform_driver(fsl_dspi_driver);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue