ARM: SAMSUNG: Move IRQ UART handling for newer devices to plat-samsung
Move the handling for the UART interrupts out of the s3c64xx specific code and into plat-samsung so that it can be used by all implementations that need it. Signed-off-by: Ben Dooks <ben-linux@fluff.org>hifive-unleashed-5.1
Ben Dooks
parent
7162ba0372
commit
51022cf659
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@ -15,6 +15,7 @@ config PLAT_S3C64XX
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select ARCH_REQUIRE_GPIOLIB
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select SAMSUNG_CLKSRC
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select SAMSUNG_IRQ_VIC_TIMER
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select SAMSUNG_IRQ_UART
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select S3C_GPIO_TRACK
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select S3C_GPIO_PULL_UPDOWN
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select S3C_GPIO_CFG_S3C24XX
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@ -22,19 +22,10 @@
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#include <mach/map.h>
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#include <plat/irq-vic-timer.h>
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#include <plat/regs-serial.h>
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#include <plat/irq-uart.h>
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#include <plat/cpu.h>
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struct uart_irq {
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void __iomem *regs;
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unsigned int base_irq;
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unsigned int parent_irq;
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};
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/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
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* are consecutive when looking up the interrupt in the demux routines.
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*/
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static struct uart_irq uart_irqs[] = {
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static struct s3c_uart_irq uart_irqs[] = {
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[0] = {
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.regs = S3C_VA_UART0,
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.base_irq = IRQ_S3CUART_BASE0,
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@ -57,110 +48,9 @@ static struct uart_irq uart_irqs[] = {
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},
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};
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static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
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{
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struct uart_irq *uirq = get_irq_chip_data(irq);
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return uirq->regs;
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}
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static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
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{
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return irq & 3;
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}
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/* UART interrupt registers, not worth adding to seperate include header */
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static void s3c_irq_uart_mask(unsigned int irq)
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{
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void __iomem *regs = s3c_irq_uart_base(irq);
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unsigned int bit = s3c_irq_uart_bit(irq);
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u32 reg;
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reg = __raw_readl(regs + S3C64XX_UINTM);
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reg |= (1 << bit);
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__raw_writel(reg, regs + S3C64XX_UINTM);
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}
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static void s3c_irq_uart_maskack(unsigned int irq)
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{
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void __iomem *regs = s3c_irq_uart_base(irq);
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unsigned int bit = s3c_irq_uart_bit(irq);
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u32 reg;
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reg = __raw_readl(regs + S3C64XX_UINTM);
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reg |= (1 << bit);
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__raw_writel(reg, regs + S3C64XX_UINTM);
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__raw_writel(1 << bit, regs + S3C64XX_UINTP);
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}
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static void s3c_irq_uart_unmask(unsigned int irq)
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{
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void __iomem *regs = s3c_irq_uart_base(irq);
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unsigned int bit = s3c_irq_uart_bit(irq);
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u32 reg;
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reg = __raw_readl(regs + S3C64XX_UINTM);
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reg &= ~(1 << bit);
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__raw_writel(reg, regs + S3C64XX_UINTM);
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}
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static void s3c_irq_uart_ack(unsigned int irq)
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{
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void __iomem *regs = s3c_irq_uart_base(irq);
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unsigned int bit = s3c_irq_uart_bit(irq);
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__raw_writel(1 << bit, regs + S3C64XX_UINTP);
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}
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static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
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{
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struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0];
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u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
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int base = uirq->base_irq;
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if (pend & (1 << 0))
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generic_handle_irq(base);
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if (pend & (1 << 1))
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generic_handle_irq(base + 1);
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if (pend & (1 << 2))
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generic_handle_irq(base + 2);
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if (pend & (1 << 3))
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generic_handle_irq(base + 3);
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}
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static struct irq_chip s3c_irq_uart = {
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.name = "s3c-uart",
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.mask = s3c_irq_uart_mask,
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.unmask = s3c_irq_uart_unmask,
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.mask_ack = s3c_irq_uart_maskack,
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.ack = s3c_irq_uart_ack,
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};
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static void __init s3c64xx_uart_irq(struct uart_irq *uirq)
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{
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void __iomem *reg_base = uirq->regs;
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unsigned int irq;
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int offs;
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/* mask all interrupts at the start. */
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__raw_writel(0xf, reg_base + S3C64XX_UINTM);
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for (offs = 0; offs < 3; offs++) {
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irq = uirq->base_irq + offs;
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set_irq_chip(irq, &s3c_irq_uart);
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set_irq_chip_data(irq, uirq);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
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}
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void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
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{
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int uart;
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printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
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/* initialise the pair of VICs */
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@ -175,6 +65,5 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
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s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
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s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
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for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++)
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s3c64xx_uart_irq(&uart_irqs[uart]);
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s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
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}
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@ -26,6 +26,11 @@ config SAMSUNG_IRQ_VIC_TIMER
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help
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Internal configuration to build the VIC timer interrupt code.
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config SAMSUNG_IRQ_UART
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bool
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help
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Internal configuration to build the IRQ UART demux code.
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# options for gpio configuration support
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config S3C_GPIO_CFG_S3C24XX
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@ -17,6 +17,7 @@ obj-y += gpio-config.o
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obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
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obj-$(CONFIG_SAMSUNG_IRQ_UART) += irq-uart.o
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obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o
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# devices
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@ -0,0 +1,20 @@
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/* arch/arm/plat-samsung/include/plat/irq-uart.h
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*
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* Copyright (c) 2010 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Header file for Samsung SoC UART IRQ demux for S3C64XX and later
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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struct s3c_uart_irq {
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void __iomem *regs;
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unsigned int base_irq;
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unsigned int parent_irq;
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};
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extern void s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs);
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@ -0,0 +1,143 @@
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/* arch/arm/plat-samsung/irq-uart.c
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* originally part of arch/arm/plat-s3c64xx/irq.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* Samsung- UART Interrupt handling
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/serial_core.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/map.h>
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#include <plat/irq-uart.h>
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#include <plat/regs-serial.h>
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#include <plat/cpu.h>
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/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
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* are consecutive when looking up the interrupt in the demux routines.
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*/
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static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
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{
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struct s3c_uart_irq *uirq = get_irq_chip_data(irq);
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return uirq->regs;
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}
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static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
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{
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return irq & 3;
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}
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static void s3c_irq_uart_mask(unsigned int irq)
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{
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void __iomem *regs = s3c_irq_uart_base(irq);
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unsigned int bit = s3c_irq_uart_bit(irq);
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u32 reg;
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reg = __raw_readl(regs + S3C64XX_UINTM);
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reg |= (1 << bit);
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__raw_writel(reg, regs + S3C64XX_UINTM);
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}
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static void s3c_irq_uart_maskack(unsigned int irq)
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{
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void __iomem *regs = s3c_irq_uart_base(irq);
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unsigned int bit = s3c_irq_uart_bit(irq);
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u32 reg;
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reg = __raw_readl(regs + S3C64XX_UINTM);
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reg |= (1 << bit);
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__raw_writel(reg, regs + S3C64XX_UINTM);
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__raw_writel(1 << bit, regs + S3C64XX_UINTP);
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}
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static void s3c_irq_uart_unmask(unsigned int irq)
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{
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void __iomem *regs = s3c_irq_uart_base(irq);
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unsigned int bit = s3c_irq_uart_bit(irq);
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u32 reg;
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reg = __raw_readl(regs + S3C64XX_UINTM);
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reg &= ~(1 << bit);
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__raw_writel(reg, regs + S3C64XX_UINTM);
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}
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static void s3c_irq_uart_ack(unsigned int irq)
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{
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void __iomem *regs = s3c_irq_uart_base(irq);
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unsigned int bit = s3c_irq_uart_bit(irq);
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__raw_writel(1 << bit, regs + S3C64XX_UINTP);
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}
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static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
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{
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struct s3c_uart_irq *uirq = desc->handler_data;
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u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
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int base = uirq->base_irq;
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if (pend & (1 << 0))
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generic_handle_irq(base);
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if (pend & (1 << 1))
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generic_handle_irq(base + 1);
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if (pend & (1 << 2))
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generic_handle_irq(base + 2);
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if (pend & (1 << 3))
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generic_handle_irq(base + 3);
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}
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static struct irq_chip s3c_irq_uart = {
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.name = "s3c-uart",
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.mask = s3c_irq_uart_mask,
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.unmask = s3c_irq_uart_unmask,
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.mask_ack = s3c_irq_uart_maskack,
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.ack = s3c_irq_uart_ack,
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};
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static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
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{
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struct irq_desc *desc = irq_to_desc(uirq->parent_irq);
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void __iomem *reg_base = uirq->regs;
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unsigned int irq;
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int offs;
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/* mask all interrupts at the start. */
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__raw_writel(0xf, reg_base + S3C64XX_UINTM);
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for (offs = 0; offs < 3; offs++) {
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irq = uirq->base_irq + offs;
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set_irq_chip(irq, &s3c_irq_uart);
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set_irq_chip_data(irq, uirq);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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desc->handler_data = uirq;
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set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
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}
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/**
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* s3c_init_uart_irqs() - initialise UART IRQs and the necessary demuxing
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* @irq: The interrupt data for registering
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* @nr_irqs: The number of interrupt descriptions in @irq.
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*
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* Register the UART interrupts specified by @irq including the demuxing
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* routines. This supports the S3C6400 and newer style of devices.
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*/
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void __init s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs)
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{
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for (; nr_irqs > 0; nr_irqs--, irq++)
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s3c_init_uart_irq(irq);
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}
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