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spi: spi-fsl-espi: Log fifo counters on error 

Log RX and TX fifo counters when a transfer is done and these are not
zero.

Signed-off-by: Tiago Brusamarello <tiago.brusamarello@datacom.ind.br>
Signed-off-by: Mark Brown <broonie@kernel.org>
hifive-unleashed-5.1
Tiago Brusamarello 2018-07-26 11:12:11 -03:00 committed by Mark Brown
parent 2ca300ac6e
commit 516ddd7906
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GPG Key ID: 24D68B725D5487D0
1 changed files with 4 additions and 1 deletions
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5
drivers/spi/spi-fsl-espi.c
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@ -547,8 +547,11 @@ static void fsl_espi_cpu_irq(struct fsl_espi *espi, u32 events)
dev_err(espi->dev,
"Transfer done but SPIE_DON isn't set!\n");
if (SPIE_RXCNT(events) || SPIE_TXCNT(events) != FSL_ESPI_FIFO_SIZE)
if (SPIE_RXCNT(events) || SPIE_TXCNT(events) != FSL_ESPI_FIFO_SIZE) {
dev_err(espi->dev, "Transfer done but rx/tx fifo's aren't empty!\n");
dev_err(espi->dev, "SPIE_RXCNT = %d, SPIE_TXCNT = %d\n",
SPIE_RXCNT(events), SPIE_TXCNT(events));
}
complete(&espi->done);
}