Merge branch 'remotes/lorenzo/pci/rcar'
- Fix rcar OB window programming (Andrew Murray)
- Add rcar suspend/resume support (Kazufumi Ikeda)
- Add r8a77961 to DT binding (Yoshihiro Shimoda)
- Rename pcie-rcar.c to pcie-rcar-host.c to make room for endpoint mode
(Lad Prabhakar)
- Move shareable code to pcie-rcar.c (Lad Prabhakar)
- Correct PCIEPAMR mask calculation for "size < 128" (Lad Prabhakar)
- Add endpoint support for multiple outbound memory windows (Lad
Prabhakar)
- Add R-Car PCIe endpoint driver and DT bindings (Lad Prabhakar)
* remotes/lorenzo/pci/rcar:
MAINTAINERS: Add file patterns for rcar PCI device tree bindings
PCI: rcar: Add endpoint mode support
dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller
PCI: endpoint: Add support to handle multiple base for mapping outbound memory
PCI: endpoint: Pass page size as argument to pci_epc_mem_init()
PCI: rcar: Fix calculating mask for PCIEPAMR register
PCI: rcar: Move shareable code to a common file
PCI: rcar: Rename pcie-rcar.c to pcie-rcar-host.c
dt-bindings: pci: rcar: add r8a77961 support
PCI: rcar: Add suspend/resume
PCI: rcar: Fix incorrect programming of OB windows
This commit is contained in:
Bjorn Helgaas
commit
51755de739
77
Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
Normal file
77
Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas R-Car PCIe Endpoint
|
||||
|
||||
maintainers:
|
||||
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
|
||||
- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: renesas,r8a774c0-pcie-ep
|
||||
- const: renesas,rcar-gen3-pcie-ep
|
||||
|
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reg:
|
||||
maxItems: 5
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: apb-base
|
||||
- const: memory0
|
||||
- const: memory1
|
||||
- const: memory2
|
||||
- const: memory3
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pcie
|
||||
|
||||
max-functions:
|
||||
minimum: 1
|
||||
maximum: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- resets
|
||||
- power-domains
|
||||
- clocks
|
||||
- clock-names
|
||||
- max-functions
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
|
||||
#include <dt-bindings/power/r8a774c0-sysc.h>
|
||||
|
||||
pcie0_ep: pcie-ep@fe000000 {
|
||||
compatible = "renesas,r8a774c0-pcie-ep",
|
||||
"renesas,rcar-gen3-pcie-ep";
|
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reg = <0xfe000000 0x80000>,
|
||||
<0xfe100000 0x100000>,
|
||||
<0xfe200000 0x200000>,
|
||||
<0x30000000 0x8000000>,
|
||||
<0x38000000 0x8000000>;
|
||||
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
|
||||
resets = <&cpg 319>;
|
||||
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
|
||||
clocks = <&cpg CPG_MOD 319>;
|
||||
clock-names = "pcie";
|
||||
max-functions = /bits/ 8 <1>;
|
||||
};
|
||||
|
|
@ -11,7 +11,8 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
|
|||
"renesas,pcie-r8a7791" for the R8A7791 SoC;
|
||||
"renesas,pcie-r8a7793" for the R8A7793 SoC;
|
||||
"renesas,pcie-r8a7795" for the R8A7795 SoC;
|
||||
"renesas,pcie-r8a7796" for the R8A7796 SoC;
|
||||
"renesas,pcie-r8a7796" for the R8A77960 SoC;
|
||||
"renesas,pcie-r8a77961" for the R8A77961 SoC;
|
||||
"renesas,pcie-r8a77980" for the R8A77980 SoC;
|
||||
"renesas,pcie-r8a77990" for the R8A77990 SoC;
|
||||
"renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or
|
||||
|
|
|
|||
|
|
@ -12949,6 +12949,7 @@ M: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
|
|||
L: linux-pci@vger.kernel.org
|
||||
L: linux-renesas-soc@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/pci/*rcar*
|
||||
F: drivers/pci/controller/*rcar*
|
||||
|
||||
PCI DRIVER FOR SAMSUNG EXYNOS
|
||||
|
|
|
|||
|
|
@ -58,8 +58,26 @@ config PCIE_RCAR
|
|||
bool "Renesas R-Car PCIe controller"
|
||||
depends on ARCH_RENESAS || COMPILE_TEST
|
||||
depends on PCI_MSI_IRQ_DOMAIN
|
||||
select PCIE_RCAR_HOST
|
||||
help
|
||||
Say Y here if you want PCIe controller support on R-Car SoCs.
|
||||
This option will be removed after arm64 defconfig is updated.
|
||||
|
||||
config PCIE_RCAR_HOST
|
||||
bool "Renesas R-Car PCIe host controller"
|
||||
depends on ARCH_RENESAS || COMPILE_TEST
|
||||
depends on PCI_MSI_IRQ_DOMAIN
|
||||
help
|
||||
Say Y here if you want PCIe controller support on R-Car SoCs in host
|
||||
mode.
|
||||
|
||||
config PCIE_RCAR_EP
|
||||
bool "Renesas R-Car PCIe endpoint controller"
|
||||
depends on ARCH_RENESAS || COMPILE_TEST
|
||||
depends on PCI_ENDPOINT
|
||||
help
|
||||
Say Y here if you want PCIe controller support on R-Car SoCs in
|
||||
endpoint mode.
|
||||
|
||||
config PCI_HOST_COMMON
|
||||
tristate
|
||||
|
|
|
|||
|
|
@ -7,7 +7,8 @@ obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
|
|||
obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
|
||||
obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
|
||||
obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
|
||||
obj-$(CONFIG_PCIE_RCAR) += pcie-rcar.o
|
||||
obj-$(CONFIG_PCIE_RCAR_HOST) += pcie-rcar.o pcie-rcar-host.o
|
||||
obj-$(CONFIG_PCIE_RCAR_EP) += pcie-rcar.o pcie-rcar-ep.o
|
||||
obj-$(CONFIG_PCI_HOST_COMMON) += pci-host-common.o
|
||||
obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
|
||||
obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
|
||||
|
|
|
|||
|
|
@ -450,7 +450,7 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
|
|||
epc->max_functions = 1;
|
||||
|
||||
ret = pci_epc_mem_init(epc, pcie->mem_res->start,
|
||||
resource_size(pcie->mem_res));
|
||||
resource_size(pcie->mem_res), PAGE_SIZE);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to initialize the memory space\n");
|
||||
goto err_init;
|
||||
|
|
|
|||
|
|
@ -412,11 +412,11 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
|
|||
reg = ep->msi_cap + PCI_MSI_DATA_32;
|
||||
msg_data = dw_pcie_readw_dbi(pci, reg);
|
||||
}
|
||||
aligned_offset = msg_addr_lower & (epc->mem->page_size - 1);
|
||||
aligned_offset = msg_addr_lower & (epc->mem->window.page_size - 1);
|
||||
msg_addr = ((u64)msg_addr_upper) << 32 |
|
||||
(msg_addr_lower & ~aligned_offset);
|
||||
ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
|
||||
epc->mem->page_size);
|
||||
epc->mem->window.page_size);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -455,9 +455,9 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
|
|||
return -EPERM;
|
||||
}
|
||||
|
||||
aligned_offset = msg_addr & (epc->mem->page_size - 1);
|
||||
aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
|
||||
ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
|
||||
epc->mem->page_size);
|
||||
epc->mem->window.page_size);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -473,7 +473,7 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
|
|||
struct pci_epc *epc = ep->epc;
|
||||
|
||||
pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
|
||||
epc->mem->page_size);
|
||||
epc->mem->window.page_size);
|
||||
|
||||
pci_epc_mem_exit(epc);
|
||||
}
|
||||
|
|
@ -606,15 +606,15 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
|
|||
if (ret < 0)
|
||||
epc->max_functions = 1;
|
||||
|
||||
ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
|
||||
ep->page_size);
|
||||
ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
|
||||
ep->page_size);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Failed to initialize address space\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
|
||||
epc->mem->page_size);
|
||||
epc->mem->window.page_size);
|
||||
if (!ep->msi_mem) {
|
||||
dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
|
||||
return -ENOMEM;
|
||||
|
|
|
|||
563
drivers/pci/controller/pcie-rcar-ep.c
Normal file
563
drivers/pci/controller/pcie-rcar-ep.c
Normal file
|
|
@ -0,0 +1,563 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* PCIe endpoint driver for Renesas R-Car SoCs
|
||||
* Copyright (c) 2020 Renesas Electronics Europe GmbH
|
||||
*
|
||||
* Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/pci-epc.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "pcie-rcar.h"
|
||||
|
||||
#define RCAR_EPC_MAX_FUNCTIONS 1
|
||||
|
||||
/* Structure representing the PCIe interface */
|
||||
struct rcar_pcie_endpoint {
|
||||
struct rcar_pcie pcie;
|
||||
phys_addr_t *ob_mapped_addr;
|
||||
struct pci_epc_mem_window *ob_window;
|
||||
u8 max_functions;
|
||||
unsigned int bar_to_atu[MAX_NR_INBOUND_MAPS];
|
||||
unsigned long *ib_window_map;
|
||||
u32 num_ib_windows;
|
||||
u32 num_ob_windows;
|
||||
};
|
||||
|
||||
static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
rcar_pci_write_reg(pcie, 0, PCIETCTLR);
|
||||
|
||||
/* Set endpoint mode */
|
||||
rcar_pci_write_reg(pcie, 0, PCIEMSR);
|
||||
|
||||
/* Initialize default capabilities. */
|
||||
rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
|
||||
rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
|
||||
PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ENDPOINT << 4);
|
||||
rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
|
||||
PCI_HEADER_TYPE_NORMAL);
|
||||
|
||||
/* Write out the physical slot number = 0 */
|
||||
rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
|
||||
|
||||
val = rcar_pci_read_reg(pcie, EXPCAP(1));
|
||||
/* device supports fixed 128 bytes MPSS */
|
||||
val &= ~GENMASK(2, 0);
|
||||
rcar_pci_write_reg(pcie, val, EXPCAP(1));
|
||||
|
||||
val = rcar_pci_read_reg(pcie, EXPCAP(2));
|
||||
/* read requests size 128 bytes */
|
||||
val &= ~GENMASK(14, 12);
|
||||
/* payload size 128 bytes */
|
||||
val &= ~GENMASK(7, 5);
|
||||
rcar_pci_write_reg(pcie, val, EXPCAP(2));
|
||||
|
||||
/* Set target link speed to 5.0 GT/s */
|
||||
rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
|
||||
PCI_EXP_LNKSTA_CLS_5_0GB);
|
||||
|
||||
/* Set the completion timer timeout to the maximum 50ms. */
|
||||
rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
|
||||
|
||||
/* Terminate list of capabilities (Next Capability Offset=0) */
|
||||
rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
|
||||
|
||||
/* flush modifications */
|
||||
wmb();
|
||||
}
|
||||
|
||||
static int rcar_pcie_ep_get_window(struct rcar_pcie_endpoint *ep,
|
||||
phys_addr_t addr)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ep->num_ob_windows; i++)
|
||||
if (ep->ob_window[i].phys_base == addr)
|
||||
return i;
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int rcar_pcie_parse_outbound_ranges(struct rcar_pcie_endpoint *ep,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct rcar_pcie *pcie = &ep->pcie;
|
||||
char outbound_name[10];
|
||||
struct resource *res;
|
||||
unsigned int i = 0;
|
||||
|
||||
ep->num_ob_windows = 0;
|
||||
for (i = 0; i < RCAR_PCI_MAX_RESOURCES; i++) {
|
||||
sprintf(outbound_name, "memory%u", i);
|
||||
res = platform_get_resource_byname(pdev,
|
||||
IORESOURCE_MEM,
|
||||
outbound_name);
|
||||
if (!res) {
|
||||
dev_err(pcie->dev, "missing outbound window %u\n", i);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (!devm_request_mem_region(&pdev->dev, res->start,
|
||||
resource_size(res),
|
||||
outbound_name)) {
|
||||
dev_err(pcie->dev, "Cannot request memory region %s.\n",
|
||||
outbound_name);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
ep->ob_window[i].phys_base = res->start;
|
||||
ep->ob_window[i].size = resource_size(res);
|
||||
/* controller doesn't support multiple allocation
|
||||
* from same window, so set page_size to window size
|
||||
*/
|
||||
ep->ob_window[i].page_size = resource_size(res);
|
||||
}
|
||||
ep->num_ob_windows = i;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_pcie_ep_get_pdata(struct rcar_pcie_endpoint *ep,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct rcar_pcie *pcie = &ep->pcie;
|
||||
struct pci_epc_mem_window *window;
|
||||
struct device *dev = pcie->dev;
|
||||
struct resource res;
|
||||
int err;
|
||||
|
||||
err = of_address_to_resource(dev->of_node, 0, &res);
|
||||
if (err)
|
||||
return err;
|
||||
pcie->base = devm_ioremap_resource(dev, &res);
|
||||
if (IS_ERR(pcie->base))
|
||||
return PTR_ERR(pcie->base);
|
||||
|
||||
ep->ob_window = devm_kcalloc(dev, RCAR_PCI_MAX_RESOURCES,
|
||||
sizeof(*window), GFP_KERNEL);
|
||||
if (!ep->ob_window)
|
||||
return -ENOMEM;
|
||||
|
||||
rcar_pcie_parse_outbound_ranges(ep, pdev);
|
||||
|
||||
err = of_property_read_u8(dev->of_node, "max-functions",
|
||||
&ep->max_functions);
|
||||
if (err < 0 || ep->max_functions > RCAR_EPC_MAX_FUNCTIONS)
|
||||
ep->max_functions = RCAR_EPC_MAX_FUNCTIONS;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_pcie_ep_write_header(struct pci_epc *epc, u8 fn,
|
||||
struct pci_epf_header *hdr)
|
||||
{
|
||||
struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
|
||||
struct rcar_pcie *pcie = &ep->pcie;
|
||||
u32 val;
|
||||
|
||||
if (!fn)
|
||||
val = hdr->vendorid;
|
||||
else
|
||||
val = rcar_pci_read_reg(pcie, IDSETR0);
|
||||
val |= hdr->deviceid << 16;
|
||||
rcar_pci_write_reg(pcie, val, IDSETR0);
|
||||
|
||||
val = hdr->revid;
|
||||
val |= hdr->progif_code << 8;
|
||||
val |= hdr->subclass_code << 16;
|
||||
val |= hdr->baseclass_code << 24;
|
||||
rcar_pci_write_reg(pcie, val, IDSETR1);
|
||||
|
||||
if (!fn)
|
||||
val = hdr->subsys_vendor_id;
|
||||
else
|
||||
val = rcar_pci_read_reg(pcie, SUBIDSETR);
|
||||
val |= hdr->subsys_id << 16;
|
||||
rcar_pci_write_reg(pcie, val, SUBIDSETR);
|
||||
|
||||
if (hdr->interrupt_pin > PCI_INTERRUPT_INTA)
|
||||
return -EINVAL;
|
||||
val = rcar_pci_read_reg(pcie, PCICONF(15));
|
||||
val |= (hdr->interrupt_pin << 8);
|
||||
rcar_pci_write_reg(pcie, val, PCICONF(15));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
|
||||
struct pci_epf_bar *epf_bar)
|
||||
{
|
||||
int flags = epf_bar->flags | LAR_ENABLE | LAM_64BIT;
|
||||
struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
|
||||
u64 size = 1ULL << fls64(epf_bar->size - 1);
|
||||
dma_addr_t cpu_addr = epf_bar->phys_addr;
|
||||
enum pci_barno bar = epf_bar->barno;
|
||||
struct rcar_pcie *pcie = &ep->pcie;
|
||||
u32 mask;
|
||||
int idx;
|
||||
int err;
|
||||
|
||||
idx = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
|
||||
if (idx >= ep->num_ib_windows) {
|
||||
dev_err(pcie->dev, "no free inbound window\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
|
||||
flags |= IO_SPACE;
|
||||
|
||||
ep->bar_to_atu[bar] = idx;
|
||||
/* use 64-bit BARs */
|
||||
set_bit(idx, ep->ib_window_map);
|
||||
set_bit(idx + 1, ep->ib_window_map);
|
||||
|
||||
if (cpu_addr > 0) {
|
||||
unsigned long nr_zeros = __ffs64(cpu_addr);
|
||||
u64 alignment = 1ULL << nr_zeros;
|
||||
|
||||
size = min(size, alignment);
|
||||
}
|
||||
|
||||
size = min(size, 1ULL << 32);
|
||||
|
||||
mask = roundup_pow_of_two(size) - 1;
|
||||
mask &= ~0xf;
|
||||
|
||||
rcar_pcie_set_inbound(pcie, cpu_addr,
|
||||
0x0, mask | flags, idx, false);
|
||||
|
||||
err = rcar_pcie_wait_for_phyrdy(pcie);
|
||||
if (err) {
|
||||
dev_err(pcie->dev, "phy not ready\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rcar_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,
|
||||
struct pci_epf_bar *epf_bar)
|
||||
{
|
||||
struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
|
||||
enum pci_barno bar = epf_bar->barno;
|
||||
u32 atu_index = ep->bar_to_atu[bar];
|
||||
|
||||
rcar_pcie_set_inbound(&ep->pcie, 0x0, 0x0, 0x0, bar, false);
|
||||
|
||||
clear_bit(atu_index, ep->ib_window_map);
|
||||
clear_bit(atu_index + 1, ep->ib_window_map);
|
||||
}
|
||||
|
||||
static int rcar_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 interrupts)
|
||||
{
|
||||
struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
|
||||
struct rcar_pcie *pcie = &ep->pcie;
|
||||
u32 flags;
|
||||
|
||||
flags = rcar_pci_read_reg(pcie, MSICAP(fn));
|
||||
flags |= interrupts << MSICAP0_MMESCAP_OFFSET;
|
||||
rcar_pci_write_reg(pcie, flags, MSICAP(fn));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
|
||||
{
|
||||
struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
|
||||
struct rcar_pcie *pcie = &ep->pcie;
|
||||
u32 flags;
|
||||
|
||||
flags = rcar_pci_read_reg(pcie, MSICAP(fn));
|
||||
if (!(flags & MSICAP0_MSIE))
|
||||
return -EINVAL;
|
||||
|
||||
return ((flags & MSICAP0_MMESE_MASK) >> MSICAP0_MMESE_OFFSET);
|
||||
}
|
||||
|
||||
static int rcar_pcie_ep_map_addr(struct pci_epc *epc, u8 fn,
|
||||
phys_addr_t addr, u64 pci_addr, size_t size)
|
||||
{
|
||||
struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
|
||||
struct rcar_pcie *pcie = &ep->pcie;
|
||||
struct resource_entry win;
|
||||
struct resource res;
|
||||
int window;
|
||||
int err;
|
||||
|
||||
/* check if we have a link. */
|
||||
err = rcar_pcie_wait_for_dl(pcie);
|
||||
if (err) {
|
||||
dev_err(pcie->dev, "link not up\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
window = rcar_pcie_ep_get_window(ep, addr);
|
||||
if (window < 0) {
|
||||
dev_err(pcie->dev, "failed to get corresponding window\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
memset(&win, 0x0, sizeof(win));
|
||||
memset(&res, 0x0, sizeof(res));
|
||||
res.start = pci_addr;
|
||||
res.end = pci_addr + size - 1;
|
||||
res.flags = IORESOURCE_MEM;
|
||||
win.res = &res;
|
||||
|
||||
rcar_pcie_set_outbound(pcie, window, &win);
|
||||
|
||||
ep->ob_mapped_addr[window] = addr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rcar_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn,
|
||||
phys_addr_t addr)
|
||||
{
|
||||
struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
|
||||
struct resource_entry win;
|
||||
struct resource res;
|
||||
int idx;
|
||||
|
||||
for (idx = 0; idx < ep->num_ob_windows; idx++)
|
||||
if (ep->ob_mapped_addr[idx] == addr)
|
||||
break;
|
||||
|
||||
if (idx >= ep->num_ob_windows)
|
||||
return;
|
||||
|
||||
memset(&win, 0x0, sizeof(win));
|
||||
memset(&res, 0x0, sizeof(res));
|
||||
win.res = &res;
|
||||
rcar_pcie_set_outbound(&ep->pcie, idx, &win);
|
||||
|
||||
ep->ob_mapped_addr[idx] = 0;
|
||||
}
|
||||
|
||||
static int rcar_pcie_ep_assert_intx(struct rcar_pcie_endpoint *ep,
|
||||
u8 fn, u8 intx)
|
||||
{
|
||||
struct rcar_pcie *pcie = &ep->pcie;
|
||||
u32 val;
|
||||
|
||||
val = rcar_pci_read_reg(pcie, PCIEMSITXR);
|
||||
if ((val & PCI_MSI_FLAGS_ENABLE)) {
|
||||
dev_err(pcie->dev, "MSI is enabled, cannot assert INTx\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
val = rcar_pci_read_reg(pcie, PCICONF(1));
|
||||
if ((val & INTDIS)) {
|
||||
dev_err(pcie->dev, "INTx message transmission is disabled\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
val = rcar_pci_read_reg(pcie, PCIEINTXR);
|
||||
if ((val & ASTINTX)) {
|
||||
dev_err(pcie->dev, "INTx is already asserted\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
val |= ASTINTX;
|
||||
rcar_pci_write_reg(pcie, val, PCIEINTXR);
|
||||
usleep_range(1000, 1001);
|
||||
val = rcar_pci_read_reg(pcie, PCIEINTXR);
|
||||
val &= ~ASTINTX;
|
||||
rcar_pci_write_reg(pcie, val, PCIEINTXR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_pcie_ep_assert_msi(struct rcar_pcie *pcie,
|
||||
u8 fn, u8 interrupt_num)
|
||||
{
|
||||
u16 msi_count;
|
||||
u32 val;
|
||||
|
||||
/* Check MSI enable bit */
|
||||
val = rcar_pci_read_reg(pcie, MSICAP(fn));
|
||||
if (!(val & MSICAP0_MSIE))
|
||||
return -EINVAL;
|
||||
|
||||
/* Get MSI numbers from MME */
|
||||
msi_count = ((val & MSICAP0_MMESE_MASK) >> MSICAP0_MMESE_OFFSET);
|
||||
msi_count = 1 << msi_count;
|
||||
|
||||
if (!interrupt_num || interrupt_num > msi_count)
|
||||
return -EINVAL;
|
||||
|
||||
val = rcar_pci_read_reg(pcie, PCIEMSITXR);
|
||||
rcar_pci_write_reg(pcie, val | (interrupt_num - 1), PCIEMSITXR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
|
||||
enum pci_epc_irq_type type,
|
||||
u16 interrupt_num)
|
||||
{
|
||||
struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
|
||||
|
||||
switch (type) {
|
||||
case PCI_EPC_IRQ_LEGACY:
|
||||
return rcar_pcie_ep_assert_intx(ep, fn, 0);
|
||||
|
||||
case PCI_EPC_IRQ_MSI:
|
||||
return rcar_pcie_ep_assert_msi(&ep->pcie, fn, interrupt_num);
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static int rcar_pcie_ep_start(struct pci_epc *epc)
|
||||
{
|
||||
struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
|
||||
|
||||
rcar_pci_write_reg(&ep->pcie, MACCTLR_INIT_VAL, MACCTLR);
|
||||
rcar_pci_write_reg(&ep->pcie, CFINIT, PCIETCTLR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rcar_pcie_ep_stop(struct pci_epc *epc)
|
||||
{
|
||||
struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
|
||||
|
||||
rcar_pci_write_reg(&ep->pcie, 0, PCIETCTLR);
|
||||
}
|
||||
|
||||
static const struct pci_epc_features rcar_pcie_epc_features = {
|
||||
.linkup_notifier = false,
|
||||
.msi_capable = true,
|
||||
.msix_capable = false,
|
||||
/* use 64-bit BARs so mark BAR[1,3,5] as reserved */
|
||||
.reserved_bar = 1 << BAR_1 | 1 << BAR_3 | 1 << BAR_5,
|
||||
.bar_fixed_64bit = 1 << BAR_0 | 1 << BAR_2 | 1 << BAR_4,
|
||||
.bar_fixed_size[0] = 128,
|
||||
.bar_fixed_size[2] = 256,
|
||||
.bar_fixed_size[4] = 256,
|
||||
};
|
||||
|
||||
static const struct pci_epc_features*
|
||||
rcar_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
|
||||
{
|
||||
return &rcar_pcie_epc_features;
|
||||
}
|
||||
|
||||
static const struct pci_epc_ops rcar_pcie_epc_ops = {
|
||||
.write_header = rcar_pcie_ep_write_header,
|
||||
.set_bar = rcar_pcie_ep_set_bar,
|
||||
.clear_bar = rcar_pcie_ep_clear_bar,
|
||||
.set_msi = rcar_pcie_ep_set_msi,
|
||||
.get_msi = rcar_pcie_ep_get_msi,
|
||||
.map_addr = rcar_pcie_ep_map_addr,
|
||||
.unmap_addr = rcar_pcie_ep_unmap_addr,
|
||||
.raise_irq = rcar_pcie_ep_raise_irq,
|
||||
.start = rcar_pcie_ep_start,
|
||||
.stop = rcar_pcie_ep_stop,
|
||||
.get_features = rcar_pcie_ep_get_features,
|
||||
};
|
||||
|
||||
static const struct of_device_id rcar_pcie_ep_of_match[] = {
|
||||
{ .compatible = "renesas,r8a774c0-pcie-ep", },
|
||||
{ .compatible = "renesas,rcar-gen3-pcie-ep" },
|
||||
{ },
|
||||
};
|
||||
|
||||
static int rcar_pcie_ep_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct rcar_pcie_endpoint *ep;
|
||||
struct rcar_pcie *pcie;
|
||||
struct pci_epc *epc;
|
||||
int err;
|
||||
|
||||
ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
|
||||
if (!ep)
|
||||
return -ENOMEM;
|
||||
|
||||
pcie = &ep->pcie;
|
||||
pcie->dev = dev;
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
err = pm_runtime_get_sync(dev);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "pm_runtime_get_sync failed\n");
|
||||
goto err_pm_disable;
|
||||
}
|
||||
|
||||
err = rcar_pcie_ep_get_pdata(ep, pdev);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "failed to request resources: %d\n", err);
|
||||
goto err_pm_put;
|
||||
}
|
||||
|
||||
ep->num_ib_windows = MAX_NR_INBOUND_MAPS;
|
||||
ep->ib_window_map =
|
||||
devm_kcalloc(dev, BITS_TO_LONGS(ep->num_ib_windows),
|
||||
sizeof(long), GFP_KERNEL);
|
||||
if (!ep->ib_window_map) {
|
||||
err = -ENOMEM;
|
||||
dev_err(dev, "failed to allocate memory for inbound map\n");
|
||||
goto err_pm_put;
|
||||
}
|
||||
|
||||
ep->ob_mapped_addr = devm_kcalloc(dev, ep->num_ob_windows,
|
||||
sizeof(*ep->ob_mapped_addr),
|
||||
GFP_KERNEL);
|
||||
if (!ep->ob_mapped_addr) {
|
||||
err = -ENOMEM;
|
||||
dev_err(dev, "failed to allocate memory for outbound memory pointers\n");
|
||||
goto err_pm_put;
|
||||
}
|
||||
|
||||
epc = devm_pci_epc_create(dev, &rcar_pcie_epc_ops);
|
||||
if (IS_ERR(epc)) {
|
||||
dev_err(dev, "failed to create epc device\n");
|
||||
err = PTR_ERR(epc);
|
||||
goto err_pm_put;
|
||||
}
|
||||
|
||||
epc->max_functions = ep->max_functions;
|
||||
epc_set_drvdata(epc, ep);
|
||||
|
||||
rcar_pcie_ep_hw_init(pcie);
|
||||
|
||||
err = pci_epc_multi_mem_init(epc, ep->ob_window, ep->num_ob_windows);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "failed to initialize the epc memory space\n");
|
||||
goto err_pm_put;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_pm_put:
|
||||
pm_runtime_put(dev);
|
||||
|
||||
err_pm_disable:
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static struct platform_driver rcar_pcie_ep_driver = {
|
||||
.driver = {
|
||||
.name = "rcar-pcie-ep",
|
||||
.of_match_table = rcar_pcie_ep_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = rcar_pcie_ep_probe,
|
||||
};
|
||||
builtin_platform_driver(rcar_pcie_ep_driver);
|
||||
1130
drivers/pci/controller/pcie-rcar-host.c
Normal file
1130
drivers/pci/controller/pcie-rcar-host.c
Normal file
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
140
drivers/pci/controller/pcie-rcar.h
Normal file
140
drivers/pci/controller/pcie-rcar.h
Normal file
|
|
@ -0,0 +1,140 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* PCIe driver for Renesas R-Car SoCs
|
||||
* Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
|
||||
*
|
||||
* Author: Phil Edworthy <phil.edworthy@renesas.com>
|
||||
*/
|
||||
|
||||
#ifndef _PCIE_RCAR_H
|
||||
#define _PCIE_RCAR_H
|
||||
|
||||
#define PCIECAR 0x000010
|
||||
#define PCIECCTLR 0x000018
|
||||
#define CONFIG_SEND_ENABLE BIT(31)
|
||||
#define TYPE0 (0 << 8)
|
||||
#define TYPE1 BIT(8)
|
||||
#define PCIECDR 0x000020
|
||||
#define PCIEMSR 0x000028
|
||||
#define PCIEINTXR 0x000400
|
||||
#define ASTINTX BIT(16)
|
||||
#define PCIEPHYSR 0x0007f0
|
||||
#define PHYRDY BIT(0)
|
||||
#define PCIEMSITXR 0x000840
|
||||
|
||||
/* Transfer control */
|
||||
#define PCIETCTLR 0x02000
|
||||
#define DL_DOWN BIT(3)
|
||||
#define CFINIT BIT(0)
|
||||
#define PCIETSTR 0x02004
|
||||
#define DATA_LINK_ACTIVE BIT(0)
|
||||
#define PCIEERRFR 0x02020
|
||||
#define UNSUPPORTED_REQUEST BIT(4)
|
||||
#define PCIEMSIFR 0x02044
|
||||
#define PCIEMSIALR 0x02048
|
||||
#define MSIFE BIT(0)
|
||||
#define PCIEMSIAUR 0x0204c
|
||||
#define PCIEMSIIER 0x02050
|
||||
|
||||
/* root port address */
|
||||
#define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
|
||||
|
||||
/* local address reg & mask */
|
||||
#define PCIELAR(x) (0x02200 + ((x) * 0x20))
|
||||
#define PCIELAMR(x) (0x02208 + ((x) * 0x20))
|
||||
#define LAM_PREFETCH BIT(3)
|
||||
#define LAM_64BIT BIT(2)
|
||||
#define LAR_ENABLE BIT(1)
|
||||
|
||||
/* PCIe address reg & mask */
|
||||
#define PCIEPALR(x) (0x03400 + ((x) * 0x20))
|
||||
#define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
|
||||
#define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
|
||||
#define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
|
||||
#define PAR_ENABLE BIT(31)
|
||||
#define IO_SPACE BIT(8)
|
||||
|
||||
/* Configuration */
|
||||
#define PCICONF(x) (0x010000 + ((x) * 0x4))
|
||||
#define INTDIS BIT(10)
|
||||
#define PMCAP(x) (0x010040 + ((x) * 0x4))
|
||||
#define MSICAP(x) (0x010050 + ((x) * 0x4))
|
||||
#define MSICAP0_MSIE BIT(16)
|
||||
#define MSICAP0_MMESCAP_OFFSET 17
|
||||
#define MSICAP0_MMESE_OFFSET 20
|
||||
#define MSICAP0_MMESE_MASK GENMASK(22, 20)
|
||||
#define EXPCAP(x) (0x010070 + ((x) * 0x4))
|
||||
#define VCCAP(x) (0x010100 + ((x) * 0x4))
|
||||
|
||||
/* link layer */
|
||||
#define IDSETR0 0x011000
|
||||
#define IDSETR1 0x011004
|
||||
#define SUBIDSETR 0x011024
|
||||
#define TLCTLR 0x011048
|
||||
#define MACSR 0x011054
|
||||
#define SPCHGFIN BIT(4)
|
||||
#define SPCHGFAIL BIT(6)
|
||||
#define SPCHGSUC BIT(7)
|
||||
#define LINK_SPEED (0xf << 16)
|
||||
#define LINK_SPEED_2_5GTS (1 << 16)
|
||||
#define LINK_SPEED_5_0GTS (2 << 16)
|
||||
#define MACCTLR 0x011058
|
||||
#define MACCTLR_NFTS_MASK GENMASK(23, 16) /* The name is from SH7786 */
|
||||
#define SPEED_CHANGE BIT(24)
|
||||
#define SCRAMBLE_DISABLE BIT(27)
|
||||
#define LTSMDIS BIT(31)
|
||||
#define MACCTLR_INIT_VAL (LTSMDIS | MACCTLR_NFTS_MASK)
|
||||
#define PMSR 0x01105c
|
||||
#define MACS2R 0x011078
|
||||
#define MACCGSPSETR 0x011084
|
||||
#define SPCNGRSN BIT(31)
|
||||
|
||||
/* R-Car H1 PHY */
|
||||
#define H1_PCIEPHYADRR 0x04000c
|
||||
#define WRITE_CMD BIT(16)
|
||||
#define PHY_ACK BIT(24)
|
||||
#define RATE_POS 12
|
||||
#define LANE_POS 8
|
||||
#define ADR_POS 0
|
||||
#define H1_PCIEPHYDOUTR 0x040014
|
||||
|
||||
/* R-Car Gen2 PHY */
|
||||
#define GEN2_PCIEPHYADDR 0x780
|
||||
#define GEN2_PCIEPHYDATA 0x784
|
||||
#define GEN2_PCIEPHYCTRL 0x78c
|
||||
|
||||
#define INT_PCI_MSI_NR 32
|
||||
|
||||
#define RCONF(x) (PCICONF(0) + (x))
|
||||
#define RPMCAP(x) (PMCAP(0) + (x))
|
||||
#define REXPCAP(x) (EXPCAP(0) + (x))
|
||||
#define RVCCAP(x) (VCCAP(0) + (x))
|
||||
|
||||
#define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
|
||||
#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
|
||||
#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
|
||||
|
||||
#define RCAR_PCI_MAX_RESOURCES 4
|
||||
#define MAX_NR_INBOUND_MAPS 6
|
||||
|
||||
struct rcar_pcie {
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
};
|
||||
|
||||
enum {
|
||||
RCAR_PCI_ACCESS_READ,
|
||||
RCAR_PCI_ACCESS_WRITE,
|
||||
};
|
||||
|
||||
void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg);
|
||||
u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg);
|
||||
void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data);
|
||||
int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie);
|
||||
int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie);
|
||||
void rcar_pcie_set_outbound(struct rcar_pcie *pcie, int win,
|
||||
struct resource_entry *window);
|
||||
void rcar_pcie_set_inbound(struct rcar_pcie *pcie, u64 cpu_addr,
|
||||
u64 pci_addr, u64 flags, int idx, bool host);
|
||||
|
||||
#endif
|
||||
|
|
@ -615,7 +615,7 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev)
|
|||
rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG);
|
||||
|
||||
err = pci_epc_mem_init(epc, rockchip->mem_res->start,
|
||||
resource_size(rockchip->mem_res));
|
||||
resource_size(rockchip->mem_res), PAGE_SIZE);
|
||||
if (err < 0) {
|
||||
dev_err(dev, "failed to initialize the memory space\n");
|
||||
goto err_uninit_port;
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
static int pci_epc_mem_get_order(struct pci_epc_mem *mem, size_t size)
|
||||
{
|
||||
int order;
|
||||
unsigned int page_shift = ilog2(mem->page_size);
|
||||
unsigned int page_shift = ilog2(mem->window.page_size);
|
||||
|
||||
size--;
|
||||
size >>= page_shift;
|
||||
|
|
@ -36,62 +36,97 @@ static int pci_epc_mem_get_order(struct pci_epc_mem *mem, size_t size)
|
|||
}
|
||||
|
||||
/**
|
||||
* __pci_epc_mem_init() - initialize the pci_epc_mem structure
|
||||
* pci_epc_multi_mem_init() - initialize the pci_epc_mem structure
|
||||
* @epc: the EPC device that invoked pci_epc_mem_init
|
||||
* @phys_base: the physical address of the base
|
||||
* @size: the size of the address space
|
||||
* @page_size: size of each page
|
||||
* @windows: pointer to windows supported by the device
|
||||
* @num_windows: number of windows device supports
|
||||
*
|
||||
* Invoke to initialize the pci_epc_mem structure used by the
|
||||
* endpoint functions to allocate mapped PCI address.
|
||||
*/
|
||||
int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_base, size_t size,
|
||||
size_t page_size)
|
||||
int pci_epc_multi_mem_init(struct pci_epc *epc,
|
||||
struct pci_epc_mem_window *windows,
|
||||
unsigned int num_windows)
|
||||
{
|
||||
int ret;
|
||||
struct pci_epc_mem *mem;
|
||||
unsigned long *bitmap;
|
||||
struct pci_epc_mem *mem = NULL;
|
||||
unsigned long *bitmap = NULL;
|
||||
unsigned int page_shift;
|
||||
int pages;
|
||||
size_t page_size;
|
||||
int bitmap_size;
|
||||
int pages;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
if (page_size < PAGE_SIZE)
|
||||
page_size = PAGE_SIZE;
|
||||
epc->num_windows = 0;
|
||||
|
||||
page_shift = ilog2(page_size);
|
||||
pages = size >> page_shift;
|
||||
bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
|
||||
if (!windows || !num_windows)
|
||||
return -EINVAL;
|
||||
|
||||
mem = kzalloc(sizeof(*mem), GFP_KERNEL);
|
||||
if (!mem) {
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
epc->windows = kcalloc(num_windows, sizeof(*epc->windows), GFP_KERNEL);
|
||||
if (!epc->windows)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < num_windows; i++) {
|
||||
page_size = windows[i].page_size;
|
||||
if (page_size < PAGE_SIZE)
|
||||
page_size = PAGE_SIZE;
|
||||
page_shift = ilog2(page_size);
|
||||
pages = windows[i].size >> page_shift;
|
||||
bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
|
||||
|
||||
mem = kzalloc(sizeof(*mem), GFP_KERNEL);
|
||||
if (!mem) {
|
||||
ret = -ENOMEM;
|
||||
i--;
|
||||
goto err_mem;
|
||||
}
|
||||
|
||||
bitmap = kzalloc(bitmap_size, GFP_KERNEL);
|
||||
if (!bitmap) {
|
||||
ret = -ENOMEM;
|
||||
kfree(mem);
|
||||
i--;
|
||||
goto err_mem;
|
||||
}
|
||||
|
||||
mem->window.phys_base = windows[i].phys_base;
|
||||
mem->window.size = windows[i].size;
|
||||
mem->window.page_size = page_size;
|
||||
mem->bitmap = bitmap;
|
||||
mem->pages = pages;
|
||||
mutex_init(&mem->lock);
|
||||
epc->windows[i] = mem;
|
||||
}
|
||||
|
||||
bitmap = kzalloc(bitmap_size, GFP_KERNEL);
|
||||
if (!bitmap) {
|
||||
ret = -ENOMEM;
|
||||
goto err_mem;
|
||||
}
|
||||
|
||||
mem->bitmap = bitmap;
|
||||
mem->phys_base = phys_base;
|
||||
mem->page_size = page_size;
|
||||
mem->pages = pages;
|
||||
mem->size = size;
|
||||
mutex_init(&mem->lock);
|
||||
|
||||
epc->mem = mem;
|
||||
epc->mem = epc->windows[0];
|
||||
epc->num_windows = num_windows;
|
||||
|
||||
return 0;
|
||||
|
||||
err_mem:
|
||||
kfree(mem);
|
||||
for (; i >= 0; i--) {
|
||||
mem = epc->windows[i];
|
||||
kfree(mem->bitmap);
|
||||
kfree(mem);
|
||||
}
|
||||
kfree(epc->windows);
|
||||
|
||||
err:
|
||||
return ret;
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(__pci_epc_mem_init);
|
||||
EXPORT_SYMBOL_GPL(pci_epc_multi_mem_init);
|
||||
|
||||
int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
|
||||
size_t size, size_t page_size)
|
||||
{
|
||||
struct pci_epc_mem_window mem_window;
|
||||
|
||||
mem_window.phys_base = base;
|
||||
mem_window.size = size;
|
||||
mem_window.page_size = page_size;
|
||||
|
||||
return pci_epc_multi_mem_init(epc, &mem_window, 1);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_epc_mem_init);
|
||||
|
||||
/**
|
||||
* pci_epc_mem_exit() - cleanup the pci_epc_mem structure
|
||||
|
|
@ -102,11 +137,22 @@ EXPORT_SYMBOL_GPL(__pci_epc_mem_init);
|
|||
*/
|
||||
void pci_epc_mem_exit(struct pci_epc *epc)
|
||||
{
|
||||
struct pci_epc_mem *mem = epc->mem;
|
||||
struct pci_epc_mem *mem;
|
||||
int i;
|
||||
|
||||
if (!epc->num_windows)
|
||||
return;
|
||||
|
||||
for (i = 0; i < epc->num_windows; i++) {
|
||||
mem = epc->windows[i];
|
||||
kfree(mem->bitmap);
|
||||
kfree(mem);
|
||||
}
|
||||
kfree(epc->windows);
|
||||
|
||||
epc->windows = NULL;
|
||||
epc->mem = NULL;
|
||||
kfree(mem->bitmap);
|
||||
kfree(mem);
|
||||
epc->num_windows = 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_epc_mem_exit);
|
||||
|
||||
|
|
@ -122,31 +168,60 @@ EXPORT_SYMBOL_GPL(pci_epc_mem_exit);
|
|||
void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
|
||||
phys_addr_t *phys_addr, size_t size)
|
||||
{
|
||||
int pageno;
|
||||
void __iomem *virt_addr = NULL;
|
||||
struct pci_epc_mem *mem = epc->mem;
|
||||
unsigned int page_shift = ilog2(mem->page_size);
|
||||
struct pci_epc_mem *mem;
|
||||
unsigned int page_shift;
|
||||
size_t align_size;
|
||||
int pageno;
|
||||
int order;
|
||||
int i;
|
||||
|
||||
size = ALIGN(size, mem->page_size);
|
||||
order = pci_epc_mem_get_order(mem, size);
|
||||
for (i = 0; i < epc->num_windows; i++) {
|
||||
mem = epc->windows[i];
|
||||
mutex_lock(&mem->lock);
|
||||
align_size = ALIGN(size, mem->window.page_size);
|
||||
order = pci_epc_mem_get_order(mem, align_size);
|
||||
|
||||
mutex_lock(&mem->lock);
|
||||
pageno = bitmap_find_free_region(mem->bitmap, mem->pages, order);
|
||||
if (pageno < 0)
|
||||
goto ret;
|
||||
pageno = bitmap_find_free_region(mem->bitmap, mem->pages,
|
||||
order);
|
||||
if (pageno >= 0) {
|
||||
page_shift = ilog2(mem->window.page_size);
|
||||
*phys_addr = mem->window.phys_base +
|
||||
((phys_addr_t)pageno << page_shift);
|
||||
virt_addr = ioremap(*phys_addr, align_size);
|
||||
if (!virt_addr) {
|
||||
bitmap_release_region(mem->bitmap,
|
||||
pageno, order);
|
||||
mutex_unlock(&mem->lock);
|
||||
continue;
|
||||
}
|
||||
mutex_unlock(&mem->lock);
|
||||
return virt_addr;
|
||||
}
|
||||
mutex_unlock(&mem->lock);
|
||||
}
|
||||
|
||||
*phys_addr = mem->phys_base + ((phys_addr_t)pageno << page_shift);
|
||||
virt_addr = ioremap(*phys_addr, size);
|
||||
if (!virt_addr)
|
||||
bitmap_release_region(mem->bitmap, pageno, order);
|
||||
|
||||
ret:
|
||||
mutex_unlock(&mem->lock);
|
||||
return virt_addr;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr);
|
||||
|
||||
static struct pci_epc_mem *pci_epc_get_matching_window(struct pci_epc *epc,
|
||||
phys_addr_t phys_addr)
|
||||
{
|
||||
struct pci_epc_mem *mem;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < epc->num_windows; i++) {
|
||||
mem = epc->windows[i];
|
||||
|
||||
if (phys_addr >= mem->window.phys_base &&
|
||||
phys_addr < (mem->window.phys_base + mem->window.size))
|
||||
return mem;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* pci_epc_mem_free_addr() - free the allocated memory address
|
||||
* @epc: the EPC device on which memory was allocated
|
||||
|
|
@ -159,14 +234,23 @@ EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr);
|
|||
void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
|
||||
void __iomem *virt_addr, size_t size)
|
||||
{
|
||||
struct pci_epc_mem *mem;
|
||||
unsigned int page_shift;
|
||||
size_t page_size;
|
||||
int pageno;
|
||||
struct pci_epc_mem *mem = epc->mem;
|
||||
unsigned int page_shift = ilog2(mem->page_size);
|
||||
int order;
|
||||
|
||||
mem = pci_epc_get_matching_window(epc, phys_addr);
|
||||
if (!mem) {
|
||||
pr_err("failed to get matching window\n");
|
||||
return;
|
||||
}
|
||||
|
||||
page_size = mem->window.page_size;
|
||||
page_shift = ilog2(page_size);
|
||||
iounmap(virt_addr);
|
||||
pageno = (phys_addr - mem->phys_base) >> page_shift;
|
||||
size = ALIGN(size, mem->page_size);
|
||||
pageno = (phys_addr - mem->window.phys_base) >> page_shift;
|
||||
size = ALIGN(size, page_size);
|
||||
order = pci_epc_mem_get_order(mem, size);
|
||||
mutex_lock(&mem->lock);
|
||||
bitmap_release_region(mem->bitmap, pageno, order);
|
||||
|
|
|
|||
|
|
@ -65,20 +65,28 @@ struct pci_epc_ops {
|
|||
struct module *owner;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pci_epc_mem_window - address window of the endpoint controller
|
||||
* @phys_base: physical base address of the PCI address window
|
||||
* @size: the size of the PCI address window
|
||||
* @page_size: size of each page
|
||||
*/
|
||||
struct pci_epc_mem_window {
|
||||
phys_addr_t phys_base;
|
||||
size_t size;
|
||||
size_t page_size;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct pci_epc_mem - address space of the endpoint controller
|
||||
* @phys_base: physical base address of the PCI address space
|
||||
* @size: the size of the PCI address space
|
||||
* @window: address window of the endpoint controller
|
||||
* @bitmap: bitmap to manage the PCI address space
|
||||
* @pages: number of bits representing the address region
|
||||
* @page_size: size of each page
|
||||
* @lock: mutex to protect bitmap
|
||||
*/
|
||||
struct pci_epc_mem {
|
||||
phys_addr_t phys_base;
|
||||
size_t size;
|
||||
struct pci_epc_mem_window window;
|
||||
unsigned long *bitmap;
|
||||
size_t page_size;
|
||||
int pages;
|
||||
/* mutex to protect against concurrent access for memory allocation*/
|
||||
struct mutex lock;
|
||||
|
|
@ -89,7 +97,11 @@ struct pci_epc_mem {
|
|||
* @dev: PCI EPC device
|
||||
* @pci_epf: list of endpoint functions present in this EPC device
|
||||
* @ops: function pointers for performing endpoint operations
|
||||
* @mem: address space of the endpoint controller
|
||||
* @windows: array of address space of the endpoint controller
|
||||
* @mem: first window of the endpoint controller, which corresponds to
|
||||
* default address space of the endpoint controller supporting
|
||||
* single window.
|
||||
* @num_windows: number of windows supported by device
|
||||
* @max_functions: max number of functions that can be configured in this EPC
|
||||
* @group: configfs group representing the PCI EPC device
|
||||
* @lock: mutex to protect pci_epc ops
|
||||
|
|
@ -100,7 +112,9 @@ struct pci_epc {
|
|||
struct device dev;
|
||||
struct list_head pci_epf;
|
||||
const struct pci_epc_ops *ops;
|
||||
struct pci_epc_mem **windows;
|
||||
struct pci_epc_mem *mem;
|
||||
unsigned int num_windows;
|
||||
u8 max_functions;
|
||||
struct config_group *group;
|
||||
/* mutex to protect against concurrent access of EP controller */
|
||||
|
|
@ -137,9 +151,6 @@ struct pci_epc_features {
|
|||
#define devm_pci_epc_create(dev, ops) \
|
||||
__devm_pci_epc_create((dev), (ops), THIS_MODULE)
|
||||
|
||||
#define pci_epc_mem_init(epc, phys_addr, size) \
|
||||
__pci_epc_mem_init((epc), (phys_addr), (size), PAGE_SIZE)
|
||||
|
||||
static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
|
||||
{
|
||||
dev_set_drvdata(&epc->dev, data);
|
||||
|
|
@ -195,8 +206,11 @@ unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features
|
|||
struct pci_epc *pci_epc_get(const char *epc_name);
|
||||
void pci_epc_put(struct pci_epc *epc);
|
||||
|
||||
int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_addr, size_t size,
|
||||
size_t page_size);
|
||||
int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
|
||||
size_t size, size_t page_size);
|
||||
int pci_epc_multi_mem_init(struct pci_epc *epc,
|
||||
struct pci_epc_mem_window *window,
|
||||
unsigned int num_windows);
|
||||
void pci_epc_mem_exit(struct pci_epc *epc);
|
||||
void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
|
||||
phys_addr_t *phys_addr, size_t size);
|
||||
|
|
|
|||
Loading…
Reference in a new issue