Microblaze patches for 5.4-rc1
- Clean up reset gpio handler - Defconfig updates - Add support for 8 byte get_user() - Switch to generic dma code In merge please fix dma_atomic_pool_init reported also by: https://lkml.org/lkml/2019/9/2/393 or https://lore.kernel.org/linux-next/20190902214011.2a5400c9@canb.auug.org.au/ -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCXYnguwAKCRDKSWXLKUoM IaF8AKCawdYH+58xRg7riR7Evbv2kM0ghwCfXosnu6Ncv07UEY9Tv5zx/qibafk= =yI3X -----END PGP SIGNATURE----- Merge tag 'microblaze-v5.4-rc1' of git://git.monstr.eu/linux-2.6-microblaze Pull Microblaze updates from Michal Simek: - clean up reset gpio handler - defconfig updates - add support for 8 byte get_user() - switch to generic dma code * tag 'microblaze-v5.4-rc1' of git://git.monstr.eu/linux-2.6-microblaze: microblaze: Switch to standard restart handler microblaze: defconfig synchronization microblaze: Enable Xilinx AXI emac driver by default arch/microblaze: support get_user() of size 8 bytes microblaze: remove ioremap_fullcache microblaze: use the generic dma coherent remap allocator microblaze/nommu: use the generic uncached segment supportalistair/sunxi64-5.4-dsi
Linus Torvalds
commit
5184d44960
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@ -5,15 +5,18 @@ config MICROBLAZE
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select ARCH_NO_SWAP
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select ARCH_HAS_BINFMT_FLAT if !MMU
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select ARCH_HAS_DMA_COHERENT_TO_PFN if MMU
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select ARCH_HAS_DMA_PREP_COHERENT
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select ARCH_HAS_GCOV_PROFILE_ALL
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select ARCH_HAS_SYNC_DMA_FOR_CPU
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE
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select ARCH_HAS_UNCACHED_SEGMENT if !MMU
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select ARCH_MIGHT_HAVE_PC_PARPORT
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select ARCH_WANT_IPC_PARSE_VERSION
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select BUILDTIME_EXTABLE_SORT
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select TIMER_OF
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select CLONE_BACKWARDS3
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select COMMON_CLK
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select DMA_DIRECT_REMAP if MMU
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select GENERIC_ATOMIC64
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select GENERIC_CLOCKEVENTS
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select GENERIC_CPU_DEVICES
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@ -18,7 +18,6 @@
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,microblaze";
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hard-reset-gpios = <&LEDs_8Bit 2 1>;
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model = "testing";
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DDR2_SDRAM: memory@90000000 {
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device_type = "memory";
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@ -281,6 +280,21 @@
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gpios = <&LEDs_8Bit 7 1>;
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};
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} ;
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gpio-restart {
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compatible = "gpio-restart";
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/*
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* FIXME: is this active low or active high?
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* the current flag (1) indicates active low.
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* delay measures are templates, should be adjusted
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* to datasheet or trial-and-error with real hardware.
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*/
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gpios = <&LEDs_8Bit 2 1>;
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active-delay = <100>;
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inactive-delay = <10>;
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wait-delay = <100>;
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};
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RS232_Uart_1: serial@84000000 {
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clock-frequency = <125000000>;
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compatible = "xlnx,xps-uartlite-1.00.a";
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@ -5,15 +5,10 @@ CONFIG_IKCONFIG=y
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CONFIG_IKCONFIG_PROC=y
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CONFIG_SYSFS_DEPRECATED=y
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CONFIG_SYSFS_DEPRECATED_V2=y
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CONFIG_KALLSYMS_ALL=y
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# CONFIG_BASE_FULL is not set
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CONFIG_KALLSYMS_ALL=y
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CONFIG_EMBEDDED=y
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CONFIG_SLAB=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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# CONFIG_BLK_DEV_BSG is not set
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CONFIG_PARTITION_ADVANCED=y
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# CONFIG_EFI_PARTITION is not set
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CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
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CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR=1
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CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
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@ -25,14 +20,19 @@ CONFIG_MMU=y
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CONFIG_CMDLINE_BOOL=y
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CONFIG_CMDLINE_FORCE=y
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CONFIG_HIGHMEM=y
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CONFIG_PCI=y
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CONFIG_PCI_XILINX=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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# CONFIG_BLK_DEV_BSG is not set
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CONFIG_PARTITION_ADVANCED=y
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# CONFIG_EFI_PARTITION is not set
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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CONFIG_INET=y
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# CONFIG_IPV6 is not set
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CONFIG_BRIDGE=m
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CONFIG_PCI=y
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CONFIG_MTD=y
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CONFIG_MTD_CFI=y
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CONFIG_MTD_CFI_INTELEXT=y
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@ -41,6 +41,7 @@ CONFIG_BLK_DEV_RAM=y
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CONFIG_BLK_DEV_RAM_SIZE=8192
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CONFIG_NETDEVICES=y
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CONFIG_XILINX_EMACLITE=y
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CONFIG_XILINX_AXI_EMAC=y
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CONFIG_XILINX_LL_TEMAC=y
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# CONFIG_INPUT is not set
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# CONFIG_SERIO is not set
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@ -59,6 +60,8 @@ CONFIG_SPI_XILINX=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_SYSFS=y
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CONFIG_GPIO_XILINX=y
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CONFIG_POWER_RESET=y
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CONFIG_POWER_RESET_GPIO_RESTART=y
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# CONFIG_HWMON is not set
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CONFIG_WATCHDOG=y
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CONFIG_XILINX_WATCHDOG=y
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@ -74,8 +77,8 @@ CONFIG_CRAMFS=y
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CONFIG_ROMFS_FS=y
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CONFIG_NFS_FS=y
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CONFIG_CIFS=y
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CONFIG_CIFS_STATS=y
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CONFIG_CIFS_STATS2=y
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CONFIG_ENCRYPTED_KEYS=y
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CONFIG_DEBUG_INFO=y
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CONFIG_DEBUG_SLAB=y
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CONFIG_DETECT_HUNG_TASK=y
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@ -83,6 +86,3 @@ CONFIG_DEBUG_SPINLOCK=y
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CONFIG_KGDB=y
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CONFIG_KGDB_TESTS=y
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CONFIG_KGDB_KDB=y
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CONFIG_EARLY_PRINTK=y
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CONFIG_KEYS=y
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CONFIG_ENCRYPTED_KEYS=y
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@ -7,15 +7,10 @@ CONFIG_IKCONFIG=y
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CONFIG_IKCONFIG_PROC=y
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CONFIG_SYSFS_DEPRECATED=y
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CONFIG_SYSFS_DEPRECATED_V2=y
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CONFIG_KALLSYMS_ALL=y
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# CONFIG_BASE_FULL is not set
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CONFIG_KALLSYMS_ALL=y
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CONFIG_EMBEDDED=y
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CONFIG_SLAB=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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# CONFIG_BLK_DEV_BSG is not set
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CONFIG_PARTITION_ADVANCED=y
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# CONFIG_EFI_PARTITION is not set
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CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
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CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR=1
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CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
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@ -25,13 +20,18 @@ CONFIG_XILINX_MICROBLAZE0_USE_FPU=2
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CONFIG_HZ_100=y
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CONFIG_CMDLINE_BOOL=y
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CONFIG_CMDLINE_FORCE=y
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CONFIG_PCI=y
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CONFIG_PCI_XILINX=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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# CONFIG_BLK_DEV_BSG is not set
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CONFIG_PARTITION_ADVANCED=y
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# CONFIG_EFI_PARTITION is not set
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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CONFIG_INET=y
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# CONFIG_IPV6 is not set
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CONFIG_PCI=y
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CONFIG_MTD=y
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CONFIG_MTD_CMDLINE_PARTS=y
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CONFIG_MTD_BLOCK=y
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@ -62,6 +62,8 @@ CONFIG_SPI_XILINX=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_SYSFS=y
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CONFIG_GPIO_XILINX=y
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CONFIG_POWER_RESET=y
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CONFIG_POWER_RESET_GPIO_RESTART=y
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# CONFIG_HWMON is not set
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CONFIG_WATCHDOG=y
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CONFIG_XILINX_WATCHDOG=y
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@ -75,11 +77,6 @@ CONFIG_ROMFS_FS=y
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CONFIG_NFS_FS=y
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CONFIG_NFS_V3_ACL=y
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CONFIG_NLS=y
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CONFIG_DEBUG_INFO=y
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CONFIG_DEBUG_SLAB=y
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CONFIG_DETECT_HUNG_TASK=y
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CONFIG_DEBUG_SPINLOCK=y
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CONFIG_EARLY_PRINTK=y
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CONFIG_KEYS=y
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CONFIG_ENCRYPTED_KEYS=y
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CONFIG_CRYPTO_ECB=y
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@ -87,3 +84,7 @@ CONFIG_CRYPTO_MD4=y
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CONFIG_CRYPTO_MD5=y
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CONFIG_CRYPTO_ARC4=y
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CONFIG_CRYPTO_DES=y
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CONFIG_DEBUG_INFO=y
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CONFIG_DEBUG_SLAB=y
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CONFIG_DETECT_HUNG_TASK=y
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CONFIG_DEBUG_SPINLOCK=y
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@ -40,7 +40,6 @@ extern void iounmap(volatile void __iomem *addr);
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extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
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#define ioremap_nocache(addr, size) ioremap((addr), (size))
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#define ioremap_fullcache(addr, size) ioremap((addr), (size))
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#define ioremap_wc(addr, size) ioremap((addr), (size))
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#define ioremap_wt(addr, size) ioremap((addr), (size))
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@ -163,44 +163,15 @@ extern long __user_bad(void);
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* Returns zero on success, or -EFAULT on error.
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* On error, the variable @x is set to zero.
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*/
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#define get_user(x, ptr) \
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__get_user_check((x), (ptr), sizeof(*(ptr)))
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#define __get_user_check(x, ptr, size) \
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({ \
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unsigned long __gu_val = 0; \
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const typeof(*(ptr)) __user *__gu_addr = (ptr); \
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int __gu_err = 0; \
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\
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if (access_ok(__gu_addr, size)) { \
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switch (size) { \
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case 1: \
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__get_user_asm("lbu", __gu_addr, __gu_val, \
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__gu_err); \
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break; \
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case 2: \
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__get_user_asm("lhu", __gu_addr, __gu_val, \
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__gu_err); \
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break; \
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case 4: \
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__get_user_asm("lw", __gu_addr, __gu_val, \
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__gu_err); \
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break; \
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default: \
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__gu_err = __user_bad(); \
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break; \
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} \
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} else { \
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__gu_err = -EFAULT; \
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} \
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x = (__force typeof(*(ptr)))__gu_val; \
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__gu_err; \
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#define get_user(x, ptr) ({ \
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const typeof(*(ptr)) __user *__gu_ptr = (ptr); \
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access_ok(__gu_ptr, sizeof(*__gu_ptr)) ? \
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__get_user(x, __gu_ptr) : -EFAULT; \
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})
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#define __get_user(x, ptr) \
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({ \
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unsigned long __gu_val = 0; \
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/*unsigned long __gu_ptr = (unsigned long)(ptr);*/ \
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long __gu_err; \
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switch (sizeof(*(ptr))) { \
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case 1: \
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@ -212,6 +183,11 @@ extern long __user_bad(void);
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case 4: \
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__get_user_asm("lw", (ptr), __gu_val, __gu_err); \
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break; \
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case 8: \
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__gu_err = __copy_from_user(&__gu_val, ptr, 8); \
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if (__gu_err) \
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__gu_err = -EFAULT; \
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break; \
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default: \
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/* __gu_val = 0; __gu_err = -EINVAL;*/ __gu_err = __user_bad();\
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} \
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@ -8,83 +8,9 @@
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*/
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/of_platform.h>
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/* Trigger specific functions */
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#ifdef CONFIG_GPIOLIB
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#include <linux/of_gpio.h>
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static int handle; /* reset pin handle */
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static unsigned int reset_val;
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static int of_platform_reset_gpio_probe(void)
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{
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int ret;
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handle = of_get_named_gpio(of_find_node_by_path("/"),
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"hard-reset-gpios", 0);
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if (!gpio_is_valid(handle)) {
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pr_info("Skipping unavailable RESET gpio %d (%s)\n",
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handle, "reset");
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return -ENODEV;
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}
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ret = gpio_request(handle, "reset");
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if (ret < 0) {
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pr_info("GPIO pin is already allocated\n");
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return ret;
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}
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/* get current setup value */
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reset_val = gpio_get_value(handle);
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/* FIXME maybe worth to perform any action */
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pr_debug("Reset: Gpio output state: 0x%x\n", reset_val);
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|
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/* Setup GPIO as output */
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ret = gpio_direction_output(handle, 0);
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if (ret < 0)
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goto err;
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||||
|
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/* Setup output direction */
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gpio_set_value(handle, 0);
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||||
|
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pr_info("RESET: Registered gpio device: %d, current val: %d\n",
|
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handle, reset_val);
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||||
return 0;
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||||
err:
|
||||
gpio_free(handle);
|
||||
return ret;
|
||||
}
|
||||
device_initcall(of_platform_reset_gpio_probe);
|
||||
|
||||
|
||||
static void gpio_system_reset(void)
|
||||
{
|
||||
if (gpio_is_valid(handle))
|
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gpio_set_value(handle, 1 - reset_val);
|
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else
|
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pr_notice("Reset GPIO unavailable - halting!\n");
|
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}
|
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#else
|
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static void gpio_system_reset(void)
|
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{
|
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pr_notice("No reset GPIO present - halting!\n");
|
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}
|
||||
|
||||
void of_platform_reset_gpio_probe(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
void machine_restart(char *cmd)
|
||||
{
|
||||
pr_notice("Machine restart...\n");
|
||||
gpio_system_reset();
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
#include <linux/reboot.h>
|
||||
|
||||
void machine_shutdown(void)
|
||||
{
|
||||
|
|
@ -106,3 +32,12 @@ void machine_power_off(void)
|
|||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
void machine_restart(char *cmd)
|
||||
{
|
||||
do_kernel_restart(cmd);
|
||||
/* Give the restart hook 1 s to take us down */
|
||||
mdelay(1000);
|
||||
pr_emerg("Reboot failed -- System halted\n");
|
||||
while (1);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,217 +4,56 @@
|
|||
* Copyright (C) 2010 Michal Simek <monstr@monstr.eu>
|
||||
* Copyright (C) 2010 PetaLogix
|
||||
* Copyright (C) 2005 John Williams <jwilliams@itee.uq.edu.au>
|
||||
*
|
||||
* Based on PowerPC version derived from arch/arm/mm/consistent.c
|
||||
* Copyright (C) 2001 Dan Malek (dmalek@jlc.net)
|
||||
* Copyright (C) 2000 Russell King
|
||||
*/
|
||||
|
||||
#include <linux/export.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/mman.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/swap.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/highmem.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/gfp.h>
|
||||
#include <linux/dma-noncoherent.h>
|
||||
|
||||
#include <asm/pgalloc.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/hardirq.h>
|
||||
#include <linux/mmu_context.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/cpuinfo.h>
|
||||
#include <asm/tlbflush.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
#ifndef CONFIG_MMU
|
||||
/* I have to use dcache values because I can't relate on ram size */
|
||||
# define UNCACHED_SHADOW_MASK (cpuinfo.dcache_high - cpuinfo.dcache_base + 1)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Consistent memory allocators. Used for DMA devices that want to
|
||||
* share uncached memory with the processor core.
|
||||
* My crufty no-MMU approach is simple. In the HW platform we can optionally
|
||||
* mirror the DDR up above the processor cacheable region. So, memory accessed
|
||||
* in this mirror region will not be cached. It's alloced from the same
|
||||
* pool as normal memory, but the handle we return is shifted up into the
|
||||
* uncached region. This will no doubt cause big problems if memory allocated
|
||||
* here is not also freed properly. -- JW
|
||||
*/
|
||||
void *arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
|
||||
gfp_t gfp, unsigned long attrs)
|
||||
void arch_dma_prep_coherent(struct page *page, size_t size)
|
||||
{
|
||||
unsigned long order, vaddr;
|
||||
void *ret;
|
||||
unsigned int i, err = 0;
|
||||
struct page *page, *end;
|
||||
phys_addr_t paddr = page_to_phys(page);
|
||||
|
||||
#ifdef CONFIG_MMU
|
||||
phys_addr_t pa;
|
||||
struct vm_struct *area;
|
||||
unsigned long va;
|
||||
#endif
|
||||
|
||||
if (in_interrupt())
|
||||
BUG();
|
||||
|
||||
/* Only allocate page size areas. */
|
||||
size = PAGE_ALIGN(size);
|
||||
order = get_order(size);
|
||||
|
||||
vaddr = __get_free_pages(gfp | __GFP_ZERO, order);
|
||||
if (!vaddr)
|
||||
return NULL;
|
||||
|
||||
/*
|
||||
* we need to ensure that there are no cachelines in use,
|
||||
* or worse dirty in this area.
|
||||
*/
|
||||
flush_dcache_range(virt_to_phys((void *)vaddr),
|
||||
virt_to_phys((void *)vaddr) + size);
|
||||
flush_dcache_range(paddr, paddr + size);
|
||||
}
|
||||
|
||||
#ifndef CONFIG_MMU
|
||||
ret = (void *)vaddr;
|
||||
/*
|
||||
* Here's the magic! Note if the uncached shadow is not implemented,
|
||||
* it's up to the calling code to also test that condition and make
|
||||
* other arranegments, such as manually flushing the cache and so on.
|
||||
*/
|
||||
# ifdef CONFIG_XILINX_UNCACHED_SHADOW
|
||||
ret = (void *)((unsigned) ret | UNCACHED_SHADOW_MASK);
|
||||
# endif
|
||||
if ((unsigned int)ret > cpuinfo.dcache_base &&
|
||||
(unsigned int)ret < cpuinfo.dcache_high)
|
||||
/*
|
||||
* Consistent memory allocators. Used for DMA devices that want to share
|
||||
* uncached memory with the processor core. My crufty no-MMU approach is
|
||||
* simple. In the HW platform we can optionally mirror the DDR up above the
|
||||
* processor cacheable region. So, memory accessed in this mirror region will
|
||||
* not be cached. It's alloced from the same pool as normal memory, but the
|
||||
* handle we return is shifted up into the uncached region. This will no doubt
|
||||
* cause big problems if memory allocated here is not also freed properly. -- JW
|
||||
*
|
||||
* I have to use dcache values because I can't relate on ram size:
|
||||
*/
|
||||
#ifdef CONFIG_XILINX_UNCACHED_SHADOW
|
||||
#define UNCACHED_SHADOW_MASK (cpuinfo.dcache_high - cpuinfo.dcache_base + 1)
|
||||
#else
|
||||
#define UNCACHED_SHADOW_MASK 0
|
||||
#endif /* CONFIG_XILINX_UNCACHED_SHADOW */
|
||||
|
||||
void *uncached_kernel_address(void *ptr)
|
||||
{
|
||||
unsigned long addr = (unsigned long)ptr;
|
||||
|
||||
addr |= UNCACHED_SHADOW_MASK;
|
||||
if (addr > cpuinfo.dcache_base && addr < cpuinfo.dcache_high)
|
||||
pr_warn("ERROR: Your cache coherent area is CACHED!!!\n");
|
||||
|
||||
/* dma_handle is same as physical (shadowed) address */
|
||||
*dma_handle = (dma_addr_t)ret;
|
||||
#else
|
||||
/* Allocate some common virtual space to map the new pages. */
|
||||
area = get_vm_area(size, VM_ALLOC);
|
||||
if (!area) {
|
||||
free_pages(vaddr, order);
|
||||
return NULL;
|
||||
}
|
||||
va = (unsigned long) area->addr;
|
||||
ret = (void *)va;
|
||||
|
||||
/* This gives us the real physical address of the first page. */
|
||||
*dma_handle = pa = __virt_to_phys(vaddr);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* free wasted pages. We skip the first page since we know
|
||||
* that it will have count = 1 and won't require freeing.
|
||||
* We also mark the pages in use as reserved so that
|
||||
* remap_page_range works.
|
||||
*/
|
||||
page = virt_to_page(vaddr);
|
||||
end = page + (1 << order);
|
||||
|
||||
split_page(page, order);
|
||||
|
||||
for (i = 0; i < size && err == 0; i += PAGE_SIZE) {
|
||||
#ifdef CONFIG_MMU
|
||||
/* MS: This is the whole magic - use cache inhibit pages */
|
||||
err = map_page(va + i, pa + i, _PAGE_KERNEL | _PAGE_NO_CACHE);
|
||||
#endif
|
||||
|
||||
SetPageReserved(page);
|
||||
page++;
|
||||
}
|
||||
|
||||
/* Free the otherwise unused pages. */
|
||||
while (page < end) {
|
||||
__free_page(page);
|
||||
page++;
|
||||
}
|
||||
|
||||
if (err) {
|
||||
free_pages(vaddr, order);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return ret;
|
||||
return (void *)addr;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MMU
|
||||
static pte_t *consistent_virt_to_pte(void *vaddr)
|
||||
void *cached_kernel_address(void *ptr)
|
||||
{
|
||||
unsigned long addr = (unsigned long)vaddr;
|
||||
unsigned long addr = (unsigned long)ptr;
|
||||
|
||||
return pte_offset_kernel(pmd_offset(pgd_offset_k(addr), addr), addr);
|
||||
}
|
||||
|
||||
long arch_dma_coherent_to_pfn(struct device *dev, void *vaddr,
|
||||
dma_addr_t dma_addr)
|
||||
{
|
||||
pte_t *ptep = consistent_virt_to_pte(vaddr);
|
||||
|
||||
if (pte_none(*ptep) || !pte_present(*ptep))
|
||||
return 0;
|
||||
|
||||
return pte_pfn(*ptep);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* free page(s) as defined by the above mapping.
|
||||
*/
|
||||
void arch_dma_free(struct device *dev, size_t size, void *vaddr,
|
||||
dma_addr_t dma_addr, unsigned long attrs)
|
||||
{
|
||||
struct page *page;
|
||||
|
||||
if (in_interrupt())
|
||||
BUG();
|
||||
|
||||
size = PAGE_ALIGN(size);
|
||||
|
||||
#ifndef CONFIG_MMU
|
||||
/* Clear SHADOW_MASK bit in address, and free as per usual */
|
||||
# ifdef CONFIG_XILINX_UNCACHED_SHADOW
|
||||
vaddr = (void *)((unsigned)vaddr & ~UNCACHED_SHADOW_MASK);
|
||||
# endif
|
||||
page = virt_to_page(vaddr);
|
||||
|
||||
do {
|
||||
__free_reserved_page(page);
|
||||
page++;
|
||||
} while (size -= PAGE_SIZE);
|
||||
#else
|
||||
do {
|
||||
pte_t *ptep = consistent_virt_to_pte(vaddr);
|
||||
unsigned long pfn;
|
||||
|
||||
if (!pte_none(*ptep) && pte_present(*ptep)) {
|
||||
pfn = pte_pfn(*ptep);
|
||||
pte_clear(&init_mm, (unsigned int)vaddr, ptep);
|
||||
if (pfn_valid(pfn)) {
|
||||
page = pfn_to_page(pfn);
|
||||
__free_reserved_page(page);
|
||||
}
|
||||
}
|
||||
vaddr += PAGE_SIZE;
|
||||
} while (size -= PAGE_SIZE);
|
||||
|
||||
/* flush tlb */
|
||||
flush_tlb_all();
|
||||
#endif
|
||||
return (void *)(addr & ~UNCACHED_SHADOW_MASK);
|
||||
}
|
||||
#endif /* CONFIG_MMU */
|
||||
|
|
|
|||
Loading…
Reference in New Issue