mfd: stpmic1: Add STPMIC1 driver
STPMIC1 is a PMIC from STMicroelectronics. The STPMIC1 integrates 10 regulators, 3 power switches, a watchdog and an input for a power on key. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>hifive-unleashed-5.1
Pascal PAILLET-LME
Lee Jones
parent
3eafbd3a77
commit
51908d2e9b
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@ -1871,6 +1871,22 @@ config MFD_STM32_TIMERS
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for PWM and IIO Timer. This driver allow to share the
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registers between the others drivers.
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config MFD_STPMIC1
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tristate "Support for STPMIC1 PMIC"
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depends on (I2C=y && OF)
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select REGMAP_I2C
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select REGMAP_IRQ
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select MFD_CORE
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help
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Support for ST Microelectronics STPMIC1 PMIC. STPMIC1 has power on
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key, watchdog and regulator functionalities which are supported via
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the relevant subsystems. This driver provides core support for the
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STPMIC1. In order to use the actual functionaltiy of the device other
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drivers must be enabled.
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To compile this driver as a module, choose M here: the
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module will be called stpmic1.
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menu "Multimedia Capabilities Port drivers"
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depends on ARCH_SA1100
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@ -233,6 +233,7 @@ obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += intel_soc_pmic_chtdc_ti.o
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obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
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obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
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obj-$(CONFIG_MFD_STPMIC1) += stpmic1.o
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obj-$(CONFIG_MFD_SUN4I_GPADC) += sun4i-gpadc.o
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obj-$(CONFIG_MFD_STM32_LPTIMER) += stm32-lptimer.o
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@ -0,0 +1,213 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) STMicroelectronics 2018
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// Author: Pascal Paillet <p.paillet@st.com>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/stpmic1.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/pm_wakeirq.h>
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#include <linux/regmap.h>
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#include <dt-bindings/mfd/st,stpmic1.h>
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#define STPMIC1_MAIN_IRQ 0
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static const struct regmap_range stpmic1_readable_ranges[] = {
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regmap_reg_range(TURN_ON_SR, VERSION_SR),
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regmap_reg_range(SWOFF_PWRCTRL_CR, LDO6_STDBY_CR),
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regmap_reg_range(BST_SW_CR, BST_SW_CR),
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regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4),
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regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4),
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regmap_reg_range(INT_MASK_R1, INT_MASK_R4),
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regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4),
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regmap_reg_range(INT_CLEAR_MASK_R1, INT_CLEAR_MASK_R4),
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regmap_reg_range(INT_SRC_R1, INT_SRC_R1),
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};
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static const struct regmap_range stpmic1_writeable_ranges[] = {
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regmap_reg_range(SWOFF_PWRCTRL_CR, LDO6_STDBY_CR),
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regmap_reg_range(BST_SW_CR, BST_SW_CR),
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regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4),
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regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4),
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regmap_reg_range(INT_CLEAR_MASK_R1, INT_CLEAR_MASK_R4),
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};
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static const struct regmap_range stpmic1_volatile_ranges[] = {
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regmap_reg_range(TURN_ON_SR, VERSION_SR),
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regmap_reg_range(WCHDG_CR, WCHDG_CR),
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regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4),
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regmap_reg_range(INT_SRC_R1, INT_SRC_R4),
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};
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static const struct regmap_access_table stpmic1_readable_table = {
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.yes_ranges = stpmic1_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(stpmic1_readable_ranges),
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};
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static const struct regmap_access_table stpmic1_writeable_table = {
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.yes_ranges = stpmic1_writeable_ranges,
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.n_yes_ranges = ARRAY_SIZE(stpmic1_writeable_ranges),
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};
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static const struct regmap_access_table stpmic1_volatile_table = {
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.yes_ranges = stpmic1_volatile_ranges,
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.n_yes_ranges = ARRAY_SIZE(stpmic1_volatile_ranges),
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};
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const struct regmap_config stpmic1_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.cache_type = REGCACHE_RBTREE,
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.max_register = PMIC_MAX_REGISTER_ADDRESS,
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.rd_table = &stpmic1_readable_table,
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.wr_table = &stpmic1_writeable_table,
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.volatile_table = &stpmic1_volatile_table,
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};
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static const struct regmap_irq stpmic1_irqs[] = {
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REGMAP_IRQ_REG(IT_PONKEY_F, 0, 0x01),
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REGMAP_IRQ_REG(IT_PONKEY_R, 0, 0x02),
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REGMAP_IRQ_REG(IT_WAKEUP_F, 0, 0x04),
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REGMAP_IRQ_REG(IT_WAKEUP_R, 0, 0x08),
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REGMAP_IRQ_REG(IT_VBUS_OTG_F, 0, 0x10),
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REGMAP_IRQ_REG(IT_VBUS_OTG_R, 0, 0x20),
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REGMAP_IRQ_REG(IT_SWOUT_F, 0, 0x40),
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REGMAP_IRQ_REG(IT_SWOUT_R, 0, 0x80),
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REGMAP_IRQ_REG(IT_CURLIM_BUCK1, 1, 0x01),
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REGMAP_IRQ_REG(IT_CURLIM_BUCK2, 1, 0x02),
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REGMAP_IRQ_REG(IT_CURLIM_BUCK3, 1, 0x04),
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REGMAP_IRQ_REG(IT_CURLIM_BUCK4, 1, 0x08),
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REGMAP_IRQ_REG(IT_OCP_OTG, 1, 0x10),
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REGMAP_IRQ_REG(IT_OCP_SWOUT, 1, 0x20),
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REGMAP_IRQ_REG(IT_OCP_BOOST, 1, 0x40),
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REGMAP_IRQ_REG(IT_OVP_BOOST, 1, 0x80),
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REGMAP_IRQ_REG(IT_CURLIM_LDO1, 2, 0x01),
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REGMAP_IRQ_REG(IT_CURLIM_LDO2, 2, 0x02),
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REGMAP_IRQ_REG(IT_CURLIM_LDO3, 2, 0x04),
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REGMAP_IRQ_REG(IT_CURLIM_LDO4, 2, 0x08),
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REGMAP_IRQ_REG(IT_CURLIM_LDO5, 2, 0x10),
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REGMAP_IRQ_REG(IT_CURLIM_LDO6, 2, 0x20),
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REGMAP_IRQ_REG(IT_SHORT_SWOTG, 2, 0x40),
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REGMAP_IRQ_REG(IT_SHORT_SWOUT, 2, 0x80),
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REGMAP_IRQ_REG(IT_TWARN_F, 3, 0x01),
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REGMAP_IRQ_REG(IT_TWARN_R, 3, 0x02),
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REGMAP_IRQ_REG(IT_VINLOW_F, 3, 0x04),
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REGMAP_IRQ_REG(IT_VINLOW_R, 3, 0x08),
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REGMAP_IRQ_REG(IT_SWIN_F, 3, 0x40),
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REGMAP_IRQ_REG(IT_SWIN_R, 3, 0x80),
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};
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static const struct regmap_irq_chip stpmic1_regmap_irq_chip = {
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.name = "pmic_irq",
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.status_base = INT_PENDING_R1,
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.mask_base = INT_CLEAR_MASK_R1,
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.unmask_base = INT_SET_MASK_R1,
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.ack_base = INT_CLEAR_R1,
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.num_regs = STPMIC1_PMIC_NUM_IRQ_REGS,
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.irqs = stpmic1_irqs,
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.num_irqs = ARRAY_SIZE(stpmic1_irqs),
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};
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static int stpmic1_probe(struct i2c_client *i2c,
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const struct i2c_device_id *id)
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{
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struct stpmic1 *ddata;
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struct device *dev = &i2c->dev;
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int ret;
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struct device_node *np = dev->of_node;
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u32 reg;
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ddata = devm_kzalloc(dev, sizeof(struct stpmic1), GFP_KERNEL);
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if (!ddata)
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return -ENOMEM;
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i2c_set_clientdata(i2c, ddata);
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ddata->dev = dev;
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ddata->regmap = devm_regmap_init_i2c(i2c, &stpmic1_regmap_config);
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if (IS_ERR(ddata->regmap))
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return PTR_ERR(ddata->regmap);
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ddata->irq = of_irq_get(np, STPMIC1_MAIN_IRQ);
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if (ddata->irq < 0) {
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dev_err(dev, "Failed to get main IRQ: %d\n", ddata->irq);
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return ddata->irq;
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}
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ret = regmap_read(ddata->regmap, VERSION_SR, ®);
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if (ret) {
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dev_err(dev, "Unable to read PMIC version\n");
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return ret;
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}
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dev_info(dev, "PMIC Chip Version: 0x%x\n", reg);
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/* Initialize PMIC IRQ Chip & associated IRQ domains */
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ret = devm_regmap_add_irq_chip(dev, ddata->regmap, ddata->irq,
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IRQF_ONESHOT | IRQF_SHARED,
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0, &stpmic1_regmap_irq_chip,
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&ddata->irq_data);
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if (ret) {
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dev_err(dev, "IRQ Chip registration failed: %d\n", ret);
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return ret;
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}
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return devm_of_platform_populate(dev);
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}
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#ifdef CONFIG_PM_SLEEP
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static int stpmic1_suspend(struct device *dev)
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{
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struct i2c_client *i2c = to_i2c_client(dev);
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struct stpmic1 *pmic_dev = i2c_get_clientdata(i2c);
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disable_irq(pmic_dev->irq);
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return 0;
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}
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static int stpmic1_resume(struct device *dev)
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{
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struct i2c_client *i2c = to_i2c_client(dev);
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struct stpmic1 *pmic_dev = i2c_get_clientdata(i2c);
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int ret;
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ret = regcache_sync(pmic_dev->regmap);
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if (ret)
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return ret;
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enable_irq(pmic_dev->irq);
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(stpmic1_pm, stpmic1_suspend, stpmic1_resume);
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static const struct of_device_id stpmic1_of_match[] = {
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{ .compatible = "st,stpmic1", },
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{},
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};
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MODULE_DEVICE_TABLE(of, stpmic1_of_match);
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static struct i2c_driver stpmic1_driver = {
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.driver = {
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.name = "stpmic1",
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.of_match_table = of_match_ptr(stpmic1_of_match),
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.pm = &stpmic1_pm,
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},
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.probe = stpmic1_probe,
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};
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module_i2c_driver(stpmic1_driver);
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MODULE_DESCRIPTION("STPMIC1 PMIC Driver");
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MODULE_AUTHOR("Pascal Paillet <p.paillet@st.com>");
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MODULE_LICENSE("GPL v2");
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@ -0,0 +1,212 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
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* Author: Philippe Peurichard <philippe.peurichard@st.com>,
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* Pascal Paillet <p.paillet@st.com> for STMicroelectronics.
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*/
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#ifndef __LINUX_MFD_STPMIC1_H
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#define __LINUX_MFD_STPMIC1_H
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#define TURN_ON_SR 0x1
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#define TURN_OFF_SR 0x2
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#define ICC_LDO_TURN_OFF_SR 0x3
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#define ICC_BUCK_TURN_OFF_SR 0x4
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#define RREQ_STATE_SR 0x5
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#define VERSION_SR 0x6
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#define SWOFF_PWRCTRL_CR 0x10
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#define PADS_PULL_CR 0x11
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#define BUCKS_PD_CR 0x12
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#define LDO14_PD_CR 0x13
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#define LDO56_VREF_PD_CR 0x14
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#define VBUS_DET_VIN_CR 0x15
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#define PKEY_TURNOFF_CR 0x16
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#define BUCKS_MASK_RANK_CR 0x17
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#define BUCKS_MASK_RESET_CR 0x18
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#define LDOS_MASK_RANK_CR 0x19
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#define LDOS_MASK_RESET_CR 0x1A
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#define WCHDG_CR 0x1B
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#define WCHDG_TIMER_CR 0x1C
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#define BUCKS_ICCTO_CR 0x1D
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#define LDOS_ICCTO_CR 0x1E
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#define BUCK1_ACTIVE_CR 0x20
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#define BUCK2_ACTIVE_CR 0x21
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#define BUCK3_ACTIVE_CR 0x22
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#define BUCK4_ACTIVE_CR 0x23
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#define VREF_DDR_ACTIVE_CR 0x24
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#define LDO1_ACTIVE_CR 0x25
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#define LDO2_ACTIVE_CR 0x26
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#define LDO3_ACTIVE_CR 0x27
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#define LDO4_ACTIVE_CR 0x28
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#define LDO5_ACTIVE_CR 0x29
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#define LDO6_ACTIVE_CR 0x2A
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#define BUCK1_STDBY_CR 0x30
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#define BUCK2_STDBY_CR 0x31
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#define BUCK3_STDBY_CR 0x32
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#define BUCK4_STDBY_CR 0x33
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#define VREF_DDR_STDBY_CR 0x34
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#define LDO1_STDBY_CR 0x35
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#define LDO2_STDBY_CR 0x36
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#define LDO3_STDBY_CR 0x37
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#define LDO4_STDBY_CR 0x38
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#define LDO5_STDBY_CR 0x39
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#define LDO6_STDBY_CR 0x3A
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#define BST_SW_CR 0x40
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#define INT_PENDING_R1 0x50
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#define INT_PENDING_R2 0x51
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#define INT_PENDING_R3 0x52
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#define INT_PENDING_R4 0x53
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#define INT_DBG_LATCH_R1 0x60
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#define INT_DBG_LATCH_R2 0x61
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#define INT_DBG_LATCH_R3 0x62
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#define INT_DBG_LATCH_R4 0x63
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#define INT_CLEAR_R1 0x70
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#define INT_CLEAR_R2 0x71
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#define INT_CLEAR_R3 0x72
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#define INT_CLEAR_R4 0x73
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#define INT_MASK_R1 0x80
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#define INT_MASK_R2 0x81
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#define INT_MASK_R3 0x82
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#define INT_MASK_R4 0x83
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#define INT_SET_MASK_R1 0x90
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#define INT_SET_MASK_R2 0x91
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#define INT_SET_MASK_R3 0x92
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#define INT_SET_MASK_R4 0x93
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#define INT_CLEAR_MASK_R1 0xA0
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#define INT_CLEAR_MASK_R2 0xA1
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#define INT_CLEAR_MASK_R3 0xA2
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#define INT_CLEAR_MASK_R4 0xA3
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#define INT_SRC_R1 0xB0
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#define INT_SRC_R2 0xB1
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#define INT_SRC_R3 0xB2
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#define INT_SRC_R4 0xB3
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#define PMIC_MAX_REGISTER_ADDRESS INT_SRC_R4
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#define STPMIC1_PMIC_NUM_IRQ_REGS 4
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#define TURN_OFF_SR_ICC_EVENT 0x08
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#define LDO_VOLTAGE_MASK GENMASK(6, 2)
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#define BUCK_VOLTAGE_MASK GENMASK(7, 2)
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#define LDO_BUCK_VOLTAGE_SHIFT 2
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#define LDO_ENABLE_MASK BIT(0)
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#define BUCK_ENABLE_MASK BIT(0)
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#define BUCK_HPLP_ENABLE_MASK BIT(1)
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#define BUCK_HPLP_SHIFT 1
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#define STDBY_ENABLE_MASK BIT(0)
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#define BUCKS_PD_CR_REG_MASK GENMASK(7, 0)
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#define BUCK_MASK_RANK_REGISTER_MASK GENMASK(3, 0)
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#define BUCK_MASK_RESET_REGISTER_MASK GENMASK(3, 0)
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#define LDO1234_PULL_DOWN_REGISTER_MASK GENMASK(7, 0)
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#define LDO56_VREF_PD_CR_REG_MASK GENMASK(5, 0)
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#define LDO_MASK_RANK_REGISTER_MASK GENMASK(5, 0)
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#define LDO_MASK_RESET_REGISTER_MASK GENMASK(5, 0)
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#define BUCK1_PULL_DOWN_REG BUCKS_PD_CR
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#define BUCK1_PULL_DOWN_MASK BIT(0)
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#define BUCK2_PULL_DOWN_REG BUCKS_PD_CR
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#define BUCK2_PULL_DOWN_MASK BIT(2)
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#define BUCK3_PULL_DOWN_REG BUCKS_PD_CR
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#define BUCK3_PULL_DOWN_MASK BIT(4)
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#define BUCK4_PULL_DOWN_REG BUCKS_PD_CR
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#define BUCK4_PULL_DOWN_MASK BIT(6)
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#define LDO1_PULL_DOWN_REG LDO14_PD_CR
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#define LDO1_PULL_DOWN_MASK BIT(0)
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#define LDO2_PULL_DOWN_REG LDO14_PD_CR
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#define LDO2_PULL_DOWN_MASK BIT(2)
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#define LDO3_PULL_DOWN_REG LDO14_PD_CR
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#define LDO3_PULL_DOWN_MASK BIT(4)
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#define LDO4_PULL_DOWN_REG LDO14_PD_CR
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#define LDO4_PULL_DOWN_MASK BIT(6)
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#define LDO5_PULL_DOWN_REG LDO56_VREF_PD_CR
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#define LDO5_PULL_DOWN_MASK BIT(0)
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#define LDO6_PULL_DOWN_REG LDO56_VREF_PD_CR
|
||||
#define LDO6_PULL_DOWN_MASK BIT(2)
|
||||
#define VREF_DDR_PULL_DOWN_REG LDO56_VREF_PD_CR
|
||||
#define VREF_DDR_PULL_DOWN_MASK BIT(4)
|
||||
|
||||
#define BUCKS_ICCTO_CR_REG_MASK GENMASK(6, 0)
|
||||
#define LDOS_ICCTO_CR_REG_MASK GENMASK(5, 0)
|
||||
|
||||
#define LDO_BYPASS_MASK BIT(7)
|
||||
|
||||
/* Main PMIC Control Register
|
||||
* SWOFF_PWRCTRL_CR
|
||||
* Address : 0x10
|
||||
*/
|
||||
#define ICC_EVENT_ENABLED BIT(4)
|
||||
#define PWRCTRL_POLARITY_HIGH BIT(3)
|
||||
#define PWRCTRL_PIN_VALID BIT(2)
|
||||
#define RESTART_REQUEST_ENABLED BIT(1)
|
||||
#define SOFTWARE_SWITCH_OFF_ENABLED BIT(0)
|
||||
|
||||
/* Main PMIC PADS Control Register
|
||||
* PADS_PULL_CR
|
||||
* Address : 0x11
|
||||
*/
|
||||
#define WAKEUP_DETECTOR_DISABLED BIT(4)
|
||||
#define PWRCTRL_PD_ACTIVE BIT(3)
|
||||
#define PWRCTRL_PU_ACTIVE BIT(2)
|
||||
#define WAKEUP_PD_ACTIVE BIT(1)
|
||||
#define PONKEY_PU_INACTIVE BIT(0)
|
||||
|
||||
/* Main PMIC VINLOW Control Register
|
||||
* VBUS_DET_VIN_CRC DMSC
|
||||
* Address : 0x15
|
||||
*/
|
||||
#define SWIN_DETECTOR_ENABLED BIT(7)
|
||||
#define SWOUT_DETECTOR_ENABLED BIT(6)
|
||||
#define VINLOW_ENABLED BIT(0)
|
||||
#define VINLOW_CTRL_REG_MASK GENMASK(7, 0)
|
||||
|
||||
/* USB Control Register
|
||||
* Address : 0x40
|
||||
*/
|
||||
#define BOOST_OVP_DISABLED BIT(7)
|
||||
#define VBUS_OTG_DETECTION_DISABLED BIT(6)
|
||||
#define SW_OUT_DISCHARGE BIT(5)
|
||||
#define VBUS_OTG_DISCHARGE BIT(4)
|
||||
#define OCP_LIMIT_HIGH BIT(3)
|
||||
#define SWIN_SWOUT_ENABLED BIT(2)
|
||||
#define USBSW_OTG_SWITCH_ENABLED BIT(1)
|
||||
#define BOOST_ENABLED BIT(0)
|
||||
|
||||
/* PKEY_TURNOFF_CR
|
||||
* Address : 0x16
|
||||
*/
|
||||
#define PONKEY_PWR_OFF BIT(7)
|
||||
#define PONKEY_CC_FLAG_CLEAR BIT(6)
|
||||
#define PONKEY_TURNOFF_TIMER_MASK GENMASK(3, 0)
|
||||
#define PONKEY_TURNOFF_MASK GENMASK(7, 0)
|
||||
|
||||
/*
|
||||
* struct stpmic1 - stpmic1 master device for sub-drivers
|
||||
* @dev: master device of the chip (can be used to access platform data)
|
||||
* @irq: main IRQ number
|
||||
* @regmap_irq_chip_data: irq chip data
|
||||
*/
|
||||
struct stpmic1 {
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
int irq;
|
||||
struct regmap_irq_chip_data *irq_data;
|
||||
};
|
||||
|
||||
#endif /* __LINUX_MFD_STPMIC1_H */
|
||||
Loading…
Reference in New Issue