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ASoC: pcm512x: Fix clocking calculations when not using the PLL 

The rationale behind the current calculation is somewhat obscure [1]
and can yield slightly wrong dividers in certain cases, which the
machine drivers for some boards (like the HiFiBerry DAC+ Pro)
seemingly try to circumvent, by updating the rate fraction so as to
suit this calculation.

The updated calculation should correctly yield the smallest bit clock
rate that would fit the frame.

[1] http://mailman.alsa-project.org/pipermail/alsa-devel/2019-January/144219.html

Signed-off-by: Dimitris Papavasiliou <dpapavas@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
hifive-unleashed-5.1
Dimitris Papavasiliou 2019-01-26 15:23:45 +02:00 committed by Mark Brown
parent ccc8d6c7b6
commit 51b033c260
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GPG Key ID: 24D68B725D5487D0
1 changed files with 2 additions and 2 deletions
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4
sound/soc/codecs/pcm512x.c
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@ -929,8 +929,8 @@ static int pcm512x_set_dividers(struct snd_soc_dai *dai,
if (!pcm512x->pll_out) {
sck_rate = clk_get_rate(pcm512x->sclk);
bclk_div = params->rate_den * 64 / lrclk_div;
bclk_rate = DIV_ROUND_CLOSEST(sck_rate, bclk_div);
bclk_rate = params_rate(params) * lrclk_div;
bclk_div = DIV_ROUND_CLOSEST(sck_rate, bclk_rate);
mck_rate = sck_rate;
} else {