PCI: add latency tolerance reporting enable/disable support
Latency tolerance reporting allows devices to send messages to the root complex indicating their latency tolerance for snooped & unsnooped memory transactions. Add support for enabling & disabling this feature, along with a routine to set the max latencies a device should send upstream. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>hifive-unleashed-5.1
Jesse Barnes
parent
48a92a8179
commit
51c2e0a7e5
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@ -1979,6 +1979,155 @@ void pci_disable_obff(struct pci_dev *dev)
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}
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EXPORT_SYMBOL(pci_disable_obff);
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/**
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* pci_ltr_supported - check whether a device supports LTR
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* @dev: PCI device
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*
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* RETURNS:
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* True if @dev supports latency tolerance reporting, false otherwise.
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*/
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bool pci_ltr_supported(struct pci_dev *dev)
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{
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int pos;
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u32 cap;
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if (!pci_is_pcie(dev))
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return false;
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pos = pci_pcie_cap(dev);
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if (!pos)
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return false;
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pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
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return cap & PCI_EXP_DEVCAP2_LTR;
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}
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EXPORT_SYMBOL(pci_ltr_supported);
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/**
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* pci_enable_ltr - enable latency tolerance reporting
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* @dev: PCI device
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*
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* Enable LTR on @dev if possible, which means enabling it first on
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* upstream ports.
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*
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* RETURNS:
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* Zero on success, errno on failure.
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*/
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int pci_enable_ltr(struct pci_dev *dev)
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{
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int pos;
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u16 ctrl;
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int ret;
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if (!pci_ltr_supported(dev))
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return -ENOTSUPP;
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pos = pci_pcie_cap(dev);
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if (!pos)
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return -ENOTSUPP;
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/* Only primary function can enable/disable LTR */
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if (PCI_FUNC(dev->devfn) != 0)
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return -EINVAL;
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/* Enable upstream ports first */
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if (dev->bus) {
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ret = pci_enable_ltr(dev->bus->self);
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if (ret)
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return ret;
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}
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pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
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ctrl |= PCI_EXP_LTR_EN;
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pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
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return 0;
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}
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EXPORT_SYMBOL(pci_enable_ltr);
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/**
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* pci_disable_ltr - disable latency tolerance reporting
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* @dev: PCI device
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*/
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void pci_disable_ltr(struct pci_dev *dev)
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{
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int pos;
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u16 ctrl;
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if (!pci_ltr_supported(dev))
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return;
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pos = pci_pcie_cap(dev);
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if (!pos)
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return;
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/* Only primary function can enable/disable LTR */
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if (PCI_FUNC(dev->devfn) != 0)
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return;
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pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
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ctrl &= ~PCI_EXP_LTR_EN;
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pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
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}
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EXPORT_SYMBOL(pci_disable_ltr);
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static int __pci_ltr_scale(int *val)
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{
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int scale = 0;
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while (*val > 1023) {
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*val = (*val + 31) / 32;
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scale++;
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}
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return scale;
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}
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/**
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* pci_set_ltr - set LTR latency values
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* @dev: PCI device
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* @snoop_lat_ns: snoop latency in nanoseconds
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* @nosnoop_lat_ns: nosnoop latency in nanoseconds
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*
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* Figure out the scale and set the LTR values accordingly.
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*/
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int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
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{
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int pos, ret, snoop_scale, nosnoop_scale;
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u16 val;
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if (!pci_ltr_supported(dev))
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return -ENOTSUPP;
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snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
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nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
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if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
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nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
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return -EINVAL;
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if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
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(nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
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return -EINVAL;
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
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if (!pos)
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return -ENOTSUPP;
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val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
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ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
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if (ret != 4)
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return -EIO;
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val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
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ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
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if (ret != 4)
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return -EIO;
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return 0;
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}
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EXPORT_SYMBOL(pci_set_ltr);
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static int pci_acs_enable;
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/**
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@ -840,6 +840,11 @@ enum pci_obff_signal_type {
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int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
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void pci_disable_obff(struct pci_dev *dev);
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bool pci_ltr_supported(struct pci_dev *dev);
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int pci_enable_ltr(struct pci_dev *dev);
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void pci_disable_ltr(struct pci_dev *dev);
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int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
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/* For use by arch with custom probe code */
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void set_pcie_port_type(struct pci_dev *pdev);
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void set_pcie_hotplug_bridge(struct pci_dev *pdev);
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@ -508,6 +508,7 @@
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#define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */
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#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
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#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */
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#define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */
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#define PCI_EXP_OBFF_MASK 0xc0000 /* OBFF support mechanism */
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#define PCI_EXP_OBFF_MSG 0x40000 /* New message signaling */
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#define PCI_EXP_OBFF_WAKE 0x80000 /* Re-use WAKE# for OBFF */
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@ -515,6 +516,7 @@
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#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */
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#define PCI_EXP_IDO_REQ_EN 0x100 /* ID-based ordering request enable */
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#define PCI_EXP_IDO_CMP_EN 0x200 /* ID-based ordering completion enable */
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#define PCI_EXP_LTR_EN 0x400 /* Latency tolerance reporting */
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#define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */
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#define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */
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#define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
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@ -535,6 +537,7 @@
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#define PCI_EXT_CAP_ID_ARI 14
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#define PCI_EXT_CAP_ID_ATS 15
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#define PCI_EXT_CAP_ID_SRIOV 16
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#define PCI_EXT_CAP_ID_LTR 24
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/* Advanced Error Reporting */
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#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
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@ -691,6 +694,12 @@
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#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */
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#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */
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#define PCI_LTR_MAX_SNOOP_LAT 0x4
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#define PCI_LTR_MAX_NOSNOOP_LAT 0x6
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#define PCI_LTR_VALUE_MASK 0x000003ff
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#define PCI_LTR_SCALE_MASK 0x00001c00
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#define PCI_LTR_SCALE_SHIFT 10
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/* Access Control Service */
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#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
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#define PCI_ACS_SV 0x01 /* Source Validation */
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