drm/i915/dg1: Add fake PCH
DG1 has the south engine display on the same PCI device. Ideally we could use HAS_PCH_SPLIT(), but that macro is misused all across the code base to rather signify a range of gens. So add a fake one for DG1 to be used where needed. Cc: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200713182321.12390-6-lucas.demarchi@intel.com
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@ -188,6 +188,12 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
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{
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struct pci_dev *pch = NULL;
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/* DG1 has south engine display on the same PCI device */
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if (IS_DG1(dev_priv)) {
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dev_priv->pch_type = PCH_DG1;
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return;
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}
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/*
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* The reason to probe ISA bridge instead of Dev31:Fun0 is to
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* make graphics device passthrough work easy for VMM, that only
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@ -26,6 +26,9 @@ enum intel_pch {
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PCH_JSP, /* Jasper Lake PCH */
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PCH_MCC, /* Mule Creek Canyon PCH */
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PCH_TGP, /* Tiger Lake PCH */
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/* Fake PCHs, functionality handled on the same PCI dev */
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PCH_DG1 = 1024,
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};
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#define INTEL_PCH_DEVICE_ID_MASK 0xff80
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@ -56,6 +59,7 @@ enum intel_pch {
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#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
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#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
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#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
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#define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
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#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
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#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
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