drm/radeon/kms: force pinning buffer into visible VRAM
This patch properly set visible VRAM and enforce any pinned buffer to be into visible VRAM. We might later add a flag to release this constraint for some newer hw more clever than previous. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -474,6 +474,7 @@ int evergreen_mc_init(struct radeon_device *rdev)
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/* size in MB on evergreen */
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rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
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rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
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rdev->mc.visible_vram_size = rdev->mc.aper_size;
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/* FIXME remove this once we support unmappable VRAM */
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if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
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rdev->mc.mc_vram_size = rdev->mc.aper_size;
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@ -1958,9 +1958,12 @@ void r100_vram_init_sizes(struct radeon_device *rdev)
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u64 config_aper_size;
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/* work out accessible VRAM */
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rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
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rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
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rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
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rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
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/* FIXME we don't use the second aperture yet when we could use it */
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if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
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rdev->mc.visible_vram_size = rdev->mc.aper_size;
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config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
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if (rdev->flags & RADEON_IS_IGP) {
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uint32_t tom;
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@ -712,6 +712,7 @@ int r600_mc_init(struct radeon_device *rdev)
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/* Setup GPU memory space */
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rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
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rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
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rdev->mc.visible_vram_size = rdev->mc.aper_size;
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/* FIXME remove this once we support unmappable VRAM */
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if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
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rdev->mc.mc_vram_size = rdev->mc.aper_size;
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@ -178,7 +178,6 @@ int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
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{
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int r, i;
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radeon_ttm_placement_from_domain(bo, domain);
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if (bo->pin_count) {
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bo->pin_count++;
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if (gpu_addr)
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@ -186,6 +185,8 @@ int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
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return 0;
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}
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radeon_ttm_placement_from_domain(bo, domain);
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/* force to pin into visible video ram */
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bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
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for (i = 0; i < bo->placement.num_placement; i++)
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bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
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r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
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@ -462,12 +462,13 @@ void rs600_mc_init(struct radeon_device *rdev)
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{
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u64 base;
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rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
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rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
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rdev->mc.vram_is_ddr = true;
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rdev->mc.vram_width = 128;
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rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
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rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
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rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
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rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
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rdev->mc.visible_vram_size = rdev->mc.aper_size;
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rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
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base = RREG32_MC(R_000004_MC_FB_LOCATION);
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base = G_000004_MC_FB_START(base) << 16;
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@ -141,6 +141,7 @@ void rs690_mc_init(struct radeon_device *rdev)
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rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
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rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
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rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
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rdev->mc.visible_vram_size = rdev->mc.aper_size;
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base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
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base = G_000100_MC_FB_START(base) << 16;
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rs690_pm_info(rdev);
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@ -901,6 +901,7 @@ int rv770_mc_init(struct radeon_device *rdev)
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/* Setup GPU memory space */
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rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
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rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
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rdev->mc.visible_vram_size = rdev->mc.aper_size;
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/* FIXME remove this once we support unmappable VRAM */
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if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
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rdev->mc.mc_vram_size = rdev->mc.aper_size;
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