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tile PCI RC: tilepro conflict with PCI and RAM addresses 

Fix a bug in the tilepro PCI resource allocation code that could make
the bootmem allocator unhappy if 4GB is installed on mshim 0.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
hifive-unleashed-5.1
Chris Metcalf 2013-08-02 16:18:58 -04:00
parent 9bbb08faa9
commit 523c178edf
1 changed files with 5 additions and 4 deletions
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9
arch/tile/kernel/setup.c
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@ -614,11 +614,12 @@ static void __init setup_bootmem_allocator_node(int i)
/*
* Throw away any memory aliased by the PCI region.
*/
if (pci_reserve_start_pfn < end && pci_reserve_end_pfn > start)
reserve_bootmem(PFN_PHYS(pci_reserve_start_pfn),
PFN_PHYS(pci_reserve_end_pfn -
pci_reserve_start_pfn),
if (pci_reserve_start_pfn < end && pci_reserve_end_pfn > start) {
start = max(pci_reserve_start_pfn, start);
end = min(pci_reserve_end_pfn, end);
reserve_bootmem(PFN_PHYS(start), PFN_PHYS(end - start),
BOOTMEM_EXCLUSIVE);
}
#endif
}