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Merge branch 'imx/cleanup' into imx/devel 

This helps resolve the conflicts between the imx cleanups and the
new code that has gone into the imx tree.
Conflict resolution was originally done by Sascha Hauer.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
hifive-unleashed-5.1
Arnd Bergmann 2011-10-07 21:57:31 +02:00
parent 4c4cbce68f 05d900c9d8
commit 526b264163
60 changed files with 2556 additions and 4720 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
arch/arm/mach-imx/Makefile
View File

@ -1,16 +1,15 @@
obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
obj-$(CONFIG_SOC_IMX1) += clock-imx1.o mm-imx1.o
obj-$(CONFIG_SOC_IMX21) += clock-imx21.o mm-imx21.o
obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o
obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
obj-$(CONFIG_SOC_IMX31) += mm-imx31.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
obj-$(CONFIG_SOC_IMX35) += mm-imx35.o cpu-imx35.o clock-imx35.o ehci-imx35.o
obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o
# Support for CMOS sensor interface
obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o

56
arch/arm/mach-imx/cache-l2x0.c
View File

@ -1,56 +0,0 @@
/*
* Copyright (C) 2009-2010 Pengutronix
* Sascha Hauer <s.hauer@pengutronix.de>
* Juergen Beisert <j.beisert@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/err.h>
#include <linux/kernel.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/hardware.h>
static int mxc_init_l2x0(void)
{
void __iomem *l2x0_base;
void __iomem *clkctl_base;
if (!cpu_is_mx31() && !cpu_is_mx35())
return 0;
/*
* First of all, we must repair broken chip settings. There are some
* i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
* misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
* Workaraound is to setup the correct register setting prior enabling the
* L2 cache. This should not hurt already working CPUs, as they are using the
* same value.
*/
#define L2_MEM_VAL 0x10
clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
if (clkctl_base != NULL) {
writel(0x00000515, clkctl_base + L2_MEM_VAL);
iounmap(clkctl_base);
} else {
pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
}
l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
if (IS_ERR(l2x0_base)) {
printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
PTR_ERR(l2x0_base));
return 0;
}
l2x0_init(l2x0_base, 0x00030024, 0x00000000);
return 0;
}
early_initcall(mxc_init_l2x0);

18
arch/arm/mach-imx/mach-armadillo5x0.c
View File

@ -314,25 +314,19 @@ static struct mtd_partition armadillo5x0_nor_flash_partitions[] = {
},
};
static struct physmap_flash_data armadillo5x0_nor_flash_pdata = {
static const struct physmap_flash_data
armadillo5x0_nor_flash_pdata __initconst = {
.width = 2,
.parts = armadillo5x0_nor_flash_partitions,
.nr_parts = ARRAY_SIZE(armadillo5x0_nor_flash_partitions),
};
static struct resource armadillo5x0_nor_flash_resource = {
static const struct resource armadillo5x0_nor_flash_resource __initconst = {
.flags = IORESOURCE_MEM,
.start = MX31_CS0_BASE_ADDR,
.end = MX31_CS0_BASE_ADDR + SZ_64M - 1,
};
static struct platform_device armadillo5x0_nor_flash = {
.name = "physmap-flash",
.id = -1,
.num_resources = 1,
.resource = &armadillo5x0_nor_flash_resource,
};
/*
* FB support
*/
@ -514,8 +508,10 @@ static void __init armadillo5x0_init(void)
imx31_add_mx3_sdc_fb(&mx3fb_pdata);
/* Register NOR Flash */
mxc_register_device(&armadillo5x0_nor_flash,
&armadillo5x0_nor_flash_pdata);
platform_device_register_resndata(NULL, "physmap-flash", -1,
&armadillo5x0_nor_flash_resource, 1,
&armadillo5x0_nor_flash_pdata,
sizeof(armadillo5x0_nor_flash_pdata));
/* Register NAND Flash */
imx31_add_mxc_nand(&armadillo5x0_nand_board_info);

2
arch/arm/mach-imx/mach-cpuimx35.c
View File

@ -66,7 +66,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
I2C_BOARD_INFO("tsc2007", 0x48),
.type = "tsc2007",
.platform_data = &tsc2007_info,
.irq = gpio_to_irq(TSC2007_IRQGPIO),
.irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
},
};

15
arch/arm/mach-imx/mach-mx1ads.c
View File

@ -68,23 +68,16 @@ static const struct imxuart_platform_data uart1_pdata __initconst = {
* Physmap flash
*/
static struct physmap_flash_data mx1ads_flash_data = {
static const struct physmap_flash_data mx1ads_flash_data __initconst = {
.width = 4, /* bankwidth in bytes */
};
static struct resource flash_resource = {
static const struct resource flash_resource __initconst = {
.start = MX1_CS0_PHYS,
.end = MX1_CS0_PHYS + SZ_32M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device flash_device = {
.name = "physmap-flash",
.id = 0,
.resource = &flash_resource,
.num_resources = 1,
};
/*
* I2C
*/
@ -125,7 +118,9 @@ static void __init mx1ads_init(void)
imx1_add_imx_uart1(&uart1_pdata);
/* Physmap flash */
mxc_register_device(&flash_device, &mx1ads_flash_data);
platform_device_register_resndata(NULL, "physmap-flash", 0,
&flash_resource, 1,
&mx1ads_flash_data, sizeof(mx1ads_flash_data));
/* I2C */
i2c_register_board_info(0, mx1ads_i2c_devices,

2
arch/arm/mach-imx/mach-mx27_3ds.c
View File

@ -359,7 +359,7 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
.bus_num = 1,
.chip_select = 0, /* SS0 */
.platform_data = &mc13783_pdata,
.irq = gpio_to_irq(PMIC_INT),
.irq = IMX_GPIO_TO_IRQ(PMIC_INT),
.mode = SPI_CS_HIGH,
}, {
.modalias = "l4f00242t03",

2
arch/arm/mach-imx/mach-vpr200.c
View File

@ -162,7 +162,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = {
}, {
I2C_BOARD_INFO("mc13892", 0x08),
.platform_data = &vpr200_pmic,
.irq = gpio_to_irq(GPIO_PMIC_INT),
.irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
}
};

256
arch/arm/mach-imx/mm-imx3.c 100644
View File

@ -0,0 +1,256 @@
/*
* Copyright (C) 1999,2000 Arm Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* - add MX31 specific definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/err.h>
#include <asm/pgtable.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/devices-common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>
#include <mach/irqs.h>
static void imx3_idle(void)
{
unsigned long reg = 0;
__asm__ __volatile__(
/* disable I and D cache */
"mrc p15, 0, %0, c1, c0, 0\n"
"bic %0, %0, #0x00001000\n"
"bic %0, %0, #0x00000004\n"
"mcr p15, 0, %0, c1, c0, 0\n"
/* invalidate I cache */
"mov %0, #0\n"
"mcr p15, 0, %0, c7, c5, 0\n"
/* clear and invalidate D cache */
"mov %0, #0\n"
"mcr p15, 0, %0, c7, c14, 0\n"
/* WFI */
"mov %0, #0\n"
"mcr p15, 0, %0, c7, c0, 4\n"
"nop\n" "nop\n" "nop\n" "nop\n"
"nop\n" "nop\n" "nop\n"
/* enable I and D cache */
"mrc p15, 0, %0, c1, c0, 0\n"
"orr %0, %0, #0x00001000\n"
"orr %0, %0, #0x00000004\n"
"mcr p15, 0, %0, c1, c0, 0\n"
: "=r" (reg));
}
static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
unsigned int mtype)
{
if (mtype == MT_DEVICE) {
/*
* Access all peripherals below 0x80000000 as nonshared device
* on mx3, but leave l2cc alone. Otherwise cache corruptions
* can occur.
*/
if (phys_addr < 0x80000000 &&
!addr_in_module(phys_addr, MX3x_L2CC))
mtype = MT_DEVICE_NONSHARED;
}
return __arm_ioremap(phys_addr, size, mtype);
}
void imx3_init_l2x0(void)
{
void __iomem *l2x0_base;
void __iomem *clkctl_base;
/*
* First of all, we must repair broken chip settings. There are some
* i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
* misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
* Workaraound is to setup the correct register setting prior enabling the
* L2 cache. This should not hurt already working CPUs, as they are using the
* same value.
*/
#define L2_MEM_VAL 0x10
clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
if (clkctl_base != NULL) {
writel(0x00000515, clkctl_base + L2_MEM_VAL);
iounmap(clkctl_base);
} else {
pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
}
l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
if (IS_ERR(l2x0_base)) {
printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
PTR_ERR(l2x0_base));
return;
}
l2x0_init(l2x0_base, 0x00030024, 0x00000000);
}
static struct map_desc mx31_io_desc[] __initdata = {
imx_map_entry(MX31, X_MEMC, MT_DEVICE),
imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
};
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
* for the IO modules.
*/
void __init mx31_map_io(void)
{
iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
}
static struct map_desc mx35_io_desc[] __initdata = {
imx_map_entry(MX35, X_MEMC, MT_DEVICE),
imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
};
void __init mx35_map_io(void)
{
iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
}
void __init imx31_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX31);
mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
imx_idle = imx3_idle;
imx_ioremap = imx3_ioremap;
}
void __init imx35_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX35);
mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
imx_idle = imx3_idle;
imx_ioremap = imx3_ioremap;
}
void __init mx31_init_irq(void)
{
mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
}
void __init mx35_init_irq(void)
{
mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
}
static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
.per_2_per_addr = 1677,
};
static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
.ap_2_ap_addr = 423,
.ap_2_bp_addr = 829,
.bp_2_ap_addr = 1029,
};
static struct sdma_platform_data imx31_sdma_pdata __initdata = {
.fw_name = "sdma-imx31-to2.bin",
.script_addrs = &imx31_to2_sdma_script,
};
void __init imx31_soc_init(void)
{
int to_version = mx31_revision() >> 4;
imx3_init_l2x0();
mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
if (to_version == 1) {
strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
strlen(imx31_sdma_pdata.fw_name));
imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
}
imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
}
static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
.ap_2_ap_addr = 642,
.uart_2_mcu_addr = 817,
.mcu_2_app_addr = 747,
.uartsh_2_mcu_addr = 1183,
.per_2_shp_addr = 1033,
.mcu_2_shp_addr = 961,
.ata_2_mcu_addr = 1333,
.mcu_2_ata_addr = 1252,
.app_2_mcu_addr = 683,
.shp_2_per_addr = 1111,
.shp_2_mcu_addr = 892,
};
static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
.ap_2_ap_addr = 729,
.uart_2_mcu_addr = 904,
.per_2_app_addr = 1597,
.mcu_2_app_addr = 834,
.uartsh_2_mcu_addr = 1270,
.per_2_shp_addr = 1120,
.mcu_2_shp_addr = 1048,
.ata_2_mcu_addr = 1429,
.mcu_2_ata_addr = 1339,
.app_2_per_addr = 1531,
.app_2_mcu_addr = 770,
.shp_2_per_addr = 1198,
.shp_2_mcu_addr = 979,
};
static struct sdma_platform_data imx35_sdma_pdata __initdata = {
.fw_name = "sdma-imx35-to2.bin",
.script_addrs = &imx35_to2_sdma_script,
};
void __init imx35_soc_init(void)
{
int to_version = mx35_revision() >> 4;
imx3_init_l2x0();
/* i.mx35 has the i.mx31 type gpio */
mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
if (to_version == 1) {
strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
strlen(imx35_sdma_pdata.fw_name));
imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
}
imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
}

91
arch/arm/mach-imx/mm-imx31.c
View File

@ -1,91 +0,0 @@
/*
* Copyright (C) 1999,2000 Arm Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* - add MX31 specific definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/err.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/devices-common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>
#include <mach/irqs.h>
static struct map_desc mx31_io_desc[] __initdata = {
imx_map_entry(MX31, X_MEMC, MT_DEVICE),
imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
};
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
* for the IO modules.
*/
void __init mx31_map_io(void)
{
iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
}
void __init imx31_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX31);
mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
}
void __init mx31_init_irq(void)
{
mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
}
static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
.per_2_per_addr = 1677,
};
static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
.ap_2_ap_addr = 423,
.ap_2_bp_addr = 829,
.bp_2_ap_addr = 1029,
};
static struct sdma_platform_data imx31_sdma_pdata __initdata = {
.fw_name = "sdma-imx31-to2.bin",
.script_addrs = &imx31_to2_sdma_script,
};
void __init imx31_soc_init(void)
{
int to_version = mx31_revision() >> 4;
mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
if (to_version == 1) {
strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
strlen(imx31_sdma_pdata.fw_name));
imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
}
imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
}

109
arch/arm/mach-imx/mm-imx35.c
View File

@ -1,109 +0,0 @@
/*
* Copyright (C) 1999,2000 Arm Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
* Copyright (C) 2002 Shane Nay (shane@minirl.com)
* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* - add MX31 specific definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/err.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/common.h>
#include <mach/devices-common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>
#include <mach/irqs.h>
static struct map_desc mx35_io_desc[] __initdata = {
imx_map_entry(MX35, X_MEMC, MT_DEVICE),
imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
};
void __init mx35_map_io(void)
{
iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
}
void __init imx35_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX35);
mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
}
void __init mx35_init_irq(void)
{
mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
}
static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
.ap_2_ap_addr = 642,
.uart_2_mcu_addr = 817,
.mcu_2_app_addr = 747,
.uartsh_2_mcu_addr = 1183,
.per_2_shp_addr = 1033,
.mcu_2_shp_addr = 961,
.ata_2_mcu_addr = 1333,
.mcu_2_ata_addr = 1252,
.app_2_mcu_addr = 683,
.shp_2_per_addr = 1111,
.shp_2_mcu_addr = 892,
};
static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
.ap_2_ap_addr = 729,
.uart_2_mcu_addr = 904,
.per_2_app_addr = 1597,
.mcu_2_app_addr = 834,
.uartsh_2_mcu_addr = 1270,
.per_2_shp_addr = 1120,
.mcu_2_shp_addr = 1048,
.ata_2_mcu_addr = 1429,
.mcu_2_ata_addr = 1339,
.app_2_per_addr = 1531,
.app_2_mcu_addr = 770,
.shp_2_per_addr = 1198,
.shp_2_mcu_addr = 979,
};
static struct sdma_platform_data imx35_sdma_pdata __initdata = {
.fw_name = "sdma-imx35-to2.bin",
.script_addrs = &imx35_to2_sdma_script,
};
void __init imx35_soc_init(void)
{
int to_version = mx35_revision() >> 4;
/* i.mx35 has the i.mx31 type gpio */
mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
if (to_version == 1) {
strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
strlen(imx35_sdma_pdata.fw_name));
imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
}
imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
}

2
arch/arm/mach-imx/pm-imx27.c
View File

@ -11,7 +11,7 @@
#include <linux/suspend.h>
#include <linux/io.h>
#include <mach/system.h>
#include <mach/mx27.h>
#include <mach/hardware.h>
static int mx27_suspend_enter(suspend_state_t state)
{

10
arch/arm/mach-mx5/Kconfig
View File

@ -50,7 +50,6 @@ config MACH_MX50_RDP
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
select IMX_HAVE_PLATFORM_FEC
help
Include support for MX50 reference design platform (RDP) board. This
includes specific configurations for the board and its peripherals.
@ -60,9 +59,11 @@ comment "i.MX51 machines:"
config MACH_MX51_BABBAGE
bool "Support MX51 BABBAGE platforms"
select SOC_IMX51
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
help
@ -86,8 +87,10 @@ config MACH_MX51_3DS
config MACH_EUKREA_CPUIMX51
bool "Support Eukrea CPUIMX51 module"
select SOC_IMX51
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
help
@ -114,10 +117,12 @@ endchoice
config MACH_EUKREA_CPUIMX51SD
bool "Support Eukrea CPUIMX51SD module"
select SOC_IMX51
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_SPI_IMX
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX
help
Include support for Eukrea CPUIMX51SD platform. This includes
specific configurations for the module and its peripherals.
@ -142,6 +147,7 @@ config MX51_EFIKA_COMMON
bool
select SOC_IMX51
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_PATA_IMX
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX

3
arch/arm/mach-mx5/Makefile
View File

@ -3,8 +3,7 @@
#
# Object file lists.
obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o system.o
obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
obj-y := cpu.o mm.o clock-mx51-mx53.o ehci.o system.o
obj-$(CONFIG_PM) += pm-imx5.o
obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o

27
arch/arm/mach-mx5/board-cpuimx51.c
View File

@ -22,21 +22,18 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <mach/eukrea-baseboards.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "devices-imx51.h"
#include "devices.h"
#define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27)
#define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28)
@ -57,7 +54,7 @@
static struct plat_serial8250_port serial_platform_data[] = {
{
.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
.irq = gpio_to_irq(CPUIMX51_QUARTA_GPIO),
.irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTA_GPIO),
.irqflags = IRQF_TRIGGER_HIGH,
.uartclk = CPUIMX51_QUART_XTAL,
.regshift = CPUIMX51_QUART_REGSHIFT,
@ -65,7 +62,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
.irq = gpio_to_irq(CPUIMX51_QUARTB_GPIO),
.irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTB_GPIO),
.irqflags = IRQF_TRIGGER_HIGH,
.uartclk = CPUIMX51_QUART_XTAL,
.regshift = CPUIMX51_QUART_REGSHIFT,
@ -73,7 +70,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
.irq = gpio_to_irq(CPUIMX51_QUARTC_GPIO),
.irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTC_GPIO),
.irqflags = IRQF_TRIGGER_HIGH,
.uartclk = CPUIMX51_QUART_XTAL,
.regshift = CPUIMX51_QUART_REGSHIFT,
@ -81,7 +78,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
.irq = gpio_to_irq(CPUIMX51_QUARTD_GPIO),
.irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTD_GPIO),
.irqflags = IRQF_TRIGGER_HIGH,
.uartclk = CPUIMX51_QUART_XTAL,
.regshift = CPUIMX51_QUART_REGSHIFT,
@ -167,7 +164,7 @@ static int initialize_otg_port(struct platform_device *pdev)
void __iomem *usb_base;
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
if (!usb_base)
return -ENOMEM;
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@ -190,7 +187,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
void __iomem *usb_base;
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
if (!usb_base)
return -ENOMEM;
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@ -206,17 +203,17 @@ static int initialize_usbh1_port(struct platform_device *pdev)
MXC_EHCI_ITC_NO_THRESHOLD);
}
static struct mxc_usbh_platform_data dr_utmi_config = {
static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
.init = initialize_otg_port,
.portsc = MXC_EHCI_UTMI_16BIT,
};
static struct fsl_usb2_platform_data usb_pdata = {
static const struct fsl_usb2_platform_data usb_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
};
static struct mxc_usbh_platform_data usbh1_config = {
static const struct mxc_usbh_platform_data usbh1_config __initconst = {
.init = initialize_usbh1_port,
.portsc = MXC_EHCI_MODE_ULPI,
};
@ -270,12 +267,12 @@ static void __init eukrea_cpuimx51_init(void)
ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
if (otg_mode_host)
mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
imx51_add_mxc_ehci_otg(&dr_utmi_config);
else {
initialize_otg_port(NULL);
mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
imx51_add_fsl_usb2_udc(&usb_pdata);
}
mxc_register_device(&mxc_usbh1_device, &usbh1_config);
imx51_add_mxc_ehci_hs(1, &usbh1_config);
#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
eukrea_mbimx51_baseboard_init();

25
arch/arm/mach-mx5/board-cpuimx51sd.c
View File

@ -22,7 +22,6 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/i2c-gpio.h>
#include <linux/spi/spi.h>
#include <linux/can/platform/mcp251x.h>
@ -32,14 +31,12 @@
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "devices-imx51.h"
#include "devices.h"
#include "cpu_op-mx51.h"
#define USBH1_RST IMX_GPIO_NR(2, 28)
@ -108,7 +105,7 @@ static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
/* Touchscreen */
/* IRQ */
_MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
PAD_CTL_PKE | PAD_CTL_SRE_FAST |
PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
};
@ -129,7 +126,7 @@ static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
I2C_BOARD_INFO("tsc2007", 0x49),
.type = "tsc2007",
.platform_data = &tsc2007_info,
.irq = gpio_to_irq(TSC2007_IRQGPIO),
.irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
},
};
@ -149,7 +146,7 @@ static int initialize_otg_port(struct platform_device *pdev)
void __iomem *usb_base;
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
if (!usb_base)
return -ENOMEM;
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@ -172,7 +169,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
void __iomem *usb_base;
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
if (!usb_base)
return -ENOMEM;
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@ -189,17 +186,17 @@ static int initialize_usbh1_port(struct platform_device *pdev)
MXC_EHCI_ITC_NO_THRESHOLD);
}
static struct mxc_usbh_platform_data dr_utmi_config = {
static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
.init = initialize_otg_port,
.portsc = MXC_EHCI_UTMI_16BIT,
};
static struct fsl_usb2_platform_data usb_pdata = {
static const struct fsl_usb2_platform_data usb_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
};
static struct mxc_usbh_platform_data usbh1_config = {
static const struct mxc_usbh_platform_data usbh1_config __initconst = {
.init = initialize_usbh1_port,
.portsc = MXC_EHCI_MODE_ULPI,
};
@ -245,7 +242,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = {
.mode = SPI_MODE_0,
.chip_select = 0,
.platform_data = &mcp251x_info,
.irq = gpio_to_irq(CAN_IRQGPIO)
.irq = IMX_GPIO_TO_IRQ(CAN_IRQGPIO)
},
};
@ -303,17 +300,17 @@ static void __init eukrea_cpuimx51sd_init(void)
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
if (otg_mode_host)
mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
imx51_add_mxc_ehci_otg(&dr_utmi_config);
else {
initialize_otg_port(NULL);
mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
imx51_add_fsl_usb2_udc(&usb_pdata);
}
gpio_request(USBH1_RST, "usb_rst");
gpio_direction_output(USBH1_RST, 0);
msleep(20);
gpio_set_value(USBH1_RST, 1);
mxc_register_device(&mxc_usbh1_device, &usbh1_config);
imx51_add_mxc_ehci_hs(1, &usbh1_config);
#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
eukrea_mbimxsd51_baseboard_init();

1
arch/arm/mach-mx5/board-mx51_3ds.c
View File

@ -25,7 +25,6 @@
#include <mach/3ds_debugboard.h>
#include "devices-imx51.h"
#include "devices.h"
#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 6))
#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28)

26
arch/arm/mach-mx5/board-mx51_babbage.c
View File

@ -24,14 +24,12 @@
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "devices-imx51.h"
#include "devices.h"
#include "cpu_op-mx51.h"
#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
@ -176,7 +174,7 @@ static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
.bitrate = 100000,
};
static struct imxi2c_platform_data babbage_hsi2c_data = {
static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = {
.bitrate = 400000,
};
@ -249,7 +247,7 @@ static int initialize_otg_port(struct platform_device *pdev)
void __iomem *usb_base;
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
if (!usb_base)
return -ENOMEM;
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@ -272,7 +270,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
void __iomem *usb_base;
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
if (!usb_base)
return -ENOMEM;
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@ -288,17 +286,17 @@ static int initialize_usbh1_port(struct platform_device *pdev)
MXC_EHCI_ITC_NO_THRESHOLD);
}
static struct mxc_usbh_platform_data dr_utmi_config = {
static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
.init = initialize_otg_port,
.portsc = MXC_EHCI_UTMI_16BIT,
};
static struct fsl_usb2_platform_data usb_pdata = {
static const struct fsl_usb2_platform_data usb_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
};
static struct mxc_usbh_platform_data usbh1_config = {
static const struct mxc_usbh_platform_data usbh1_config __initconst = {
.init = initialize_usbh1_port,
.portsc = MXC_EHCI_MODE_ULPI,
};
@ -357,8 +355,8 @@ static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
static void __init mx51_babbage_init(void)
{
iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21,
PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
imx51_soc_init();
@ -381,17 +379,17 @@ static void __init mx51_babbage_init(void)
imx51_add_imx_i2c(0, &babbage_i2c_data);
imx51_add_imx_i2c(1, &babbage_i2c_data);
mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
imx51_add_hsi2c(&babbage_hsi2c_data);
if (otg_mode_host)
mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
imx51_add_mxc_ehci_otg(&dr_utmi_config);
else {
initialize_otg_port(NULL);
mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
imx51_add_fsl_usb2_udc(&usb_pdata);
}
gpio_usbh1_active();
mxc_register_device(&mxc_usbh1_device, &usbh1_config);
imx51_add_mxc_ehci_hs(1, &usbh1_config);
/* setback USBH1_STP to be function */
mxc_iomux_v3_setup_pad(usbh1stp);
babbage_usbhub_reset();

2
arch/arm/mach-mx5/board-mx51_efikamx.c
View File

@ -32,14 +32,12 @@
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "devices-imx51.h"
#include "devices.h"
#include "efika.h"
#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16)

6
arch/arm/mach-mx5/board-mx51_efikasb.c
View File

@ -35,14 +35,12 @@
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "devices-imx51.h"
#include "devices.h"
#include "efika.h"
#define EFIKASB_USBH2_STP IMX_GPIO_NR(2, 20)
@ -122,7 +120,7 @@ static int initialize_usbh2_port(struct platform_device *pdev)
return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
}
static struct mxc_usbh_platform_data usbh2_config = {
static struct mxc_usbh_platform_data usbh2_config __initdata = {
.init = initialize_usbh2_port,
.portsc = MXC_EHCI_MODE_ULPI,
};
@ -132,7 +130,7 @@ static void __init mx51_efikasb_usb(void)
usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
if (usbh2_config.otg)
mxc_register_device(&mxc_usbh2_device, &usbh2_config);
imx51_add_mxc_ehci_hs(2, &usbh2_config);
}
static const struct gpio_led mx51_efikasb_leds[] __initconst = {

4
arch/arm/mach-mx5/board-mx53_ard.c
View File

@ -134,8 +134,8 @@ static struct resource ard_smsc911x_resources[] = {
.flags = IORESOURCE_MEM,
},
{
.start = gpio_to_irq(ARD_ETHERNET_INT_B),
.end = gpio_to_irq(ARD_ETHERNET_INT_B),
.start = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
.end = IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
.flags = IORESOURCE_IRQ,
},
};

2
arch/arm/mach-mx5/clock-mx51-mx53.c
View File

@ -1573,7 +1573,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
/* System timer */
mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
MX51_MXC_INT_GPT);
MX51_INT_GPT);
return 0;
}

13
arch/arm/mach-mx5/devices-imx51.h
View File

@ -13,9 +13,15 @@ extern const struct imx_fec_data imx51_fec_data;
#define imx51_add_fec(pdata) \
imx_add_fec(&imx51_fec_data, pdata)
extern const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data;
#define imx51_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx51_fsl_usb2_udc_data, pdata)
extern const struct imx_imx_i2c_data imx51_imx_i2c_data[];
#define imx51_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
#define imx51_add_hsi2c(pdata) \
imx51_add_imx_i2c(2, pdata)
extern const struct imx_imx_ssi_data imx51_imx_ssi_data[];
#define imx51_add_imx_ssi(id, pdata) \
@ -25,6 +31,13 @@ extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[];
#define imx51_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
extern const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data;
#define imx51_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx51_mxc_ehci_otg_data, pdata)
extern const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[];
#define imx51_add_mxc_ehci_hs(id, pdata) \
imx_add_mxc_ehci(&imx51_mxc_ehci_hs_data[id - 1], pdata)
extern const struct imx_mxc_nand_data imx51_mxc_nand_data;
#define imx51_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)

120
arch/arm/mach-mx5/devices.c
View File

@ -1,120 +0,0 @@
/*
* Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com>
* Copyright (C) 2010 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <mach/hardware.h>
#include <mach/imx-uart.h>
#include <mach/irqs.h>
static struct resource mxc_hsi2c_resources[] = {
{
.start = MX51_HSI2C_DMA_BASE_ADDR,
.end = MX51_HSI2C_DMA_BASE_ADDR + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MX51_MXC_INT_HS_I2C,
.end = MX51_MXC_INT_HS_I2C,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_hsi2c_device = {
.name = "imx-i2c",
.id = 2,
.num_resources = ARRAY_SIZE(mxc_hsi2c_resources),
.resource = mxc_hsi2c_resources
};
static u64 usb_dma_mask = DMA_BIT_MASK(32);
static struct resource usbotg_resources[] = {
{
.start = MX51_OTG_BASE_ADDR,
.end = MX51_OTG_BASE_ADDR + 0x1ff,
.flags = IORESOURCE_MEM,
},
{
.start = MX51_MXC_INT_USB_OTG,
.flags = IORESOURCE_IRQ,
},
};
/* OTG gadget device */
struct platform_device mxc_usbdr_udc_device = {
.name = "fsl-usb2-udc",
.id = -1,
.num_resources = ARRAY_SIZE(usbotg_resources),
.resource = usbotg_resources,
.dev = {
.dma_mask = &usb_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
struct platform_device mxc_usbdr_host_device = {
.name = "mxc-ehci",
.id = 0,
.num_resources = ARRAY_SIZE(usbotg_resources),
.resource = usbotg_resources,
.dev = {
.dma_mask = &usb_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource usbh1_resources[] = {
{
.start = MX51_OTG_BASE_ADDR + 0x200,
.end = MX51_OTG_BASE_ADDR + 0x200 + 0x1ff,
.flags = IORESOURCE_MEM,
},
{
.start = MX51_MXC_INT_USB_H1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh1_device = {
.name = "mxc-ehci",
.id = 1,
.num_resources = ARRAY_SIZE(usbh1_resources),
.resource = usbh1_resources,
.dev = {
.dma_mask = &usb_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct resource usbh2_resources[] = {
{
.start = MX51_OTG_BASE_ADDR + 0x400,
.end = MX51_OTG_BASE_ADDR + 0x400 + 0x1ff,
.flags = IORESOURCE_MEM,
},
{
.start = MX51_MXC_INT_USB_H2,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_usbh2_device = {
.name = "mxc-ehci",
.id = 2,
.num_resources = ARRAY_SIZE(usbh2_resources),
.resource = usbh2_resources,
.dev = {
.dma_mask = &usb_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};

5
arch/arm/mach-mx5/devices.h
View File

@ -1,5 +0,0 @@
extern struct platform_device mxc_usbdr_host_device;
extern struct platform_device mxc_usbh1_device;
extern struct platform_device mxc_usbh2_device;
extern struct platform_device mxc_usbdr_udc_device;
extern struct platform_device mxc_hsi2c_device;

2
arch/arm/mach-mx5/ehci.c
View File

@ -52,7 +52,7 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
void __iomem *usbother_base;
int ret = 0;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
if (!usb_base) {
printk(KERN_ERR "%s(): ioremap failed\n", __func__);
return -ENOMEM;

3
arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
View File

@ -28,7 +28,6 @@
#include <asm/mach/arch.h>
#include "devices-imx51.h"
#include "devices.h"
#define MBIMX51_TSC2007_GPIO IMX_GPIO_NR(3, 30)
#define MBIMX51_LED0 IMX_GPIO_NR(3, 5)
@ -160,7 +159,7 @@ struct tsc2007_platform_data tsc2007_data = {
static struct i2c_board_info mbimx51_i2c_devices[] = {
{
I2C_BOARD_INFO("tsc2007", 0x49),
.irq = gpio_to_irq(MBIMX51_TSC2007_GPIO),
.irq = IMX_GPIO_TO_IRQ(MBIMX51_TSC2007_GPIO),
.platform_data = &tsc2007_data,
}, {
I2C_BOARD_INFO("tlv320aic23", 0x1a),

6
arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
View File

@ -24,7 +24,6 @@
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
#include <linux/input.h>
@ -41,13 +40,12 @@
#include <mach/audmux.h>
#include "devices-imx51.h"
#include "devices.h"
static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
/* LED */
MX51_PAD_NANDF_D10__GPIO3_30,
/* SWITCH */
_MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, PAD_CTL_PUS_22K_UP |
PAD_CTL_PKE | PAD_CTL_SRE_FAST |
PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
/* UART2 */
@ -66,7 +64,7 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
MX51_PAD_SD1_DATA2__SD1_DATA2,
MX51_PAD_SD1_DATA3__SD1_DATA3,
/* SD1 CD */
_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_PUS_22K_UP |
PAD_CTL_PKE | PAD_CTL_SRE_FAST |
PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
};

72
arch/arm/mach-mx5/mm-mx50.c
View File

@ -1,72 +0,0 @@
/*
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Create static mapping between physical to virtual memory.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-v3.h>
#include <mach/irqs.h>
/*
* Define the MX50 memory map.
*/
static struct map_desc mx50_io_desc[] __initdata = {
imx_map_entry(MX50, TZIC, MT_DEVICE),
imx_map_entry(MX50, SPBA0, MT_DEVICE),
imx_map_entry(MX50, AIPS1, MT_DEVICE),
imx_map_entry(MX50, AIPS2, MT_DEVICE),
};
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
* for the IO modules.
*/
void __init mx50_map_io(void)
{
iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
}
void __init imx50_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX50);
mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
}
void __init mx50_init_irq(void)
{
tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
}
void __init imx50_soc_init(void)
{
/* i.mx50 has the i.mx31 type gpio */
mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
}

90
arch/arm/mach-mx5/mm.c
View File

@ -21,12 +21,27 @@
#include <mach/devices-common.h>
#include <mach/iomux-v3.h>
static void imx5_idle(void)
{
mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
}
/*
* Define the MX50 memory map.
*/
static struct map_desc mx50_io_desc[] __initdata = {
imx_map_entry(MX50, TZIC, MT_DEVICE),
imx_map_entry(MX50, SPBA0, MT_DEVICE),
imx_map_entry(MX50, AIPS1, MT_DEVICE),
imx_map_entry(MX50, AIPS2, MT_DEVICE),
};
/*
* Define the MX51 memory map.
*/
static struct map_desc mx51_io_desc[] __initdata = {
imx_map_entry(MX51, TZIC, MT_DEVICE),
imx_map_entry(MX51, IRAM, MT_DEVICE),
imx_map_entry(MX51, DEBUG, MT_DEVICE),
imx_map_entry(MX51, AIPS1, MT_DEVICE),
imx_map_entry(MX51, SPBA0, MT_DEVICE),
imx_map_entry(MX51, AIPS2, MT_DEVICE),
@ -36,6 +51,7 @@ static struct map_desc mx51_io_desc[] __initdata = {
* Define the MX53 memory map.
*/
static struct map_desc mx53_io_desc[] __initdata = {
imx_map_entry(MX53, TZIC, MT_DEVICE),
imx_map_entry(MX53, AIPS1, MT_DEVICE),
imx_map_entry(MX53, SPBA0, MT_DEVICE),
imx_map_entry(MX53, AIPS2, MT_DEVICE),
@ -46,21 +62,34 @@ static struct map_desc mx53_io_desc[] __initdata = {
* system startup to create static physical to virtual memory mappings
* for the IO modules.
*/
void __init mx50_map_io(void)
{
iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
}
void __init mx51_map_io(void)
{
iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
}
void __init mx53_map_io(void)
{
iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
}
void __init imx50_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX50);
mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
}
void __init imx51_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX51);
mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
}
void __init mx53_map_io(void)
{
iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
imx_idle = imx5_idle;
}
void __init imx53_init_early(void)
@ -70,35 +99,19 @@ void __init imx53_init_early(void)
mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
}
void __init mx50_init_irq(void)
{
tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
}
void __init mx51_init_irq(void)
{
unsigned long tzic_addr;
void __iomem *tzic_virt;
if (mx51_revision() < IMX_CHIP_REVISION_2_0)
tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
else
tzic_addr = MX51_TZIC_BASE_ADDR;
tzic_virt = ioremap(tzic_addr, SZ_16K);
if (!tzic_virt)
panic("unable to map TZIC interrupt controller\n");
tzic_init_irq(tzic_virt);
tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
}
void __init mx53_init_irq(void)
{
unsigned long tzic_addr;
void __iomem *tzic_virt;
tzic_addr = MX53_TZIC_BASE_ADDR;
tzic_virt = ioremap(tzic_addr, SZ_16K);
if (!tzic_virt)
panic("unable to map TZIC interrupt controller\n");
tzic_init_irq(tzic_virt);
tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
}
static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
@ -138,13 +151,24 @@ static struct sdma_platform_data imx53_sdma_pdata __initdata = {
.script_addrs = &imx53_sdma_script,
};
void __init imx50_soc_init(void)
{
/* i.mx50 has the i.mx31 type gpio */
mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
}
void __init imx51_soc_init(void)
{
/* i.mx51 has the i.mx31 type gpio */
mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO1_LOW, MX51_MXC_INT_GPIO1_HIGH);
mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH);
mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH);
mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH);
mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
/* i.mx51 has the i.mx35 type sdma */
imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);

17
arch/arm/mach-mx5/mx51_efika.c
View File

@ -34,14 +34,12 @@
#include <linux/usb/ulpi.h>
#include <mach/ulpi.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "devices-imx51.h"
#include "devices.h"
#include "efika.h"
#include "cpu_op-mx51.h"
@ -133,7 +131,7 @@ static int initialize_otg_port(struct platform_device *pdev)
u32 v;
void __iomem *usb_base;
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
if (!usb_base)
return -ENOMEM;
usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
@ -150,7 +148,7 @@ static int initialize_otg_port(struct platform_device *pdev)
return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
}
static struct mxc_usbh_platform_data dr_utmi_config = {
static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
.init = initialize_otg_port,
.portsc = MXC_EHCI_UTMI_16BIT,
};
@ -170,7 +168,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
gpio_set_value(EFIKAMX_USBH1_STP, 1);
msleep(1);
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
/* The clock for the USBH1 ULPI port will come externally */
@ -189,7 +187,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
}
static struct mxc_usbh_platform_data usbh1_config = {
static struct mxc_usbh_platform_data usbh1_config __initdata = {
.init = initialize_usbh1_port,
.portsc = MXC_EHCI_MODE_ULPI,
};
@ -217,9 +215,9 @@ static void __init mx51_efika_usb(void)
usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
imx51_add_mxc_ehci_otg(&dr_utmi_config);
if (usbh1_config.otg)
mxc_register_device(&mxc_usbh1_device, &usbh1_config);
imx51_add_mxc_ehci_hs(1, &usbh1_config);
}
static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
@ -589,7 +587,7 @@ static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
.bus_num = 0,
.chip_select = 0,
.platform_data = &mx51_efika_mc13892_data,
.irq = gpio_to_irq(EFIKAMX_PMIC),
.irq = IMX_GPIO_TO_IRQ(EFIKAMX_PMIC),
},
};
@ -632,4 +630,3 @@ void __init efika_board_common_init(void)
get_cpu_op = mx51_get_cpu_op;
#endif
}

18
arch/arm/mach-mx5/pm-imx5.c
View File

@ -14,18 +14,15 @@
#include <linux/err.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <mach/system.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include "crm_regs.h"
static struct clk *gpc_dvfs_clk;
static int mx5_suspend_prepare(void)
{
return clk_enable(gpc_dvfs_clk);
}
static int mx5_suspend_enter(suspend_state_t state)
{
clk_enable(gpc_dvfs_clk);
switch (state) {
case PM_SUSPEND_MEM:
mx5_cpu_lp_set(STOP_POWER_OFF);
@ -46,12 +43,9 @@ static int mx5_suspend_enter(suspend_state_t state)
__raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
}
cpu_do_idle();
return 0;
}
static void mx5_suspend_finish(void)
{
clk_disable(gpc_dvfs_clk);
return 0;
}
static int mx5_pm_valid(suspend_state_t state)
@ -61,9 +55,7 @@ static int mx5_pm_valid(suspend_state_t state)
static const struct platform_suspend_ops mx5_suspend_ops = {
.valid = mx5_pm_valid,
.prepare = mx5_suspend_prepare,
.enter = mx5_suspend_enter,
.finish = mx5_suspend_finish,
};
static int __init mx5_pm_init(void)

1
arch/arm/mach-mx5/system.c
View File

@ -13,6 +13,7 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include "crm_regs.h"
/* set cpu low power mode before WFI instruction. This function is called

6
arch/arm/mach-mxs/Makefile
View File

@ -1,11 +1,11 @@
# Common support
obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o
obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o mm.o
obj-$(CONFIG_MXS_OCOTP) += ocotp.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o

4
arch/arm/mach-mxs/include/mach/gpio.h
View File

@ -22,14 +22,10 @@
#include <asm-generic/gpio.h>
#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr))
/* use gpiolib dispatchers */
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
#define irq_to_gpio(irq) ((irq) - MXS_GPIO_IRQ_START)
#endif /* __MACH_MXS_GPIO_H__ */

2
arch/arm/mach-mxs/include/mach/mxs.h
View File

@ -86,6 +86,8 @@
.type = _type, \
}
#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr))
#define MXS_SET_ADDR 0x4
#define MXS_CLR_ADDR 0x8
#define MXS_TOG_ADDR 0xc

1
arch/arm/mach-mxs/mach-mx23evk.c
View File

@ -15,7 +15,6 @@
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>

24
arch/arm/mach-mxs/mach-mx28evk.c
View File

@ -16,7 +16,6 @@
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/regulator/machine.h>
@ -417,6 +416,11 @@ static void __init mx28evk_add_regulators(void)
static void __init mx28evk_add_regulators(void) {}
#endif
static struct gpio mx28evk_lcd_gpios[] = {
{ MX28EVK_LCD_ENABLE, GPIOF_OUT_INIT_HIGH, "lcd-enable" },
{ MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" },
};
static void __init mx28evk_init(void)
{
int ret;
@ -443,19 +447,12 @@ static void __init mx28evk_init(void)
mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]);
}
ret = gpio_request_one(MX28EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
ret = gpio_request_array(mx28evk_lcd_gpios,
ARRAY_SIZE(mx28evk_lcd_gpios));
if (ret)
pr_warn("failed to request gpio lcd-enable: %d\n", ret);
pr_warn("failed to request gpio pins for lcd: %d\n", ret);
else
gpio_set_value(MX28EVK_LCD_ENABLE, 1);
ret = gpio_request_one(MX28EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
if (ret)
pr_warn("failed to request gpio bl-enable: %d\n", ret);
else
gpio_set_value(MX28EVK_BL_ENABLE, 1);
mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
mx28_add_saif(0);
mx28_add_saif(1);
@ -480,6 +477,9 @@ static void __init mx28evk_init(void)
"mmc1-slot-power");
if (ret)
pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret);
else
mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
mx28_add_rtc_stmp3xxx();

1
arch/arm/mach-mxs/mach-stmp378x_devb.c
View File

@ -19,7 +19,6 @@
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/spi/spi.h>
#include <asm/mach-types.h>

44
arch/arm/mach-mxs/mm-mx28.c
View File

@ -1,44 +0,0 @@
/*
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*
* Create static mapping between physical to virtual memory.
*/
#include <linux/mm.h>
#include <linux/init.h>
#include <asm/mach/map.h>
#include <mach/mx28.h>
#include <mach/common.h>
#include <mach/iomux.h>
/*
* Define the MX28 memory map.
*/
static struct map_desc mx28_io_desc[] __initdata = {
mxs_map_entry(MX28, OCRAM, MT_DEVICE),
mxs_map_entry(MX28, IO, MT_DEVICE),
};
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
* for the IO modules.
*/
void __init mx28_map_io(void)
{
iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc));
}
void __init mx28_init_irq(void)
{
icoll_init_irq();
}

19
arch/arm/mach-mxs/mm-mx23.c → arch/arm/mach-mxs/mm.c
View File

@ -17,6 +17,7 @@
#include <asm/mach/map.h>
#include <mach/mx23.h>
#include <mach/mx28.h>
#include <mach/common.h>
#include <mach/iomux.h>
@ -28,6 +29,14 @@ static struct map_desc mx23_io_desc[] __initdata = {
mxs_map_entry(MX23, IO, MT_DEVICE),
};
/*
* Define the MX28 memory map.
*/
static struct map_desc mx28_io_desc[] __initdata = {
mxs_map_entry(MX28, OCRAM, MT_DEVICE),
mxs_map_entry(MX28, IO, MT_DEVICE),
};
/*
* This function initializes the memory map. It is called during the
* system startup to create static physical to virtual memory mappings
@ -42,3 +51,13 @@ void __init mx23_init_irq(void)
{
icoll_init_irq();
}
void __init mx28_map_io(void)
{
iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc));
}
void __init mx28_init_irq(void)
{
icoll_init_irq();
}

18
arch/arm/plat-mxc/audmux-v2.c
View File

@ -187,18 +187,11 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
static int mxc_audmux_v2_init(void)
{
int ret;
#if defined(CONFIG_ARCH_MX5)
if (cpu_is_mx51()) {
audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR);
ret = 0;
return ret;
}
#endif
#if defined(CONFIG_ARCH_MX3)
if (cpu_is_mx31())
} else if (cpu_is_mx31()) {
audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
else if (cpu_is_mx35()) {
} else if (cpu_is_mx35()) {
audmux_clk = clk_get(NULL, "audmux");
if (IS_ERR(audmux_clk)) {
ret = PTR_ERR(audmux_clk);
@ -207,10 +200,7 @@ static int mxc_audmux_v2_init(void)
return ret;
}
audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
}
#endif
#if defined(CONFIG_SOC_IMX25)
if (cpu_is_mx25()) {
} else if (cpu_is_mx25()) {
audmux_clk = clk_get(NULL, "audmux");
if (IS_ERR(audmux_clk)) {
ret = PTR_ERR(audmux_clk);
@ -220,7 +210,7 @@ static int mxc_audmux_v2_init(void)
}
audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
}
#endif /* if defined(CONFIG_SOC_IMX25) */
audmux_debugfs_init();
return 0;

14
arch/arm/plat-mxc/devices.c
View File

@ -23,20 +23,6 @@
#include <linux/platform_device.h>
#include <mach/common.h>
int __init mxc_register_device(struct platform_device *pdev, void *data)
{
int ret;
pdev->dev.platform_data = data;
ret = platform_device_register(pdev);
if (ret)
pr_debug("Unable to register platform device '%s': %d\n",
pdev->name, ret);
return ret;
}
struct platform_device *__init imx_add_platform_device_dmamask(
const char *name, int id,
const struct resource *res, unsigned int num_resources,

2
arch/arm/plat-mxc/devices/Kconfig
View File

@ -1,6 +1,6 @@
config IMX_HAVE_PLATFORM_FEC
bool
default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53
default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX50 || SOC_IMX51 || SOC_IMX53
config IMX_HAVE_PLATFORM_FLEXCAN
select HAVE_CAN_FLEXCAN if CAN

5
arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
View File

@ -36,6 +36,11 @@ const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX35);
#endif /* ifdef CONFIG_SOC_IMX35 */
#ifdef CONFIG_SOC_IMX51
const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data __initconst =
imx_fsl_usb2_udc_data_entry_single(MX51);
#endif
struct platform_device *__init imx_add_fsl_usb2_udc(
const struct imx_fsl_usb2_udc_data *data,
const struct fsl_usb2_platform_data *pdata)

6
arch/arm/plat-mxc/devices/platform-imx-i2c.c
View File

@ -85,6 +85,12 @@ const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K)
imx51_imx_i2c_data_entry(0, 1),
imx51_imx_i2c_data_entry(1, 2),
{
.id = 2,
.iobase = MX51_HSI2C_DMA_BASE_ADDR,
.iosize = SZ_16K,
.irq = MX51_INT_HS_I2C,
},
};
#endif /* ifdef CONFIG_SOC_IMX51 */

9
arch/arm/plat-mxc/devices/platform-mxc-ehci.c
View File

@ -49,6 +49,15 @@ const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst =
imx_mxc_ehci_data_entry_single(MX35, 1, HS);
#endif /* ifdef CONFIG_SOC_IMX35 */
#ifdef CONFIG_SOC_IMX51
const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data __initconst =
imx_mxc_ehci_data_entry_single(MX51, 0, OTG);
const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[] __initconst = {
imx_mxc_ehci_data_entry_single(MX51, 1, HS1),
imx_mxc_ehci_data_entry_single(MX51, 2, HS2),
};
#endif /* ifdef CONFIG_SOC_IMX51 */
struct platform_device *__init imx_add_mxc_ehci(
const struct imx_mxc_ehci_data *data,
const struct mxc_usbh_platform_data *pdata)

12
arch/arm/plat-mxc/include/mach/common.h
View File

@ -66,12 +66,22 @@ extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
unsigned long ckih1, unsigned long ckih2);
extern struct platform_device *mxc_register_gpio(char *name, int id,
resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
extern int mxc_register_device(struct platform_device *pdev, void *data);
extern void mxc_set_cpu_type(unsigned int type);
extern void mxc_arch_reset_init(void __iomem *);
extern void mx51_efikamx_reset(void);
extern int mx53_revision(void);
extern int mx53_display_revision(void);
enum mxc_cpu_pwr_mode {
WAIT_CLOCKED, /* wfi only */
WAIT_UNCLOCKED, /* WAIT */
WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
STOP_POWER_ON, /* just STOP */
STOP_POWER_OFF, /* STOP + SRPG */
};
extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
extern void (*imx_idle)(void);
extern void imx_print_silicon_rev(const char *cpu, int srev);
void avic_handle_irq(struct pt_regs *);

9
arch/arm/plat-mxc/include/mach/gpio.h
View File

@ -23,17 +23,10 @@
#include <mach/hardware.h>
#include <asm-generic/gpio.h>
/* There's a off-by-one betweem the gpio bank number and the gpiochip */
/* range e.g. GPIO_1_5 is gpio 5 under linux */
#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
/* use gpiolib dispatchers */
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq(gpio) (MXC_GPIO_IRQ_START + (gpio))
#define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START)
#define gpio_to_irq __gpio_to_irq
#endif

13
arch/arm/plat-mxc/include/mach/hardware.h
View File

@ -81,11 +81,16 @@
* AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
* AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
* mx51:
* TZIC 0xe0000000+0x004000 -> 0xf5000000+0x004000
* IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
* DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000
* SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
* AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
* AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000
* mx53:
* TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
* AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
* AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
*/
#define IMX_IO_P2V(x) ( \
0xf4000000 + \
@ -116,4 +121,10 @@
.type = _type, \
}
/* There's a off-by-one betweem the gpio bank number and the gpiochip */
/* range e.g. GPIO_1_5 is gpio 5 under linux */
#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
#define IMX_GPIO_TO_IRQ(gpio) (MXC_GPIO_IRQ_START + (gpio))
#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */

22
arch/arm/plat-mxc/include/mach/io.h
View File

@ -14,32 +14,22 @@
/* Allow IO space to be anywhere in the memory */
#define IO_SPACE_LIMIT 0xffffffff
#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35)
#include <mach/hardware.h>
#define __arch_ioremap __imx_ioremap
#define __arch_iounmap __iounmap
#define addr_in_module(addr, mod) \
((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
extern void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int);
static inline void __iomem *
__imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
{
if (mtype == MT_DEVICE && (cpu_is_mx31() || cpu_is_mx35())) {
/*
* Access all peripherals below 0x80000000 as nonshared device
* on mx3, but leave l2cc alone. Otherwise cache corruptions
* can occur.
*/
if (phys_addr < 0x80000000 &&
!addr_in_module(phys_addr, MX3x_L2CC))
mtype = MT_DEVICE_NONSHARED;
}
return __arm_ioremap(phys_addr, size, mtype);
if (imx_ioremap != NULL)
return imx_ioremap(phys_addr, size, mtype);
else
return __arm_ioremap(phys_addr, size, mtype);
}
#endif
/* io address mapping macro */
#define __io(a) __typesafe_io(a)

2270
arch/arm/plat-mxc/include/mach/iomux-mx51.h
View File

File diff suppressed because it is too large Load Diff

3530
arch/arm/plat-mxc/include/mach/iomux-mx53.h
View File

File diff suppressed because it is too large Load Diff

1
arch/arm/plat-mxc/include/mach/iomux-v3.h
View File

@ -80,6 +80,7 @@ typedef u64 iomux_v3_cfg_t;
((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \
((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT))
#define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(pad))
/*
* Use to set PAD control
*/

183
arch/arm/plat-mxc/include/mach/mx51.h
View File

@ -18,18 +18,6 @@
#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
#define MX51_DEBUG_BASE_ADDR 0x60000000
#define MX51_DEBUG_SIZE SZ_1M
#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000)
#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x02000)
#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x03000)
#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x04000)
#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x05000)
#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x06000)
#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x07000)
#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x08000)
/*
* SPBA global module enabled #0
*/
@ -55,7 +43,10 @@
#define MX51_AIPS1_BASE_ADDR 0x73f00000
#define MX51_AIPS1_SIZE SZ_1M
#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000)
#define MX51_USB_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000)
#define MX51_USB_OTG_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0000)
#define MX51_USB_HS1_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0200)
#define MX51_USB_HS2_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0400)
#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000)
#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000)
#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000)
@ -132,6 +123,7 @@
#define MX51_GPU2D_BASE_ADDR 0xd0000000
#define MX51_TZIC_BASE_ADDR 0xe0000000
#define MX51_TZIC_SIZE SZ_16K
#define MX51_IO_P2V(x) IMX_IO_P2V(x)
#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x))
@ -240,117 +232,114 @@
/*
* Interrupt numbers
*/
#define MX51_MXC_INT_BASE 0
#define MX51_MXC_INT_RESV0 0
#define MX51_INT_BASE 0
#define MX51_INT_RESV0 0
#define MX51_INT_ESDHC1 1
#define MX51_INT_ESDHC2 2
#define MX51_INT_ESDHC3 3
#define MX51_INT_ESDHC4 4
#define MX51_MXC_INT_RESV5 5
#define MX51_INT_RESV5 5
#define MX51_INT_SDMA 6
#define MX51_MXC_INT_IOMUX 7
#define MX51_INT_IOMUX 7
#define MX51_INT_NFC 8
#define MX51_MXC_INT_VPU 9
#define MX51_INT_VPU 9
#define MX51_INT_IPU_ERR 10
#define MX51_INT_IPU_SYN 11
#define MX51_MXC_INT_GPU 12
#define MX51_MXC_INT_RESV13 13
#define MX51_MXC_INT_USB_H1 14
#define MX51_MXC_INT_EMI 15
#define MX51_MXC_INT_USB_H2 16
#define MX51_MXC_INT_USB_H3 17
#define MX51_MXC_INT_USB_OTG 18
#define MX51_MXC_INT_SAHARA_H0 19
#define MX51_MXC_INT_SAHARA_H1 20
#define MX51_MXC_INT_SCC_SMN 21
#define MX51_MXC_INT_SCC_STZ 22
#define MX51_MXC_INT_SCC_SCM 23
#define MX51_MXC_INT_SRTC_NTZ 24
#define MX51_MXC_INT_SRTC_TZ 25
#define MX51_MXC_INT_RTIC 26
#define MX51_MXC_INT_CSU 27
#define MX51_MXC_INT_SLIM_B 28
#define MX51_INT_GPU 12
#define MX51_INT_RESV13 13
#define MX51_INT_USB_HS1 14
#define MX51_INT_EMI 15
#define MX51_INT_USB_HS2 16
#define MX51_INT_USB_HS3 17
#define MX51_INT_USB_OTG 18
#define MX51_INT_SAHARA_H0 19
#define MX51_INT_SAHARA_H1 20
#define MX51_INT_SCC_SMN 21
#define MX51_INT_SCC_STZ 22
#define MX51_INT_SCC_SCM 23
#define MX51_INT_SRTC_NTZ 24
#define MX51_INT_SRTC_TZ 25
#define MX51_INT_RTIC 26
#define MX51_INT_CSU 27
#define MX51_INT_SLIM_B 28
#define MX51_INT_SSI1 29
#define MX51_INT_SSI2 30
#define MX51_INT_UART1 31
#define MX51_INT_UART2 32
#define MX51_INT_UART3 33
#define MX51_MXC_INT_RESV34 34
#define MX51_MXC_INT_RESV35 35
#define MX51_INT_RESV34 34
#define MX51_INT_RESV35 35
#define MX51_INT_ECSPI1 36
#define MX51_INT_ECSPI2 37
#define MX51_INT_CSPI 38
#define MX51_MXC_INT_GPT 39
#define MX51_MXC_INT_EPIT1 40
#define MX51_MXC_INT_EPIT2 41
#define MX51_MXC_INT_GPIO1_INT7 42
#define MX51_MXC_INT_GPIO1_INT6 43
#define MX51_MXC_INT_GPIO1_INT5 44
#define MX51_MXC_INT_GPIO1_INT4 45
#define MX51_MXC_INT_GPIO1_INT3 46
#define MX51_MXC_INT_GPIO1_INT2 47
#define MX51_MXC_INT_GPIO1_INT1 48
#define MX51_MXC_INT_GPIO1_INT0 49
#define MX51_MXC_INT_GPIO1_LOW 50
#define MX51_MXC_INT_GPIO1_HIGH 51
#define MX51_MXC_INT_GPIO2_LOW 52
#define MX51_MXC_INT_GPIO2_HIGH 53
#define MX51_MXC_INT_GPIO3_LOW 54
#define MX51_MXC_INT_GPIO3_HIGH 55
#define MX51_MXC_INT_GPIO4_LOW 56
#define MX51_MXC_INT_GPIO4_HIGH 57
#define MX51_MXC_INT_WDOG1 58
#define MX51_MXC_INT_WDOG2 59
#define MX51_INT_GPT 39
#define MX51_INT_EPIT1 40
#define MX51_INT_EPIT2 41
#define MX51_INT_GPIO1_INT7 42
#define MX51_INT_GPIO1_INT6 43
#define MX51_INT_GPIO1_INT5 44
#define MX51_INT_GPIO1_INT4 45
#define MX51_INT_GPIO1_INT3 46
#define MX51_INT_GPIO1_INT2 47
#define MX51_INT_GPIO1_INT1 48
#define MX51_INT_GPIO1_INT0 49
#define MX51_INT_GPIO1_LOW 50
#define MX51_INT_GPIO1_HIGH 51
#define MX51_INT_GPIO2_LOW 52
#define MX51_INT_GPIO2_HIGH 53
#define MX51_INT_GPIO3_LOW 54
#define MX51_INT_GPIO3_HIGH 55
#define MX51_INT_GPIO4_LOW 56
#define MX51_INT_GPIO4_HIGH 57
#define MX51_INT_WDOG1 58
#define MX51_INT_WDOG2 59
#define MX51_INT_KPP 60
#define MX51_INT_PWM1 61
#define MX51_INT_I2C1 62
#define MX51_INT_I2C2 63
#define MX51_MXC_INT_HS_I2C 64
#define MX51_MXC_INT_RESV65 65
#define MX51_MXC_INT_RESV66 66
#define MX51_MXC_INT_SIM_IPB 67
#define MX51_MXC_INT_SIM_DAT 68
#define MX51_MXC_INT_IIM 69
#define MX51_MXC_INT_ATA 70
#define MX51_MXC_INT_CCM1 71
#define MX51_MXC_INT_CCM2 72
#define MX51_MXC_INT_GPC1 73
#define MX51_MXC_INT_GPC2 74
#define MX51_MXC_INT_SRC 75
#define MX51_MXC_INT_NM 76
#define MX51_MXC_INT_PMU 77
#define MX51_MXC_INT_CTI_IRQ 78
#define MX51_MXC_INT_CTI1_TG0 79
#define MX51_MXC_INT_CTI1_TG1 80
#define MX51_MXC_INT_MCG_ERR 81
#define MX51_MXC_INT_MCG_TMR 82
#define MX51_MXC_INT_MCG_FUNC 83
#define MX51_MXC_INT_GPU2_IRQ 84
#define MX51_MXC_INT_GPU2_BUSY 85
#define MX51_MXC_INT_RESV86 86
#define MX51_INT_HS_I2C 64
#define MX51_INT_RESV65 65
#define MX51_INT_RESV66 66
#define MX51_INT_SIM_IPB 67
#define MX51_INT_SIM_DAT 68
#define MX51_INT_IIM 69
#define MX51_INT_ATA 70
#define MX51_INT_CCM1 71
#define MX51_INT_CCM2 72
#define MX51_INT_GPC1 73
#define MX51_INT_GPC2 74
#define MX51_INT_SRC 75
#define MX51_INT_NM 76
#define MX51_INT_PMU 77
#define MX51_INT_CTI_IRQ 78
#define MX51_INT_CTI1_TG0 79
#define MX51_INT_CTI1_TG1 80
#define MX51_INT_MCG_ERR 81
#define MX51_INT_MCG_TMR 82
#define MX51_INT_MCG_FUNC 83
#define MX51_INT_GPU2_IRQ 84
#define MX51_INT_GPU2_BUSY 85
#define MX51_INT_RESV86 86
#define MX51_INT_FEC 87
#define MX51_MXC_INT_OWIRE 88
#define MX51_MXC_INT_CTI1_TG2 89
#define MX51_MXC_INT_SJC 90
#define MX51_MXC_INT_SPDIF 91
#define MX51_MXC_INT_TVE 92
#define MX51_MXC_INT_FIRI 93
#define MX51_INT_OWIRE 88
#define MX51_INT_CTI1_TG2 89
#define MX51_INT_SJC 90
#define MX51_INT_SPDIF 91
#define MX51_INT_TVE 92
#define MX51_INT_FIRI 93
#define MX51_INT_PWM2 94
#define MX51_MXC_INT_SLIM_EXP 95
#define MX51_INT_SLIM_EXP 95
#define MX51_INT_SSI3 96
#define MX51_MXC_INT_EMI_BOOT 97
#define MX51_MXC_INT_CTI1_TG3 98
#define MX51_MXC_INT_SMC_RX 99
#define MX51_MXC_INT_VPU_IDLE 100
#define MX51_MXC_INT_EMI_NFC 101
#define MX51_MXC_INT_GPU_IDLE 102
#define MX51_INT_EMI_BOOT 97
#define MX51_INT_CTI1_TG3 98
#define MX51_INT_SMC_RX 99
#define MX51_INT_VPU_IDLE 100
#define MX51_INT_EMI_NFC 101
#define MX51_INT_GPU_IDLE 102
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
extern int mx51_revision(void);
extern void mx51_display_revision(void);
#endif
/* tape-out 1 defines */
#define MX51_TZIC_BASE_ADDR_TO1 0x8fffc000
#endif /* ifndef __MACH_MX51_H__ */

1
arch/arm/plat-mxc/include/mach/mx53.h
View File

@ -9,6 +9,7 @@
/* TZIC */
#define MX53_TZIC_BASE_ADDR 0x0FFFC000
#define MX53_TZIC_SIZE SZ_16K
/*
* AHCI SATA

7
arch/arm/plat-mxc/include/mach/mxc.h
View File

@ -183,13 +183,6 @@ struct cpu_op {
};
int tzic_enable_wake(int is_idle);
enum mxc_cpu_pwr_mode {
WAIT_CLOCKED, /* wfi only */
WAIT_UNCLOCKED, /* WAIT */
WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
STOP_POWER_ON, /* just STOP */
STOP_POWER_OFF, /* STOP + SRPG */
};
extern struct cpu_op *(*get_cpu_op)(int *op);
#endif

35
arch/arm/plat-mxc/include/mach/system.h
View File

@ -17,41 +17,12 @@
#ifndef __ASM_ARCH_MXC_SYSTEM_H__
#define __ASM_ARCH_MXC_SYSTEM_H__
#include <mach/hardware.h>
#include <mach/common.h>
extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
extern void (*imx_idle)(void);
static inline void arch_idle(void)
{
/* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
if (cpu_is_mx31() || cpu_is_mx35()) {
unsigned long reg = 0;
__asm__ __volatile__(
/* disable I and D cache */
"mrc p15, 0, %0, c1, c0, 0\n"
"bic %0, %0, #0x00001000\n"
"bic %0, %0, #0x00000004\n"
"mcr p15, 0, %0, c1, c0, 0\n"
/* invalidate I cache */
"mov %0, #0\n"
"mcr p15, 0, %0, c7, c5, 0\n"
/* clear and invalidate D cache */
"mov %0, #0\n"
"mcr p15, 0, %0, c7, c14, 0\n"
/* WFI */
"mov %0, #0\n"
"mcr p15, 0, %0, c7, c0, 4\n"
"nop\n" "nop\n" "nop\n" "nop\n"
"nop\n" "nop\n" "nop\n"
/* enable I and D cache */
"mrc p15, 0, %0, c1, c0, 0\n"
"orr %0, %0, #0x00001000\n"
"orr %0, %0, #0x00000004\n"
"mcr p15, 0, %0, c1, c0, 0\n"
: "=r" (reg));
} else if (cpu_is_mx51())
mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
if (imx_idle != NULL)
(imx_idle)();
else
cpu_do_idle();
}

3
arch/arm/plat-mxc/system.c
View File

@ -28,6 +28,9 @@
#include <asm/system.h>
#include <asm/mach-types.h>
void (*imx_idle)(void) = NULL;
void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
static void __iomem *wdog_base;
/*

12
drivers/gpio/gpio-mxc.c
View File

@ -31,6 +31,8 @@
#include <linux/of_device.h>
#include <asm-generic/bug.h>
#define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START)
enum mxc_gpio_hwtype {
IMX1_GPIO, /* runs on i.mx1 */
IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
@ -337,6 +339,15 @@ static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
mxc_gpio_hwtype = hwtype;
}
static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
struct bgpio_chip *bgc = to_bgpio_chip(gc);
struct mxc_gpio_port *port =
container_of(bgc, struct mxc_gpio_port, bgc);
return port->virtual_irq_start + offset;
}
static int __devinit mxc_gpio_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@ -403,6 +414,7 @@ static int __devinit mxc_gpio_probe(struct platform_device *pdev)
if (err)
goto out_iounmap;
port->bgc.gc.to_irq = mxc_gpio_to_irq;
port->bgc.gc.base = pdev->id * 32;
port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);

2
drivers/gpio/gpio-mxs.c
View File

@ -49,6 +49,8 @@
#define GPIO_INT_LEV_MASK (1 << 0)
#define GPIO_INT_POL_MASK (1 << 1)
#define irq_to_gpio(irq) ((irq) - MXS_GPIO_IRQ_START)
struct mxs_gpio_port {
void __iomem *base;
int id;