drm/i915: Avoid use of uninitialised values when disabling panel-fitter
We were passing garbage values into the panel-fitter control register when disabling it on Ironlake - those values (filter modes and reserved MBZ bits) would have then be re-used the next time panel-fitting was enabled. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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@ -1865,9 +1865,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
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int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
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int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
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int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
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int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
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int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
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int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
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int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
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int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
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int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
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@ -1936,15 +1933,19 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
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}
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/* Enable panel fitting for LVDS */
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
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|| HAS_eDP || intel_pch_has_edp(crtc)) {
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if (dev_priv->pch_pf_size) {
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temp = I915_READ(pf_ctl_reg);
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I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
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I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos);
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I915_WRITE(pf_win_size, dev_priv->pch_pf_size);
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} else
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I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
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if (dev_priv->pch_pf_size &&
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(intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
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|| HAS_eDP || intel_pch_has_edp(crtc))) {
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/* Force use of hard-coded filter coefficients
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* as some pre-programmed values are broken,
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* e.g. x201.
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*/
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I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
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PF_ENABLE | PF_FILTER_MED_3x3);
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I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
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dev_priv->pch_pf_pos);
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I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
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dev_priv->pch_pf_size);
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}
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/* Enable CPU pipe */
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@ -2109,14 +2110,8 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
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udelay(100);
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/* Disable PF */
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temp = I915_READ(pf_ctl_reg);
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if ((temp & PF_ENABLE) != 0) {
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I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
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I915_READ(pf_ctl_reg);
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}
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I915_WRITE(pf_win_size, 0);
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POSTING_READ(pf_win_size);
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I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
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I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
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/* disable CPU FDI tx and PCH FDI rx */
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temp = I915_READ(fdi_tx_reg);
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