drm/i915/gvt: Handle MMIO GEN8_GAMW_ECO_DEV_RW_IA for 64K GTT
The register RENDER_HWS_PGA_GEN7 is renamed to GEN8_GAMW_ECO_DEV_RW_IA from GEN8 which can control IPS enabling. v3: MMIO control for IPS is not removed from gen9 but gen10 (Matthew Auld) v2: IPS of all engines must be enabled together for gen9. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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@ -210,6 +210,31 @@ static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
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return 0;
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}
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static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu,
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unsigned int offset, void *p_data, unsigned int bytes)
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{
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u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;
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if (INTEL_GEN(vgpu->gvt->dev_priv) <= 10) {
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if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD)
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gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id);
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else if (!ips)
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gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id);
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else {
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/* All engines must be enabled together for vGPU,
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* since we don't know which engine the ppgtt will
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* bind to when shadowing.
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*/
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gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n",
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ips);
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return -EINVAL;
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}
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}
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write_vreg(vgpu, offset, p_data, bytes);
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return 0;
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}
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static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
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void *p_data, unsigned int bytes)
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{
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@ -1769,7 +1794,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
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MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL);
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MMIO_GM_RDR(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL);
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MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
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gamw_echo_dev_rw_ia_write);
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MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
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MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
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MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
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