ARM: SAMSUNG: Consolidate plat/pll.h
Removed - arch/arm/plat-s3c24xx/include/plat/pll.h - arch/arm/mach-s3c64xx/include/mach/pll.h - arch/arm/plat-s5p/include/plat/pll.h - arch/arm/plat-samsung/include/plat/pll6553x.h And created - arch/arm/plat-samsung/include/plat/pll.h Cc: Ben Dooks <ben-linux@fluff.org> [kgene.kim@samsung.com: changed title] [kgene.kim@samsung.com: fixed conflicts in plat-s5p/include/pll.h] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>hifive-unleashed-5.1
Kukjin Kim
parent
c0468b0244
commit
52e329ebb0
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@ -696,9 +696,9 @@ static void __init h1940_init(void)
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S3C2410_MISCCR_USBSUSPND0 |
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S3C2410_MISCCR_USBSUSPND1, 0x0);
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tmp = (0x78 << S3C24XX_PLLCON_MDIVSHIFT)
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| (0x02 << S3C24XX_PLLCON_PDIVSHIFT)
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| (0x03 << S3C24XX_PLLCON_SDIVSHIFT);
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tmp = (0x78 << S3C24XX_PLL_MDIV_SHIFT)
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| (0x02 << S3C24XX_PLL_PDIV_SHIFT)
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| (0x03 << S3C24XX_PLL_SDIV_SHIFT);
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writel(tmp, S3C2410_UPLLCON);
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gpio_request(S3C2410_GPC(0), "LCD power");
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@ -21,7 +21,6 @@
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#include <plat/cpu.h>
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#include <plat/cpu-freq.h>
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#include <plat/pll6553x.h>
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#include <plat/pll.h>
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#include <asm/mach/map.h>
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@ -25,13 +25,13 @@
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#include <mach/regs-sys.h>
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#include <mach/regs-clock.h>
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#include <mach/pll.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/cpu-freq.h>
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#include <plat/clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/pll.h>
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/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
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* ext_xtal_mux for want of an actual name from the manual.
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@ -735,7 +735,8 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
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/* For now assume the mux always selects the crystal */
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clk_ext_xtal_mux.parent = xtal_clk;
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epll = s3c6400_get_epll(xtal);
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epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),
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__raw_readl(S3C_EPLL_CON1));
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mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
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apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
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@ -1,45 +0,0 @@
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/* arch/arm/plat-s3c64xx/include/plat/pll.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX PLL code
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1)
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#define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1)
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#define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1)
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#define S3C6400_PLL_MDIV_SHIFT (16)
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#define S3C6400_PLL_PDIV_SHIFT (8)
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#define S3C6400_PLL_SDIV_SHIFT (0)
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#include <asm/div64.h>
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#include <plat/pll6553x.h>
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static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
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u32 pllcon)
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{
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u32 mdiv, pdiv, sdiv;
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u64 fvco = baseclk;
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mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
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pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
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sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
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fvco *= mdiv;
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do_div(fvco, (pdiv << sdiv));
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return (unsigned long)fvco;
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}
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static inline unsigned long s3c6400_get_epll(unsigned long baseclk)
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{
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return s3c_get_pll6553x(baseclk, __raw_readl(S3C_EPLL_CON0),
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__raw_readl(S3C_EPLL_CON1));
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}
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@ -1,62 +0,0 @@
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/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h
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*
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C24xx - common pll registers and code
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*/
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#define S3C24XX_PLLCON_MDIVSHIFT 12
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#define S3C24XX_PLLCON_PDIVSHIFT 4
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#define S3C24XX_PLLCON_SDIVSHIFT 0
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#define S3C24XX_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1)
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#define S3C24XX_PLLCON_PDIVMASK ((1<<5)-1)
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#define S3C24XX_PLLCON_SDIVMASK 3
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#include <asm/div64.h>
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static inline unsigned int
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s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)
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{
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unsigned int mdiv, pdiv, sdiv;
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uint64_t fvco;
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mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT;
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pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT;
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sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT;
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mdiv &= S3C24XX_PLLCON_MDIVMASK;
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pdiv &= S3C24XX_PLLCON_PDIVMASK;
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sdiv &= S3C24XX_PLLCON_SDIVMASK;
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fvco = (uint64_t)baseclk * (mdiv + 8);
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do_div(fvco, (pdiv + 2) << sdiv);
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return (unsigned int)fvco;
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}
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#define S3C2416_PLL_M_SHIFT (14)
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#define S3C2416_PLL_P_SHIFT (5)
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#define S3C2416_PLL_S_MASK (7)
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#define S3C2416_PLL_M_MASK ((1 << 10) - 1)
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#define S3C2416_PLL_P_MASK (63)
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static inline unsigned int
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s3c2416_get_pll(unsigned int pllval, unsigned int baseclk)
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{
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unsigned int m, p, s;
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uint64_t fvco;
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m = pllval >> S3C2416_PLL_M_SHIFT;
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p = pllval >> S3C2416_PLL_P_SHIFT;
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s = pllval & S3C2416_PLL_S_MASK;
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m &= S3C2416_PLL_M_MASK;
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p &= S3C2416_PLL_P_MASK;
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fvco = (uint64_t)baseclk * m;
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do_div(fvco, (p << s));
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return (unsigned int)fvco;
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}
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@ -1,152 +0,0 @@
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/* arch/arm/plat-s5p/include/plat/pll.h
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*
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* Copyright (c) 2009 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5P PLL code
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*
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* Based on arch/arm/plat-s3c64xx/include/plat/pll.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define PLL45XX_MDIV_MASK (0x3FF)
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#define PLL45XX_PDIV_MASK (0x3F)
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#define PLL45XX_SDIV_MASK (0x7)
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#define PLL45XX_MDIV_SHIFT (16)
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#define PLL45XX_PDIV_SHIFT (8)
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#define PLL45XX_SDIV_SHIFT (0)
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#include <asm/div64.h>
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enum pll45xx_type_t {
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pll_4500,
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pll_4502,
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pll_4508
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};
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static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
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enum pll45xx_type_t pll_type)
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{
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u32 mdiv, pdiv, sdiv;
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u64 fvco = baseclk;
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mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
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pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
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sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
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if (pll_type == pll_4508)
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sdiv = sdiv - 1;
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fvco *= mdiv;
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do_div(fvco, (pdiv << sdiv));
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return (unsigned long)fvco;
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}
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#define PLL46XX_KDIV_MASK (0xFFFF)
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#define PLL4650C_KDIV_MASK (0xFFF)
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#define PLL46XX_MDIV_MASK (0x1FF)
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#define PLL46XX_PDIV_MASK (0x3F)
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#define PLL46XX_SDIV_MASK (0x7)
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#define PLL46XX_MDIV_SHIFT (16)
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#define PLL46XX_PDIV_SHIFT (8)
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#define PLL46XX_SDIV_SHIFT (0)
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enum pll46xx_type_t {
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pll_4600,
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pll_4650,
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pll_4650c,
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};
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static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
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u32 pll_con0, u32 pll_con1,
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enum pll46xx_type_t pll_type)
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{
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unsigned long result;
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u32 mdiv, pdiv, sdiv, kdiv;
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u64 tmp;
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mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
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pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
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sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
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if (pll_type == pll_4650c)
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kdiv = pll_con1 & PLL4650C_KDIV_MASK;
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else
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kdiv = pll_con1 & PLL46XX_KDIV_MASK;
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tmp = baseclk;
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if (pll_type == pll_4600) {
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tmp *= (mdiv << 16) + kdiv;
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do_div(tmp, (pdiv << sdiv));
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result = tmp >> 16;
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} else {
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tmp *= (mdiv << 10) + kdiv;
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do_div(tmp, (pdiv << sdiv));
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result = tmp >> 10;
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}
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return result;
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}
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#define PLL90XX_MDIV_MASK (0xFF)
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#define PLL90XX_PDIV_MASK (0x3F)
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#define PLL90XX_SDIV_MASK (0x7)
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#define PLL90XX_KDIV_MASK (0xffff)
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#define PLL90XX_MDIV_SHIFT (16)
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#define PLL90XX_PDIV_SHIFT (8)
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#define PLL90XX_SDIV_SHIFT (0)
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#define PLL90XX_KDIV_SHIFT (0)
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static inline unsigned long s5p_get_pll90xx(unsigned long baseclk,
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u32 pll_con, u32 pll_conk)
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{
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unsigned long result;
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u32 mdiv, pdiv, sdiv, kdiv;
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u64 tmp;
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mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK;
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pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK;
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sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK;
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kdiv = pll_conk & PLL90XX_KDIV_MASK;
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/* We need to multiple baseclk by mdiv (the integer part) and kdiv
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* which is in 2^16ths, so shift mdiv up (does not overflow) and
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* add kdiv before multiplying. The use of tmp is to avoid any
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* overflows before shifting bac down into result when multipling
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* by the mdiv and kdiv pair.
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*/
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tmp = baseclk;
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tmp *= (mdiv << 16) + kdiv;
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do_div(tmp, (pdiv << sdiv));
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result = tmp >> 16;
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return result;
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}
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#define PLL65XX_MDIV_MASK (0x3FF)
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#define PLL65XX_PDIV_MASK (0x3F)
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#define PLL65XX_SDIV_MASK (0x7)
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#define PLL65XX_MDIV_SHIFT (16)
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#define PLL65XX_PDIV_SHIFT (8)
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#define PLL65XX_SDIV_SHIFT (0)
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static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con)
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{
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u32 mdiv, pdiv, sdiv;
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u64 fvco = baseclk;
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mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK;
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pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK;
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sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK;
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fvco *= mdiv;
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do_div(fvco, (pdiv << sdiv));
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return (unsigned long)fvco;
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}
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@ -0,0 +1,323 @@
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/* linux/arch/arm/plat-samsung/include/plat/pll.h
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*
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* Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* Samsung PLL codes
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <asm/div64.h>
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#define S3C24XX_PLL_MDIV_MASK (0xFF)
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#define S3C24XX_PLL_PDIV_MASK (0x1F)
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#define S3C24XX_PLL_SDIV_MASK (0x3)
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#define S3C24XX_PLL_MDIV_SHIFT (12)
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#define S3C24XX_PLL_PDIV_SHIFT (4)
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#define S3C24XX_PLL_SDIV_SHIFT (0)
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static inline unsigned int s3c24xx_get_pll(unsigned int pllval,
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unsigned int baseclk)
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{
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unsigned int mdiv, pdiv, sdiv;
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uint64_t fvco;
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mdiv = (pllval >> S3C24XX_PLL_MDIV_SHIFT) & S3C24XX_PLL_MDIV_MASK;
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pdiv = (pllval >> S3C24XX_PLL_PDIV_SHIFT) & S3C24XX_PLL_PDIV_MASK;
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sdiv = (pllval >> S3C24XX_PLL_SDIV_SHIFT) & S3C24XX_PLL_SDIV_MASK;
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fvco = (uint64_t)baseclk * (mdiv + 8);
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do_div(fvco, (pdiv + 2) << sdiv);
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return (unsigned int)fvco;
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}
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#define S3C2416_PLL_MDIV_MASK (0x3FF)
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#define S3C2416_PLL_PDIV_MASK (0x3F)
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#define S3C2416_PLL_SDIV_MASK (0x7)
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#define S3C2416_PLL_MDIV_SHIFT (14)
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#define S3C2416_PLL_PDIV_SHIFT (5)
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#define S3C2416_PLL_SDIV_SHIFT (0)
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static inline unsigned int s3c2416_get_pll(unsigned int pllval,
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unsigned int baseclk)
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{
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unsigned int mdiv, pdiv, sdiv;
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uint64_t fvco;
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mdiv = (pllval >> S3C2416_PLL_MDIV_SHIFT) & S3C2416_PLL_MDIV_MASK;
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pdiv = (pllval >> S3C2416_PLL_PDIV_SHIFT) & S3C2416_PLL_PDIV_MASK;
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sdiv = (pllval >> S3C2416_PLL_SDIV_SHIFT) & S3C2416_PLL_SDIV_MASK;
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fvco = (uint64_t)baseclk * mdiv;
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do_div(fvco, (pdiv << sdiv));
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return (unsigned int)fvco;
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}
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#define S3C6400_PLL_MDIV_MASK (0x3FF)
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#define S3C6400_PLL_PDIV_MASK (0x3F)
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#define S3C6400_PLL_SDIV_MASK (0x7)
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#define S3C6400_PLL_MDIV_SHIFT (16)
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#define S3C6400_PLL_PDIV_SHIFT (8)
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#define S3C6400_PLL_SDIV_SHIFT (0)
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static inline unsigned long s3c6400_get_pll(unsigned long baseclk,
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u32 pllcon)
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{
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u32 mdiv, pdiv, sdiv;
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u64 fvco = baseclk;
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mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;
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pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;
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sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;
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fvco *= mdiv;
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do_div(fvco, (pdiv << sdiv));
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return (unsigned long)fvco;
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}
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#define PLL6553X_MDIV_MASK (0x7F)
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#define PLL6553X_PDIV_MASK (0x1F)
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#define PLL6553X_SDIV_MASK (0x3)
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#define PLL6553X_KDIV_MASK (0xFFFF)
|
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#define PLL6553X_MDIV_SHIFT (16)
|
||||
#define PLL6553X_PDIV_SHIFT (8)
|
||||
#define PLL6553X_SDIV_SHIFT (0)
|
||||
|
||||
static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
|
||||
u32 pll_con0, u32 pll_con1)
|
||||
{
|
||||
unsigned long result;
|
||||
u32 mdiv, pdiv, sdiv, kdiv;
|
||||
u64 tmp;
|
||||
|
||||
mdiv = (pll_con0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
|
||||
pdiv = (pll_con0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
|
||||
sdiv = (pll_con0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
|
||||
kdiv = pll_con1 & PLL6553X_KDIV_MASK;
|
||||
|
||||
/*
|
||||
* We need to multiple baseclk by mdiv (the integer part) and kdiv
|
||||
* which is in 2^16ths, so shift mdiv up (does not overflow) and
|
||||
* add kdiv before multiplying. The use of tmp is to avoid any
|
||||
* overflows before shifting bac down into result when multipling
|
||||
* by the mdiv and kdiv pair.
|
||||
*/
|
||||
|
||||
tmp = baseclk;
|
||||
tmp *= (mdiv << 16) + kdiv;
|
||||
do_div(tmp, (pdiv << sdiv));
|
||||
result = tmp >> 16;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#define PLL35XX_MDIV_MASK (0x3FF)
|
||||
#define PLL35XX_PDIV_MASK (0x3F)
|
||||
#define PLL35XX_SDIV_MASK (0x7)
|
||||
#define PLL35XX_MDIV_SHIFT (16)
|
||||
#define PLL35XX_PDIV_SHIFT (8)
|
||||
#define PLL35XX_SDIV_SHIFT (0)
|
||||
|
||||
static inline unsigned long s5p_get_pll35xx(unsigned long baseclk, u32 pll_con)
|
||||
{
|
||||
u32 mdiv, pdiv, sdiv;
|
||||
u64 fvco = baseclk;
|
||||
|
||||
mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
|
||||
pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
|
||||
sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
|
||||
|
||||
fvco *= mdiv;
|
||||
do_div(fvco, (pdiv << sdiv));
|
||||
|
||||
return (unsigned long)fvco;
|
||||
}
|
||||
|
||||
#define PLL36XX_KDIV_MASK (0xFFFF)
|
||||
#define PLL36XX_MDIV_MASK (0x1FF)
|
||||
#define PLL36XX_PDIV_MASK (0x3F)
|
||||
#define PLL36XX_SDIV_MASK (0x7)
|
||||
#define PLL36XX_MDIV_SHIFT (16)
|
||||
#define PLL36XX_PDIV_SHIFT (8)
|
||||
#define PLL36XX_SDIV_SHIFT (0)
|
||||
|
||||
static inline unsigned long s5p_get_pll36xx(unsigned long baseclk,
|
||||
u32 pll_con0, u32 pll_con1)
|
||||
{
|
||||
unsigned long result;
|
||||
u32 mdiv, pdiv, sdiv, kdiv;
|
||||
u64 tmp;
|
||||
|
||||
mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
|
||||
pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
|
||||
sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
|
||||
kdiv = pll_con1 & PLL36XX_KDIV_MASK;
|
||||
|
||||
tmp = baseclk;
|
||||
|
||||
tmp *= (mdiv << 16) + kdiv;
|
||||
do_div(tmp, (pdiv << sdiv));
|
||||
result = tmp >> 16;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#define PLL45XX_MDIV_MASK (0x3FF)
|
||||
#define PLL45XX_PDIV_MASK (0x3F)
|
||||
#define PLL45XX_SDIV_MASK (0x7)
|
||||
#define PLL45XX_MDIV_SHIFT (16)
|
||||
#define PLL45XX_PDIV_SHIFT (8)
|
||||
#define PLL45XX_SDIV_SHIFT (0)
|
||||
|
||||
enum pll45xx_type_t {
|
||||
pll_4500,
|
||||
pll_4502,
|
||||
pll_4508
|
||||
};
|
||||
|
||||
static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
|
||||
enum pll45xx_type_t pll_type)
|
||||
{
|
||||
u32 mdiv, pdiv, sdiv;
|
||||
u64 fvco = baseclk;
|
||||
|
||||
mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
|
||||
pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
|
||||
sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
|
||||
|
||||
if (pll_type == pll_4508)
|
||||
sdiv = sdiv - 1;
|
||||
|
||||
fvco *= mdiv;
|
||||
do_div(fvco, (pdiv << sdiv));
|
||||
|
||||
return (unsigned long)fvco;
|
||||
}
|
||||
|
||||
/* CON0 bit-fields */
|
||||
#define PLL46XX_MDIV_MASK (0x1FF)
|
||||
#define PLL46XX_PDIV_MASK (0x3F)
|
||||
#define PLL46XX_SDIV_MASK (0x7)
|
||||
#define PLL46XX_LOCKED_SHIFT (29)
|
||||
#define PLL46XX_MDIV_SHIFT (16)
|
||||
#define PLL46XX_PDIV_SHIFT (8)
|
||||
#define PLL46XX_SDIV_SHIFT (0)
|
||||
|
||||
/* CON1 bit-fields */
|
||||
#define PLL46XX_MRR_MASK (0x1F)
|
||||
#define PLL46XX_MFR_MASK (0x3F)
|
||||
#define PLL46XX_KDIV_MASK (0xFFFF)
|
||||
#define PLL4650C_KDIV_MASK (0xFFF)
|
||||
#define PLL46XX_MRR_SHIFT (24)
|
||||
#define PLL46XX_MFR_SHIFT (16)
|
||||
#define PLL46XX_KDIV_SHIFT (0)
|
||||
|
||||
enum pll46xx_type_t {
|
||||
pll_4600,
|
||||
pll_4650,
|
||||
pll_4650c,
|
||||
};
|
||||
|
||||
static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
|
||||
u32 pll_con0, u32 pll_con1,
|
||||
enum pll46xx_type_t pll_type)
|
||||
{
|
||||
unsigned long result;
|
||||
u32 mdiv, pdiv, sdiv, kdiv;
|
||||
u64 tmp;
|
||||
|
||||
mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
|
||||
pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
|
||||
sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
|
||||
kdiv = pll_con1 & PLL46XX_KDIV_MASK;
|
||||
|
||||
if (pll_type == pll_4650c)
|
||||
kdiv = pll_con1 & PLL4650C_KDIV_MASK;
|
||||
else
|
||||
kdiv = pll_con1 & PLL46XX_KDIV_MASK;
|
||||
|
||||
tmp = baseclk;
|
||||
|
||||
if (pll_type == pll_4600) {
|
||||
tmp *= (mdiv << 16) + kdiv;
|
||||
do_div(tmp, (pdiv << sdiv));
|
||||
result = tmp >> 16;
|
||||
} else {
|
||||
tmp *= (mdiv << 10) + kdiv;
|
||||
do_div(tmp, (pdiv << sdiv));
|
||||
result = tmp >> 10;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#define PLL90XX_MDIV_MASK (0xFF)
|
||||
#define PLL90XX_PDIV_MASK (0x3F)
|
||||
#define PLL90XX_SDIV_MASK (0x7)
|
||||
#define PLL90XX_KDIV_MASK (0xffff)
|
||||
#define PLL90XX_LOCKED_SHIFT (29)
|
||||
#define PLL90XX_MDIV_SHIFT (16)
|
||||
#define PLL90XX_PDIV_SHIFT (8)
|
||||
#define PLL90XX_SDIV_SHIFT (0)
|
||||
#define PLL90XX_KDIV_SHIFT (0)
|
||||
|
||||
static inline unsigned long s5p_get_pll90xx(unsigned long baseclk,
|
||||
u32 pll_con, u32 pll_conk)
|
||||
{
|
||||
unsigned long result;
|
||||
u32 mdiv, pdiv, sdiv, kdiv;
|
||||
u64 tmp;
|
||||
|
||||
mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK;
|
||||
pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK;
|
||||
sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK;
|
||||
kdiv = pll_conk & PLL90XX_KDIV_MASK;
|
||||
|
||||
/*
|
||||
* We need to multiple baseclk by mdiv (the integer part) and kdiv
|
||||
* which is in 2^16ths, so shift mdiv up (does not overflow) and
|
||||
* add kdiv before multiplying. The use of tmp is to avoid any
|
||||
* overflows before shifting bac down into result when multipling
|
||||
* by the mdiv and kdiv pair.
|
||||
*/
|
||||
|
||||
tmp = baseclk;
|
||||
tmp *= (mdiv << 16) + kdiv;
|
||||
do_div(tmp, (pdiv << sdiv));
|
||||
result = tmp >> 16;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#define PLL65XX_MDIV_MASK (0x3FF)
|
||||
#define PLL65XX_PDIV_MASK (0x3F)
|
||||
#define PLL65XX_SDIV_MASK (0x7)
|
||||
#define PLL65XX_MDIV_SHIFT (16)
|
||||
#define PLL65XX_PDIV_SHIFT (8)
|
||||
#define PLL65XX_SDIV_SHIFT (0)
|
||||
|
||||
static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con)
|
||||
{
|
||||
u32 mdiv, pdiv, sdiv;
|
||||
u64 fvco = baseclk;
|
||||
|
||||
mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK;
|
||||
pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK;
|
||||
sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK;
|
||||
|
||||
fvco *= mdiv;
|
||||
do_div(fvco, (pdiv << sdiv));
|
||||
|
||||
return (unsigned long)fvco;
|
||||
}
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
/* arch/arm/plat-samsung/include/plat/pll6553x.h
|
||||
* partially from arch/arm/mach-s3c64xx/include/mach/pll.h
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* Samsung PLL6553x PLL code
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* S3C6400 and compatible (S3C2416, etc.) EPLL code */
|
||||
|
||||
#define PLL6553X_MDIV_MASK ((1 << (23-16)) - 1)
|
||||
#define PLL6553X_PDIV_MASK ((1 << (13-8)) - 1)
|
||||
#define PLL6553X_SDIV_MASK ((1 << (2-0)) - 1)
|
||||
#define PLL6553X_MDIV_SHIFT (16)
|
||||
#define PLL6553X_PDIV_SHIFT (8)
|
||||
#define PLL6553X_SDIV_SHIFT (0)
|
||||
#define PLL6553X_KDIV_MASK (0xffff)
|
||||
|
||||
static inline unsigned long s3c_get_pll6553x(unsigned long baseclk,
|
||||
u32 pll0, u32 pll1)
|
||||
{
|
||||
unsigned long result;
|
||||
u32 mdiv, pdiv, sdiv, kdiv;
|
||||
u64 tmp;
|
||||
|
||||
mdiv = (pll0 >> PLL6553X_MDIV_SHIFT) & PLL6553X_MDIV_MASK;
|
||||
pdiv = (pll0 >> PLL6553X_PDIV_SHIFT) & PLL6553X_PDIV_MASK;
|
||||
sdiv = (pll0 >> PLL6553X_SDIV_SHIFT) & PLL6553X_SDIV_MASK;
|
||||
kdiv = pll1 & PLL6553X_KDIV_MASK;
|
||||
|
||||
/* We need to multiple baseclk by mdiv (the integer part) and kdiv
|
||||
* which is in 2^16ths, so shift mdiv up (does not overflow) and
|
||||
* add kdiv before multiplying. The use of tmp is to avoid any
|
||||
* overflows before shifting bac down into result when multipling
|
||||
* by the mdiv and kdiv pair.
|
||||
*/
|
||||
|
||||
tmp = baseclk;
|
||||
tmp *= (mdiv << 16) + kdiv;
|
||||
do_div(tmp, (pdiv << sdiv));
|
||||
result = tmp >> 16;
|
||||
|
||||
return result;
|
||||
}
|
||||
Loading…
Reference in New Issue