drm/i915: Fix offset page-flips on i965+
i965 uses the Display Registers to compute the offset from the display base so the new base does not need adjusting when flipping. The older chipsets use a fence to access the display and so do perceive the surface as linear and have a single base register which is reprogrammed using the flip. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Reported-by: Marty Jack <martyj19@comcast.net> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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@ -5042,9 +5042,9 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_unpin_work *work;
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unsigned long flags, offset;
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int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
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int ret, pipesrc;
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u32 flip_mask;
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int pipe = intel_crtc->pipe;
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u32 pf, pipesrc;
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int ret;
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work = kzalloc(sizeof *work, GFP_KERNEL);
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if (work == NULL)
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@ -5093,12 +5093,14 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
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atomic_inc(&obj_priv->pending_flip);
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work->pending_flip_obj = obj;
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if (intel_crtc->plane)
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flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
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else
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flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
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if (IS_GEN3(dev) || IS_GEN2(dev)) {
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u32 flip_mask;
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if (intel_crtc->plane)
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flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
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else
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flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
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BEGIN_LP_RING(2);
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OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
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OUT_RING(0);
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@ -5106,29 +5108,56 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
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}
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/* Offset into the new buffer for cases of shared fbs between CRTCs */
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offset = obj_priv->gtt_offset;
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offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
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offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
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BEGIN_LP_RING(4);
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if (IS_I965G(dev)) {
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switch(INTEL_INFO(dev)->gen) {
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case 2:
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OUT_RING(MI_DISPLAY_FLIP |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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OUT_RING(fb->pitch);
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OUT_RING(offset | obj_priv->tiling_mode);
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pipesrc = I915_READ(pipesrc_reg);
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OUT_RING(pipesrc & 0x0fff0fff);
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} else if (IS_GEN3(dev)) {
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OUT_RING(obj_priv->gtt_offset + offset);
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OUT_RING(MI_NOOP);
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break;
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case 3:
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OUT_RING(MI_DISPLAY_FLIP_I915 |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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OUT_RING(fb->pitch);
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OUT_RING(offset);
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OUT_RING(obj_priv->gtt_offset + offset);
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OUT_RING(MI_NOOP);
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} else {
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break;
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case 4:
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case 5:
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/* i965+ uses the linear or tiled offsets from the
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* Display Registers (which do not change across a page-flip)
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* so we need only reprogram the base address.
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*/
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OUT_RING(MI_DISPLAY_FLIP |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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OUT_RING(fb->pitch);
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OUT_RING(offset);
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OUT_RING(MI_NOOP);
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OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
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/* XXX Enabling the panel-fitter across page-flip is so far
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* untested on non-native modes, so ignore it for now.
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* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
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*/
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pf = 0;
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pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
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OUT_RING(pf | pipesrc);
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break;
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case 6:
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OUT_RING(MI_DISPLAY_FLIP |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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OUT_RING(fb->pitch | obj_priv->tiling_mode);
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OUT_RING(obj_priv->gtt_offset);
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pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
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pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
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OUT_RING(pf | pipesrc);
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break;
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}
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ADVANCE_LP_RING();
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