ARM: OMAP2/3: intc: Add DT support for TI interrupt controller
Add a function to initialize the OMAP2/3 interrupt controller (INTC) using a device tree node. This version take advantage of the new irq_domain_add_legacy API. Replace some printk() with the proper pr_ macro. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Grant Likely <grant.likely@secretlab.ca>
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27
Documentation/devicetree/bindings/arm/omap/intc.txt
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27
Documentation/devicetree/bindings/arm/omap/intc.txt
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@ -0,0 +1,27 @@
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* OMAP Interrupt Controller
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OMAP2/3 are using a TI interrupt controller that can support several
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configurable number of interrupts.
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Main node required properties:
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- compatible : should be:
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"ti,omap2-intc"
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The type shall be a <u32> and the value shall be 1.
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The cell contains the interrupt number in the range [0-128].
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- ti,intc-size: Number of interrupts handled by the interrupt controller.
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- reg: physical base address and size of the intc registers map.
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Example:
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intc: interrupt-controller@1 {
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compatible = "ti,omap2-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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ti,intc-size = <96>;
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reg = <0x48200000 0x1000>;
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};
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@ -174,6 +174,18 @@ void omap3_intc_handle_irq(struct pt_regs *regs);
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extern void __iomem *omap4_get_l2cache_base(void);
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extern void __iomem *omap4_get_l2cache_base(void);
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#endif
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#endif
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struct device_node;
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#ifdef CONFIG_OF
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int __init omap_intc_of_init(struct device_node *node,
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struct device_node *parent);
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#else
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int __init omap_intc_of_init(struct device_node *node,
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struct device_node *parent)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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extern void __iomem *omap4_get_scu_base(void);
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extern void __iomem *omap4_get_scu_base(void);
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#else
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#else
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@ -11,12 +11,16 @@
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* for more details.
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* for more details.
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*/
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*/
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#include <linux/kernel.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <mach/hardware.h>
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#include <asm/exception.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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/* selected INTC register offsets */
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/* selected INTC register offsets */
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@ -57,6 +61,8 @@ static struct omap_irq_bank {
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},
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},
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};
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};
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static struct irq_domain *domain;
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/* Structure to save interrupt controller context */
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/* Structure to save interrupt controller context */
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struct omap3_intc_regs {
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struct omap3_intc_regs {
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u32 sysconfig;
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u32 sysconfig;
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@ -147,17 +153,27 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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}
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}
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static void __init omap_init_irq(u32 base, int nr_irqs)
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static void __init omap_init_irq(u32 base, int nr_irqs,
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struct device_node *node)
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{
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{
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void __iomem *omap_irq_base;
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void __iomem *omap_irq_base;
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unsigned long nr_of_irqs = 0;
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unsigned long nr_of_irqs = 0;
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unsigned int nr_banks = 0;
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unsigned int nr_banks = 0;
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int i, j;
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int i, j, irq_base;
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omap_irq_base = ioremap(base, SZ_4K);
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omap_irq_base = ioremap(base, SZ_4K);
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if (WARN_ON(!omap_irq_base))
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if (WARN_ON(!omap_irq_base))
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return;
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return;
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irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
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if (irq_base < 0) {
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pr_warn("Couldn't allocate IRQ numbers\n");
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irq_base = 0;
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}
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domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
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&irq_domain_simple_ops, NULL);
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for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
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for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
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struct omap_irq_bank *bank = irq_banks + i;
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struct omap_irq_bank *bank = irq_banks + i;
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@ -166,36 +182,36 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
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/* Static mapping, never released */
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/* Static mapping, never released */
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bank->base_reg = ioremap(base, SZ_4K);
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bank->base_reg = ioremap(base, SZ_4K);
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if (!bank->base_reg) {
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if (!bank->base_reg) {
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printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
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pr_err("Could not ioremap irq bank%i\n", i);
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continue;
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continue;
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}
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}
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omap_irq_bank_init_one(bank);
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omap_irq_bank_init_one(bank);
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for (j = 0; j < bank->nr_irqs; j += 32)
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for (j = 0; j < bank->nr_irqs; j += 32)
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omap_alloc_gc(bank->base_reg + j, j, 32);
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omap_alloc_gc(bank->base_reg + j, j + irq_base, 32);
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nr_of_irqs += bank->nr_irqs;
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nr_of_irqs += bank->nr_irqs;
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nr_banks++;
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nr_banks++;
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}
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}
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printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
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pr_info("Total of %ld interrupts on %d active controller%s\n",
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nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
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nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
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}
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}
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void __init omap2_init_irq(void)
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void __init omap2_init_irq(void)
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{
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{
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omap_init_irq(OMAP24XX_IC_BASE, 96);
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omap_init_irq(OMAP24XX_IC_BASE, 96, NULL);
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}
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}
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void __init omap3_init_irq(void)
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void __init omap3_init_irq(void)
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{
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{
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omap_init_irq(OMAP34XX_IC_BASE, 96);
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omap_init_irq(OMAP34XX_IC_BASE, 96, NULL);
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}
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}
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void __init ti81xx_init_irq(void)
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void __init ti81xx_init_irq(void)
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{
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{
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omap_init_irq(OMAP34XX_IC_BASE, 128);
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omap_init_irq(OMAP34XX_IC_BASE, 128, NULL);
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}
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}
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static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
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static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
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@ -225,8 +241,10 @@ out:
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irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
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irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
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irqnr &= ACTIVEIRQ_MASK;
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irqnr &= ACTIVEIRQ_MASK;
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if (irqnr)
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if (irqnr) {
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irqnr = irq_find_mapping(domain, irqnr);
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handle_IRQ(irqnr, regs);
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handle_IRQ(irqnr, regs);
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}
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} while (irqnr);
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} while (irqnr);
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}
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}
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@ -236,6 +254,28 @@ asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs
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omap_intc_handle_irq(base_addr, regs);
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omap_intc_handle_irq(base_addr, regs);
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}
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}
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int __init omap_intc_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct resource res;
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u32 nr_irqs = 96;
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if (WARN_ON(!node))
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return -ENODEV;
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if (of_address_to_resource(node, 0, &res)) {
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WARN(1, "unable to get intc registers\n");
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return -EINVAL;
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}
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if (of_property_read_u32(node, "ti,intc-size", &nr_irqs))
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pr_warn("unable to get intc-size, default to %d\n", nr_irqs);
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omap_init_irq(res.start, nr_irqs, of_node_get(node));
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return 0;
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}
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#ifdef CONFIG_ARCH_OMAP3
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#ifdef CONFIG_ARCH_OMAP3
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static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
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static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
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