drm/i915/gen9: Clear residual context state on context switch
commit bc8a76a152
upstream.
Intel ID: PSIRT-TA-201910-001
CVEID: CVE-2019-14615
Intel GPU Hardware prior to Gen11 does not clear EU state
during a context switch. This can result in information
leakage between contexts.
For Gen8 and Gen9, hardware provides a mechanism for
fast cleardown of the EU state, by issuing a PIPE_CONTROL
with bit 27 set. We can use this in a context batch buffer
to explicitly cleardown the state on every context switch.
As this workaround is already in place for gen8, we can borrow
the code verbatim for Gen9.
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Cc: Kumar Valsan Prathap <prathap.kumar.valsan@intel.com>
Cc: Chris Wilson <chris.p.wilson@intel.com>
Cc: Balestrieri Francesco <francesco.balestrieri@intel.com>
Cc: Bloomfield Jon <jon.bloomfield@intel.com>
Cc: Dutt Sudeep <sudeep.dutt@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
5.4-rM2-2.2.x-imx-squashed
parent
f58642c1bc
commit
53b9bd37af
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@ -2132,6 +2132,14 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
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/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
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batch = gen8_emit_flush_coherentl3_wa(engine, batch);
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/* WaClearSlmSpaceAtContextSwitch:skl,bxt,kbl,glk,cfl */
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batch = gen8_emit_pipe_control(batch,
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PIPE_CONTROL_FLUSH_L3 |
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PIPE_CONTROL_GLOBAL_GTT_IVB |
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PIPE_CONTROL_CS_STALL |
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PIPE_CONTROL_QW_WRITE,
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slm_offset(engine));
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batch = emit_lri(batch, lri, ARRAY_SIZE(lri));
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/* WaMediaPoolStateCmdInWABB:bxt,glk */
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