[MIPS] Au1xx0 code sets incorrect mips_hpt_frequency
Alchemy CPU counter ticks at the full CPU clock speed. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -231,7 +231,6 @@ wakeup_counter0_set(int ticks)
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*/
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*/
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unsigned long cal_r4koff(void)
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unsigned long cal_r4koff(void)
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{
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{
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unsigned long count;
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unsigned long cpu_speed;
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unsigned long cpu_speed;
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unsigned long flags;
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unsigned long flags;
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unsigned long counter;
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unsigned long counter;
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@ -258,7 +257,7 @@ unsigned long cal_r4koff(void)
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#if defined(CONFIG_AU1000_USE32K)
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#if defined(CONFIG_AU1000_USE32K)
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{
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{
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unsigned long start, end;
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unsigned long start, end, count;
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start = au_readl(SYS_RTCREAD);
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start = au_readl(SYS_RTCREAD);
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start += 2;
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start += 2;
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@ -282,7 +281,6 @@ unsigned long cal_r4koff(void)
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#else
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#else
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cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
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cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
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AU1000_SRC_CLK;
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AU1000_SRC_CLK;
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count = cpu_speed / 2;
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#endif
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#endif
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}
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}
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else {
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else {
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@ -291,10 +289,9 @@ unsigned long cal_r4koff(void)
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* NOTE: some old silicon doesn't allow reading the PLL.
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* NOTE: some old silicon doesn't allow reading the PLL.
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*/
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*/
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cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
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cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
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count = cpu_speed / 2;
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no_au1xxx_32khz = 1;
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no_au1xxx_32khz = 1;
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}
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}
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mips_hpt_frequency = count;
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mips_hpt_frequency = cpu_speed;
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// Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
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// Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
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set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
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set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
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spin_unlock_irqrestore(&time_lock, flags);
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spin_unlock_irqrestore(&time_lock, flags);
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