Merge branches 'clk-actions', 'clk-rockchip', 'clk-iproc', 'clk-intel' and 'clk-debugfs' into clk-next
- RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs * clk-actions: MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs clk: actions: Add Actions S500 SoC Reset Management Unit support dt-bindings: reset: Add binding constants for Actions S500 RMU clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoC clk: actions: Fix h_clk for Actions S500 SoC * clk-rockchip: clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocks clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328" clk: rockchip: use separate compatibles for rk3288w-cru dt-bindings: clocks: add rk3288w variant compatible clk: rockchip: Handle clock tree for rk3288w variant clk: rockchip: convert rk3036 pll type to use internal lock status clk: rockchip: convert basic pll lock_wait to use regmap_read_poll_timeout clk: rockchip: convert rk3399 pll type to use readl_relaxed_poll_timeout * clk-iproc: clk: iproc: round clock rate to the closest * clk-intel: clk: intel: Avoid unnecessary memset by improving code clk: intel: Improve locking in the driver clk: intel: Use devm_clk_hw_register() instead of clk_hw_register() * clk-debugfs: clk: Add support for enabling/disabling clocks from debugfs
This commit is contained in:
Stephen Boyd
commit
53e07424ec
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@ -4,9 +4,15 @@ The RK3288 clock controller generates and supplies clock to various
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controllers within the SoC and also implements a reset controller for SoC
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peripherals.
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A revision of this SoC is available: rk3288w. The clock tree is a bit
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different so another dt-compatible is available. Noticed that it is only
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setting the difference but there is no automatic revision detection. This
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should be performed by bootloaders.
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Required Properties:
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- compatible: should be "rockchip,rk3288-cru"
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- compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in
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case of this revision of Rockchip rk3288.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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@ -1533,6 +1533,7 @@ F: drivers/mmc/host/owl-mmc.c
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F: drivers/pinctrl/actions/*
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F: drivers/soc/actions/
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F: include/dt-bindings/power/owl-*
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F: include/dt-bindings/reset/actions,*
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F: include/linux/soc/actions/
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N: owl
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@ -23,8 +23,10 @@
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#include "owl-gate.h"
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#include "owl-mux.h"
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#include "owl-pll.h"
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#include "owl-reset.h"
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#include <dt-bindings/clock/actions,s500-cmu.h>
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#include <dt-bindings/reset/actions,s500-reset.h>
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#define CMU_COREPLL (0x0000)
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#define CMU_DEVPLL (0x0004)
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@ -175,6 +177,8 @@ static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RAT
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static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
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/* gate clocks */
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static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
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static OWL_GATE(dmac_clk, "dmac_clk", "h_clk", CMU_DEVCLKEN0, 1, 0, 0);
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static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
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static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
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static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
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@ -183,7 +187,8 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
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static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
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/* divider clocks */
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static OWL_DIVIDER(h_clk, "h_clk", "ahbprevdiv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
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static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
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static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
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static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
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/* factor clocks */
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@ -428,6 +433,9 @@ static struct owl_clk_common *s500_clks[] = {
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&spdif_clk.common,
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&nand_clk.common,
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&ecc_clk.common,
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&apb_clk.common,
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&dmac_clk.common,
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&gpio_clk.common,
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};
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static struct clk_hw_onecell_data s500_hw_clks = {
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@ -484,24 +492,103 @@ static struct clk_hw_onecell_data s500_hw_clks = {
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[CLK_SPDIF] = &spdif_clk.common.hw,
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[CLK_NAND] = &nand_clk.common.hw,
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[CLK_ECC] = &ecc_clk.common.hw,
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[CLK_APB] = &apb_clk.common.hw,
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[CLK_DMAC] = &dmac_clk.common.hw,
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[CLK_GPIO] = &gpio_clk.common.hw,
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},
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.num = CLK_NR_CLKS,
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};
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static const struct owl_reset_map s500_resets[] = {
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[RESET_DMAC] = { CMU_DEVRST0, BIT(0) },
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[RESET_NORIF] = { CMU_DEVRST0, BIT(1) },
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[RESET_DDR] = { CMU_DEVRST0, BIT(2) },
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[RESET_NANDC] = { CMU_DEVRST0, BIT(3) },
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[RESET_SD0] = { CMU_DEVRST0, BIT(4) },
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[RESET_SD1] = { CMU_DEVRST0, BIT(5) },
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[RESET_PCM1] = { CMU_DEVRST0, BIT(6) },
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[RESET_DE] = { CMU_DEVRST0, BIT(7) },
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[RESET_LCD] = { CMU_DEVRST0, BIT(8) },
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[RESET_SD2] = { CMU_DEVRST0, BIT(9) },
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[RESET_DSI] = { CMU_DEVRST0, BIT(10) },
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[RESET_CSI] = { CMU_DEVRST0, BIT(11) },
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[RESET_BISP] = { CMU_DEVRST0, BIT(12) },
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[RESET_KEY] = { CMU_DEVRST0, BIT(14) },
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[RESET_GPIO] = { CMU_DEVRST0, BIT(15) },
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[RESET_AUDIO] = { CMU_DEVRST0, BIT(17) },
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[RESET_PCM0] = { CMU_DEVRST0, BIT(18) },
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[RESET_VDE] = { CMU_DEVRST0, BIT(19) },
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[RESET_VCE] = { CMU_DEVRST0, BIT(20) },
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[RESET_GPU3D] = { CMU_DEVRST0, BIT(22) },
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[RESET_NIC301] = { CMU_DEVRST0, BIT(23) },
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[RESET_LENS] = { CMU_DEVRST0, BIT(26) },
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[RESET_PERIPHRESET] = { CMU_DEVRST0, BIT(27) },
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[RESET_USB2_0] = { CMU_DEVRST1, BIT(0) },
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[RESET_TVOUT] = { CMU_DEVRST1, BIT(1) },
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[RESET_HDMI] = { CMU_DEVRST1, BIT(2) },
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[RESET_HDCP2TX] = { CMU_DEVRST1, BIT(3) },
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[RESET_UART6] = { CMU_DEVRST1, BIT(4) },
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[RESET_UART0] = { CMU_DEVRST1, BIT(5) },
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[RESET_UART1] = { CMU_DEVRST1, BIT(6) },
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[RESET_UART2] = { CMU_DEVRST1, BIT(7) },
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[RESET_SPI0] = { CMU_DEVRST1, BIT(8) },
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[RESET_SPI1] = { CMU_DEVRST1, BIT(9) },
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[RESET_SPI2] = { CMU_DEVRST1, BIT(10) },
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[RESET_SPI3] = { CMU_DEVRST1, BIT(11) },
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[RESET_I2C0] = { CMU_DEVRST1, BIT(12) },
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[RESET_I2C1] = { CMU_DEVRST1, BIT(13) },
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[RESET_USB3] = { CMU_DEVRST1, BIT(14) },
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[RESET_UART3] = { CMU_DEVRST1, BIT(15) },
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[RESET_UART4] = { CMU_DEVRST1, BIT(16) },
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[RESET_UART5] = { CMU_DEVRST1, BIT(17) },
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[RESET_I2C2] = { CMU_DEVRST1, BIT(18) },
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[RESET_I2C3] = { CMU_DEVRST1, BIT(19) },
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[RESET_ETHERNET] = { CMU_DEVRST1, BIT(20) },
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[RESET_CHIPID] = { CMU_DEVRST1, BIT(21) },
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[RESET_USB2_1] = { CMU_DEVRST1, BIT(22) },
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[RESET_WD0RESET] = { CMU_DEVRST1, BIT(24) },
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[RESET_WD1RESET] = { CMU_DEVRST1, BIT(25) },
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[RESET_WD2RESET] = { CMU_DEVRST1, BIT(26) },
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[RESET_WD3RESET] = { CMU_DEVRST1, BIT(27) },
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[RESET_DBG0RESET] = { CMU_DEVRST1, BIT(28) },
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[RESET_DBG1RESET] = { CMU_DEVRST1, BIT(29) },
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[RESET_DBG2RESET] = { CMU_DEVRST1, BIT(30) },
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[RESET_DBG3RESET] = { CMU_DEVRST1, BIT(31) },
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};
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static struct owl_clk_desc s500_clk_desc = {
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.clks = s500_clks,
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.num_clks = ARRAY_SIZE(s500_clks),
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.hw_clks = &s500_hw_clks,
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.resets = s500_resets,
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.num_resets = ARRAY_SIZE(s500_resets),
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};
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static int s500_clk_probe(struct platform_device *pdev)
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{
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struct owl_clk_desc *desc;
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struct owl_reset *reset;
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int ret;
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desc = &s500_clk_desc;
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owl_clk_regmap_init(pdev, desc);
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reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
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if (!reset)
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return -ENOMEM;
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reset->rcdev.of_node = pdev->dev.of_node;
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reset->rcdev.ops = &owl_reset_ops;
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reset->rcdev.nr_resets = desc->num_resets;
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reset->reset_map = desc->resets;
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reset->regmap = desc->regmap;
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ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
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if (ret)
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dev_err(&pdev->dev, "Failed to register reset controller\n");
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return owl_clk_probe(&pdev->dev, desc->hw_clks);
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}
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@ -119,7 +119,7 @@ static long iproc_asiu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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if (rate == *parent_rate)
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return *parent_rate;
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div = DIV_ROUND_UP(*parent_rate, rate);
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div = DIV_ROUND_CLOSEST(*parent_rate, rate);
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if (div < 2)
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return *parent_rate;
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@ -145,7 +145,7 @@ static int iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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return 0;
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}
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div = DIV_ROUND_UP(parent_rate, rate);
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div = DIV_ROUND_CLOSEST(parent_rate, rate);
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if (div < 2)
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return -EINVAL;
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@ -3054,6 +3054,31 @@ static int clk_rate_set(void *data, u64 val)
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}
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#define clk_rate_mode 0644
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static int clk_prepare_enable_set(void *data, u64 val)
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{
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struct clk_core *core = data;
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int ret = 0;
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if (val)
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ret = clk_prepare_enable(core->hw->clk);
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else
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clk_disable_unprepare(core->hw->clk);
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return ret;
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}
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static int clk_prepare_enable_get(void *data, u64 *val)
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{
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struct clk_core *core = data;
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*val = core->enable_count && core->prepare_count;
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return 0;
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}
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DEFINE_DEBUGFS_ATTRIBUTE(clk_prepare_enable_fops, clk_prepare_enable_get,
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clk_prepare_enable_set, "%llu\n");
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#else
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#define clk_rate_set NULL
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#define clk_rate_mode 0444
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@ -3231,6 +3256,10 @@ static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
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debugfs_create_u32("clk_notifier_count", 0444, root, &core->notifier_count);
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debugfs_create_file("clk_duty_cycle", 0444, root, core,
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&clk_duty_cycle_fops);
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#ifdef CLOCK_ALLOW_WRITE_DEBUGFS
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debugfs_create_file("clk_prepare_enable", 0644, root, core,
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&clk_prepare_enable_fops);
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#endif
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if (core->num_parents > 0)
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debugfs_create_file("clk_parent", 0444, root, core,
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@ -12,6 +12,7 @@
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/clk-provider.h>
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#include <linux/iopoll.h>
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#include <linux/regmap.h>
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#include <linux/clk.h>
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#include "clk.h"
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@ -86,23 +87,14 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
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{
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struct regmap *grf = pll->ctx->grf;
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unsigned int val;
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int delay = 24000000, ret;
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int ret;
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while (delay > 0) {
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ret = regmap_read(grf, pll->lock_offset, &val);
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if (ret) {
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pr_err("%s: failed to read pll lock status: %d\n",
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__func__, ret);
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return ret;
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}
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ret = regmap_read_poll_timeout(grf, pll->lock_offset, val,
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val & BIT(pll->lock_shift), 0, 1000);
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if (ret)
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pr_err("%s: timeout waiting for pll to lock\n", __func__);
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if (val & BIT(pll->lock_shift))
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return 0;
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delay--;
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}
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pr_err("%s: timeout waiting for pll to lock\n", __func__);
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return -ETIMEDOUT;
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return ret;
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}
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/**
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@ -118,12 +110,31 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
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#define RK3036_PLLCON1_REFDIV_SHIFT 0
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#define RK3036_PLLCON1_POSTDIV2_MASK 0x7
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#define RK3036_PLLCON1_POSTDIV2_SHIFT 6
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#define RK3036_PLLCON1_LOCK_STATUS BIT(10)
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#define RK3036_PLLCON1_DSMPD_MASK 0x1
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#define RK3036_PLLCON1_DSMPD_SHIFT 12
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#define RK3036_PLLCON1_PWRDOWN BIT(13)
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#define RK3036_PLLCON2_FRAC_MASK 0xffffff
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#define RK3036_PLLCON2_FRAC_SHIFT 0
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#define RK3036_PLLCON1_PWRDOWN (1 << 13)
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static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll)
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{
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u32 pllcon;
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int ret;
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/*
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* Lock time typical 250, max 500 input clock cycles @24MHz
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* So define a very safe maximum of 1000us, meaning 24000 cycles.
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*/
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ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1),
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pllcon,
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pllcon & RK3036_PLLCON1_LOCK_STATUS,
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0, 1000);
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if (ret)
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pr_err("%s: timeout waiting for pll to lock\n", __func__);
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return ret;
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}
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static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
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struct rockchip_pll_rate_table *rate)
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@ -221,7 +232,7 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
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writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
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/* wait for the pll to lock */
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ret = rockchip_pll_wait_lock(pll);
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ret = rockchip_rk3036_pll_wait_lock(pll);
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if (ret) {
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pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
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__func__);
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@ -260,7 +271,7 @@ static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
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writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
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pll->reg_base + RK3036_PLLCON(1));
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rockchip_pll_wait_lock(pll);
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rockchip_rk3036_pll_wait_lock(pll);
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return 0;
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}
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@ -589,19 +600,20 @@ static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
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static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll)
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{
|
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u32 pllcon;
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int delay = 24000000;
|
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int ret;
|
||||
|
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/* poll check the lock status in rk3399 xPLLCON2 */
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while (delay > 0) {
|
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pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
|
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if (pllcon & RK3399_PLLCON2_LOCK_STATUS)
|
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return 0;
|
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/*
|
||||
* Lock time typical 250, max 500 input clock cycles @24MHz
|
||||
* So define a very safe maximum of 1000us, meaning 24000 cycles.
|
||||
*/
|
||||
ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2),
|
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pllcon,
|
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pllcon & RK3399_PLLCON2_LOCK_STATUS,
|
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0, 1000);
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if (ret)
|
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pr_err("%s: timeout waiting for pll to lock\n", __func__);
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delay--;
|
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}
|
||||
|
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pr_err("%s: timeout waiting for pll to lock\n", __func__);
|
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return -ETIMEDOUT;
|
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return ret;
|
||||
}
|
||||
|
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static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll,
|
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|
|
@ -751,6 +751,7 @@ static const char *const rk3188_critical_clocks[] __initconst = {
|
|||
"pclk_peri",
|
||||
"hclk_cpubus",
|
||||
"hclk_vio_bus",
|
||||
"sclk_mac_lbtest",
|
||||
};
|
||||
|
||||
static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)
|
||||
|
|
|
|||
|
|
@ -15,6 +15,11 @@
|
|||
#define RK3288_GRF_SOC_CON(x) (0x244 + x * 4)
|
||||
#define RK3288_GRF_SOC_STATUS1 0x284
|
||||
|
||||
enum rk3288_variant {
|
||||
RK3288_CRU,
|
||||
RK3288W_CRU,
|
||||
};
|
||||
|
||||
enum rk3288_plls {
|
||||
apll, dpll, cpll, gpll, npll,
|
||||
};
|
||||
|
|
@ -425,8 +430,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
|
|||
COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
|
||||
RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3288_CLKGATE_CON(3), 0, GFLAGS),
|
||||
DIV(0, "hclk_vio", "aclk_vio0", 0,
|
||||
RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
|
||||
COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
|
||||
RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
|
||||
RK3288_CLKGATE_CON(3), 2, GFLAGS),
|
||||
|
|
@ -819,6 +822,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
|
|||
INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
|
||||
};
|
||||
|
||||
static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
|
||||
DIV(0, "hclk_vio", "aclk_vio1", 0,
|
||||
RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
|
||||
};
|
||||
|
||||
static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
|
||||
DIV(0, "hclk_vio", "aclk_vio0", 0,
|
||||
RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
|
||||
};
|
||||
|
||||
static const char *const rk3288_critical_clocks[] __initconst = {
|
||||
"aclk_cpu",
|
||||
"aclk_peri",
|
||||
|
|
@ -914,7 +927,8 @@ static struct syscore_ops rk3288_clk_syscore_ops = {
|
|||
.resume = rk3288_clk_resume,
|
||||
};
|
||||
|
||||
static void __init rk3288_clk_init(struct device_node *np)
|
||||
static void __init rk3288_common_init(struct device_node *np,
|
||||
enum rk3288_variant soc)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
|
||||
|
|
@ -936,6 +950,14 @@ static void __init rk3288_clk_init(struct device_node *np)
|
|||
RK3288_GRF_SOC_STATUS1);
|
||||
rockchip_clk_register_branches(ctx, rk3288_clk_branches,
|
||||
ARRAY_SIZE(rk3288_clk_branches));
|
||||
|
||||
if (soc == RK3288W_CRU)
|
||||
rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
|
||||
ARRAY_SIZE(rk3288w_hclkvio_branch));
|
||||
else
|
||||
rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
|
||||
ARRAY_SIZE(rk3288_hclkvio_branch));
|
||||
|
||||
rockchip_clk_protect_critical(rk3288_critical_clocks,
|
||||
ARRAY_SIZE(rk3288_critical_clocks));
|
||||
|
||||
|
|
@ -954,4 +976,15 @@ static void __init rk3288_clk_init(struct device_node *np)
|
|||
|
||||
rockchip_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
|
||||
static void __init rk3288_clk_init(struct device_node *np)
|
||||
{
|
||||
rk3288_common_init(np, RK3288_CRU);
|
||||
}
|
||||
CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
|
||||
|
||||
static void __init rk3288w_clk_init(struct device_node *np)
|
||||
{
|
||||
rk3288_common_init(np, RK3288W_CRU);
|
||||
}
|
||||
CLK_OF_DECLARE(rk3288w_cru, "rockchip,rk3288w-cru", rk3288w_clk_init);
|
||||
|
|
|
|||
|
|
@ -808,22 +808,22 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
|
|||
MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
|
||||
RK3328_SDMMC_CON0, 1),
|
||||
MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc",
|
||||
RK3328_SDMMC_CON1, 0),
|
||||
RK3328_SDMMC_CON1, 1),
|
||||
|
||||
MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio",
|
||||
RK3328_SDIO_CON0, 1),
|
||||
MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio",
|
||||
RK3328_SDIO_CON1, 0),
|
||||
RK3328_SDIO_CON1, 1),
|
||||
|
||||
MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc",
|
||||
RK3328_EMMC_CON0, 1),
|
||||
MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc",
|
||||
RK3328_EMMC_CON1, 0),
|
||||
RK3328_EMMC_CON1, 1),
|
||||
|
||||
MMC(SCLK_SDMMC_EXT_DRV, "sdmmc_ext_drv", "clk_sdmmc_ext",
|
||||
RK3328_SDMMC_EXT_CON0, 1),
|
||||
MMC(SCLK_SDMMC_EXT_SAMPLE, "sdmmc_ext_sample", "clk_sdmmc_ext",
|
||||
RK3328_SDMMC_EXT_CON1, 0),
|
||||
RK3328_SDMMC_EXT_CON1, 1),
|
||||
};
|
||||
|
||||
static const char *const rk3328_critical_clocks[] __initconst = {
|
||||
|
|
|
|||
|
|
@ -128,7 +128,7 @@ lgm_clk_register_pll(struct lgm_clk_provider *ctx,
|
|||
pll->hw.init = &init;
|
||||
|
||||
hw = &pll->hw;
|
||||
ret = clk_hw_register(dev, hw);
|
||||
ret = devm_clk_hw_register(dev, hw);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
|
|
|
|||
|
|
@ -119,7 +119,7 @@ lgm_clk_register_mux(struct lgm_clk_provider *ctx,
|
|||
mux->hw.init = &init;
|
||||
|
||||
hw = &mux->hw;
|
||||
ret = clk_hw_register(dev, hw);
|
||||
ret = devm_clk_hw_register(dev, hw);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
|
|
@ -247,7 +247,7 @@ lgm_clk_register_divider(struct lgm_clk_provider *ctx,
|
|||
div->hw.init = &init;
|
||||
|
||||
hw = &div->hw;
|
||||
ret = clk_hw_register(dev, hw);
|
||||
ret = devm_clk_hw_register(dev, hw);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
|
|
@ -361,7 +361,7 @@ lgm_clk_register_gate(struct lgm_clk_provider *ctx,
|
|||
gate->hw.init = &init;
|
||||
|
||||
hw = &gate->hw;
|
||||
ret = clk_hw_register(dev, hw);
|
||||
ret = devm_clk_hw_register(dev, hw);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
|
|
@ -420,18 +420,14 @@ lgm_clk_ddiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
|||
{
|
||||
struct lgm_clk_ddiv *ddiv = to_lgm_clk_ddiv(hw);
|
||||
unsigned int div0, div1, exdiv;
|
||||
unsigned long flags;
|
||||
u64 prate;
|
||||
|
||||
spin_lock_irqsave(&ddiv->lock, flags);
|
||||
div0 = lgm_get_clk_val(ddiv->membase, ddiv->reg,
|
||||
ddiv->shift0, ddiv->width0) + 1;
|
||||
div1 = lgm_get_clk_val(ddiv->membase, ddiv->reg,
|
||||
ddiv->shift1, ddiv->width1) + 1;
|
||||
exdiv = lgm_get_clk_val(ddiv->membase, ddiv->reg,
|
||||
ddiv->shift2, ddiv->width2);
|
||||
spin_unlock_irqrestore(&ddiv->lock, flags);
|
||||
|
||||
prate = (u64)parent_rate;
|
||||
do_div(prate, div0);
|
||||
do_div(prate, div1);
|
||||
|
|
@ -548,24 +544,21 @@ lgm_clk_ddiv_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
div = div * 2;
|
||||
div = DIV_ROUND_CLOSEST_ULL((u64)div, 5);
|
||||
}
|
||||
spin_unlock_irqrestore(&ddiv->lock, flags);
|
||||
|
||||
if (div <= 0) {
|
||||
spin_unlock_irqrestore(&ddiv->lock, flags);
|
||||
if (div <= 0)
|
||||
return *prate;
|
||||
}
|
||||
|
||||
if (lgm_clk_get_ddiv_val(div, &ddiv1, &ddiv2) != 0) {
|
||||
if (lgm_clk_get_ddiv_val(div + 1, &ddiv1, &ddiv2) != 0) {
|
||||
spin_unlock_irqrestore(&ddiv->lock, flags);
|
||||
if (lgm_clk_get_ddiv_val(div, &ddiv1, &ddiv2) != 0)
|
||||
if (lgm_clk_get_ddiv_val(div + 1, &ddiv1, &ddiv2) != 0)
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
rate64 = *prate;
|
||||
do_div(rate64, ddiv1);
|
||||
do_div(rate64, ddiv2);
|
||||
|
||||
/* if predivide bit is enabled, modify rounded rate by factor of 2.5 */
|
||||
spin_lock_irqsave(&ddiv->lock, flags);
|
||||
if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) {
|
||||
rate64 = rate64 * 2;
|
||||
rate64 = DIV_ROUND_CLOSEST_ULL(rate64, 5);
|
||||
|
|
@ -588,19 +581,18 @@ int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
|
|||
unsigned int nr_clk)
|
||||
{
|
||||
struct device *dev = ctx->dev;
|
||||
struct clk_init_data init = {};
|
||||
struct lgm_clk_ddiv *ddiv;
|
||||
struct clk_hw *hw;
|
||||
unsigned int idx;
|
||||
int ret;
|
||||
|
||||
for (idx = 0; idx < nr_clk; idx++, list++) {
|
||||
ddiv = NULL;
|
||||
struct clk_init_data init = {};
|
||||
struct lgm_clk_ddiv *ddiv;
|
||||
|
||||
ddiv = devm_kzalloc(dev, sizeof(*ddiv), GFP_KERNEL);
|
||||
if (!ddiv)
|
||||
return -ENOMEM;
|
||||
|
||||
memset(&init, 0, sizeof(init));
|
||||
init.name = list->name;
|
||||
init.ops = &lgm_clk_ddiv_ops;
|
||||
init.flags = list->flags;
|
||||
|
|
@ -624,7 +616,7 @@ int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx,
|
|||
ddiv->hw.init = &init;
|
||||
|
||||
hw = &ddiv->hw;
|
||||
ret = clk_hw_register(dev, hw);
|
||||
ret = devm_clk_hw_register(dev, hw);
|
||||
if (ret) {
|
||||
dev_err(dev, "register clk: %s failed!\n", list->name);
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -72,7 +72,12 @@
|
|||
#define CLK_NAND 52
|
||||
#define CLK_ECC 53
|
||||
#define CLK_RMII_REF 54
|
||||
#define CLK_GPIO 55
|
||||
|
||||
#define CLK_NR_CLKS (CLK_RMII_REF + 1)
|
||||
/* system clock (part 2) */
|
||||
#define CLK_APB 56
|
||||
#define CLK_DMAC 57
|
||||
|
||||
#define CLK_NR_CLKS (CLK_DMAC + 1)
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */
|
||||
|
|
|
|||
67
include/dt-bindings/reset/actions,s500-reset.h
Normal file
67
include/dt-bindings/reset/actions,s500-reset.h
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Device Tree binding constants for Actions Semi S500 Reset Management Unit
|
||||
*
|
||||
* Copyright (c) 2014 Actions Semi Inc.
|
||||
* Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H
|
||||
#define __DT_BINDINGS_ACTIONS_S500_RESET_H
|
||||
|
||||
#define RESET_DMAC 0
|
||||
#define RESET_NORIF 1
|
||||
#define RESET_DDR 2
|
||||
#define RESET_NANDC 3
|
||||
#define RESET_SD0 4
|
||||
#define RESET_SD1 5
|
||||
#define RESET_PCM1 6
|
||||
#define RESET_DE 7
|
||||
#define RESET_LCD 8
|
||||
#define RESET_SD2 9
|
||||
#define RESET_DSI 10
|
||||
#define RESET_CSI 11
|
||||
#define RESET_BISP 12
|
||||
#define RESET_KEY 13
|
||||
#define RESET_GPIO 14
|
||||
#define RESET_AUDIO 15
|
||||
#define RESET_PCM0 16
|
||||
#define RESET_VDE 17
|
||||
#define RESET_VCE 18
|
||||
#define RESET_GPU3D 19
|
||||
#define RESET_NIC301 20
|
||||
#define RESET_LENS 21
|
||||
#define RESET_PERIPHRESET 22
|
||||
#define RESET_USB2_0 23
|
||||
#define RESET_TVOUT 24
|
||||
#define RESET_HDMI 25
|
||||
#define RESET_HDCP2TX 26
|
||||
#define RESET_UART6 27
|
||||
#define RESET_UART0 28
|
||||
#define RESET_UART1 29
|
||||
#define RESET_UART2 30
|
||||
#define RESET_SPI0 31
|
||||
#define RESET_SPI1 32
|
||||
#define RESET_SPI2 33
|
||||
#define RESET_SPI3 34
|
||||
#define RESET_I2C0 35
|
||||
#define RESET_I2C1 36
|
||||
#define RESET_USB3 37
|
||||
#define RESET_UART3 38
|
||||
#define RESET_UART4 39
|
||||
#define RESET_UART5 40
|
||||
#define RESET_I2C2 41
|
||||
#define RESET_I2C3 42
|
||||
#define RESET_ETHERNET 43
|
||||
#define RESET_CHIPID 44
|
||||
#define RESET_USB2_1 45
|
||||
#define RESET_WD0RESET 46
|
||||
#define RESET_WD1RESET 47
|
||||
#define RESET_WD2RESET 48
|
||||
#define RESET_WD3RESET 49
|
||||
#define RESET_DBG0RESET 50
|
||||
#define RESET_DBG1RESET 51
|
||||
#define RESET_DBG2RESET 52
|
||||
#define RESET_DBG3RESET 53
|
||||
|
||||
#endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */
|
||||
Loading…
Reference in a new issue