sh: mach-se: Convert SE7343 FPGA to dynamic IRQ allocation.
This gets rid of the arbitrary set of vectors used by the SE7722 FPGA interrupt controller and switches over to a completely dynamic set. No assumptions regarding a contiguous range are made, and the platform resources themselves need to be filled in lazily. Signed-off-by: Paul Mundt <lethal@linux-sh.org>hifive-unleashed-5.1
Paul Mundt
parent
8c0b8139c8
commit
53e6d8e006
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@ -16,15 +16,17 @@
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#include <linux/io.h>
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#include <mach-se/mach/se7343.h>
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unsigned int se7343_fpga_irq[SE7343_FPGA_IRQ_NR] = { 0, };
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static void disable_se7343_irq(unsigned int irq)
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{
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unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
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unsigned int bit = (unsigned int)get_irq_chip_data(irq);
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ctrl_outw(ctrl_inw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
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}
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static void enable_se7343_irq(unsigned int irq)
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{
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unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
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unsigned int bit = (unsigned int)get_irq_chip_data(irq);
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ctrl_outw(ctrl_inw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
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}
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@ -38,18 +40,15 @@ static struct irq_chip se7343_irq_chip __read_mostly = {
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static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
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{
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unsigned short intv = ctrl_inw(PA_CPLD_ST);
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struct irq_desc *ext_desc;
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unsigned int ext_irq = SE7343_FPGA_IRQ_BASE;
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unsigned int ext_irq = 0;
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intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;
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while (intv) {
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if (intv & 1) {
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ext_desc = irq_desc + ext_irq;
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handle_level_irq(ext_irq, ext_desc);
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}
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intv >>= 1;
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ext_irq++;
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for (; intv; intv >>= 1, ext_irq++) {
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if (!(intv & 1))
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continue;
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generic_handle_irq(se7343_fpga_irq[ext_irq]);
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}
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}
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@ -58,16 +57,24 @@ static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
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*/
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void __init init_7343se_IRQ(void)
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{
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int i;
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int i, irq;
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ctrl_outw(0, PA_CPLD_IMSK); /* disable all irqs */
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ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */
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for (i = 0; i < SE7343_FPGA_IRQ_NR; i++)
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set_irq_chip_and_handler_name(SE7343_FPGA_IRQ_BASE + i,
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for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
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irq = create_irq();
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if (irq < 0)
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return;
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se7343_fpga_irq[i] = irq;
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set_irq_chip_and_handler_name(se7343_fpga_irq[i],
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&se7343_irq_chip,
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handle_level_irq, "level");
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set_irq_chip_data(se7343_fpga_irq[i], (void *)i);
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}
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set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux);
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set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
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set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux);
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@ -82,7 +82,6 @@ static struct plat_serial8250_port serial_platform_data[] = {
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.mapbase = 0x16000000,
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.regshift = 1,
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.flags = ST16C2550C_FLAGS,
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.irq = UARTA_IRQ,
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.uartclk = 7372800,
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},
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[1] = {
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@ -90,7 +89,6 @@ static struct plat_serial8250_port serial_platform_data[] = {
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.mapbase = 0x17000000,
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.regshift = 1,
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.flags = ST16C2550C_FLAGS,
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.irq = UARTB_IRQ,
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.uartclk = 7372800,
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},
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{ },
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@ -121,7 +119,7 @@ static struct resource usb_resources[] = {
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.flags = IORESOURCE_MEM,
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},
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[2] = {
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.start = USB_IRQ,
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/* Filled in later */
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.flags = IORESOURCE_IRQ,
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},
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};
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@ -138,8 +136,8 @@ static struct isp116x_platform_data usb_platform_data = {
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static struct platform_device usb_device = {
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.name = "isp116x-hcd",
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.id = -1,
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.num_resources = ARRAY_SIZE(usb_resources),
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.resource = usb_resources,
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.num_resources = ARRAY_SIZE(usb_resources),
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.resource = usb_resources,
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.dev = {
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.platform_data = &usb_platform_data,
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},
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@ -155,6 +153,13 @@ static struct platform_device *sh7343se_platform_devices[] __initdata = {
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static int __init sh7343se_devices_setup(void)
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{
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/* Wire-up dynamic vectors */
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serial_platform_data[0].irq = se7343_fpga_irq[SE7343_FPGA_IRQ_UARTA];
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serial_platform_data[1].irq = se7343_fpga_irq[SE7343_FPGA_IRQ_UARTB];
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usb_resources[2].start = usb_resources[2].end =
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se7343_fpga_irq[SE7343_FPGA_IRQ_USB];
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return platform_add_devices(sh7343se_platform_devices,
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ARRAY_SIZE(sh7343se_platform_devices));
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}
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@ -179,6 +184,5 @@ static void __init sh7343se_setup(char **cmdline_p)
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static struct sh_machine_vector mv_7343se __initmv = {
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.mv_name = "SolutionEngine 7343",
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.mv_setup = sh7343se_setup,
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.mv_nr_irqs = SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_NR,
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.mv_init_irq = init_7343se_IRQ,
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};
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@ -94,26 +94,26 @@
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#define PORT_DRVCR 0xA4050180
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#define PORT_PADR 0xA4050120
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#define PORT_PBDR 0xA4050122
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#define PORT_PCDR 0xA4050124
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#define PORT_PDDR 0xA4050126
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#define PORT_PEDR 0xA4050128
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#define PORT_PFDR 0xA405012A
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#define PORT_PGDR 0xA405012C
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#define PORT_PHDR 0xA405012E
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#define PORT_PJDR 0xA4050130
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#define PORT_PKDR 0xA4050132
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#define PORT_PLDR 0xA4050134
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#define PORT_PMDR 0xA4050136
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#define PORT_PNDR 0xA4050138
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#define PORT_PQDR 0xA405013A
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#define PORT_PRDR 0xA405013C
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#define PORT_PTDR 0xA4050160
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#define PORT_PUDR 0xA4050162
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#define PORT_PVDR 0xA4050164
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#define PORT_PWDR 0xA4050166
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#define PORT_PYDR 0xA4050168
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#define PORT_PADR 0xA4050120
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#define PORT_PBDR 0xA4050122
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#define PORT_PCDR 0xA4050124
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#define PORT_PDDR 0xA4050126
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#define PORT_PEDR 0xA4050128
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#define PORT_PFDR 0xA405012A
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#define PORT_PGDR 0xA405012C
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#define PORT_PHDR 0xA405012E
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#define PORT_PJDR 0xA4050130
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#define PORT_PKDR 0xA4050132
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#define PORT_PLDR 0xA4050134
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#define PORT_PMDR 0xA4050136
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#define PORT_PNDR 0xA4050138
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#define PORT_PQDR 0xA405013A
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#define PORT_PRDR 0xA405013C
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#define PORT_PTDR 0xA4050160
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#define PORT_PUDR 0xA4050162
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#define PORT_PVDR 0xA4050164
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#define PORT_PWDR 0xA4050166
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#define PORT_PYDR 0xA4050168
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#define FPGA_IN 0xb1400000
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#define FPGA_OUT 0xb1400002
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@ -133,18 +133,10 @@
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#define SE7343_FPGA_IRQ_UARTB 11
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#define SE7343_FPGA_IRQ_NR 12
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#define SE7343_FPGA_IRQ_BASE 120
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#define MRSHPC_IRQ3 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC3)
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#define MRSHPC_IRQ2 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC2)
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#define MRSHPC_IRQ1 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC1)
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#define MRSHPC_IRQ0 (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC0)
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#define SMC_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_SMC)
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#define USB_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_USB)
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#define UARTA_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_UARTA)
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#define UARTB_IRQ (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_UARTB)
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/* arch/sh/boards/se/7343/irq.c */
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extern unsigned int se7343_fpga_irq[];
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void init_7343se_IRQ(void);
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#endif /* __ASM_SH_HITACHI_SE7343_H */
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