drm/exynos: decon: Make plane alpha configurable
The decon hardware supports variable plane alpha. Currently planes are opaque, make this configurable. Tested on TM2 with Exynos 5433 CPU, on top of linux-next-20181019. Signed-off-by: Christoph Manszewski <c.manszewski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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@ -83,6 +83,14 @@ static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
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[CURSON_WIN] = DRM_PLANE_TYPE_CURSOR,
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};
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static const unsigned int capabilities[WINDOWS_NR] = {
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0,
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EXYNOS_DRM_PLANE_CAP_WIN_BLEND,
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EXYNOS_DRM_PLANE_CAP_WIN_BLEND,
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EXYNOS_DRM_PLANE_CAP_WIN_BLEND,
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EXYNOS_DRM_PLANE_CAP_WIN_BLEND,
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};
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static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
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u32 val)
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{
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@ -251,9 +259,30 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
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decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
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}
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static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win,
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unsigned int alpha)
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{
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u32 win_alpha = alpha >> 8;
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u32 val = 0;
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if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
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val = VIDOSD_Wx_ALPHA_R_F(win_alpha) |
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VIDOSD_Wx_ALPHA_G_F(win_alpha) |
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VIDOSD_Wx_ALPHA_B_F(win_alpha);
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decon_set_bits(ctx, DECON_VIDOSDxC(win),
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VIDOSDxC_ALPHA0_RGB_MASK, val);
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decon_set_bits(ctx, DECON_BLENDCON, BLEND_NEW, BLEND_NEW);
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}
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}
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static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
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struct drm_framebuffer *fb)
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{
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struct exynos_drm_plane plane = ctx->planes[win];
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struct exynos_drm_plane_state *state =
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to_exynos_plane_state(plane.base.state);
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unsigned int alpha = state->base.alpha;
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unsigned long val;
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val = readl(ctx->addr + DECON_WINCONx(win));
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@ -280,6 +309,7 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
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val |= WINCONx_BPPMODE_32BPP_A8888;
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val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
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val |= WINCONx_BURSTLEN_16WORD;
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val |= WINCONx_ALPHA_MUL_F;
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break;
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}
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@ -299,6 +329,8 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
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}
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writel(val, ctx->addr + DECON_WINCONx(win));
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if (win > 0)
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decon_win_set_bldmod(ctx, win, alpha);
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}
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static void decon_shadow_protect(struct decon_context *ctx, bool protect)
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@ -551,6 +583,7 @@ static int decon_bind(struct device *dev, struct device *master, void *data)
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ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
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ctx->configs[win].zpos = win - ctx->first_win;
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ctx->configs[win].type = decon_win_types[win];
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ctx->configs[win].capabilities = capabilities[win];
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ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
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&ctx->configs[win]);
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@ -104,6 +104,7 @@
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#define WINCONx_BURSTLEN_16WORD (0x0 << 10)
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#define WINCONx_BURSTLEN_8WORD (0x1 << 10)
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#define WINCONx_BURSTLEN_4WORD (0x2 << 10)
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#define WINCONx_ALPHA_MUL_F (1 << 7)
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#define WINCONx_BLD_PIX_F (1 << 6)
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#define WINCONx_BPPMODE_MASK (0xf << 2)
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#define WINCONx_BPPMODE_16BPP_565 (0x5 << 2)
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@ -121,6 +122,9 @@
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#define SHADOWCON_PROTECT_MASK GENMASK(14, 10)
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#define SHADOWCON_Wx_PROTECT(n) (1 << (10 + (n)))
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/* VIDOSDxC */
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#define VIDOSDxC_ALPHA0_RGB_MASK (0xffffff)
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/* VIDOSDxD */
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#define VIDOSD_Wx_ALPHA_R_F(n) (((n) & 0xff) << 16)
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#define VIDOSD_Wx_ALPHA_G_F(n) (((n) & 0xff) << 8)
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@ -206,4 +210,7 @@
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#define CRCCTRL_CRCEN (0x1 << 0)
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#define CRCCTRL_MASK (0x7)
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/* BLENDCON */
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#define BLEND_NEW (1 << 0)
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#endif /* EXYNOS_REGS_DECON5433_H */
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