RDMA/mlx5: Expose TIR and QP ICM address for sw_owner_v2 devices
Expose the ICM address to access TIR and QP, this will allow sw_owned_v2 devices to steer traffic to TIRs and QPs same as done with sw_owner capability. Link: https://lore.kernel.org/r/20200903073857.1129166-4-leon@kernel.org Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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@ -1477,7 +1477,8 @@ static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN;
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resp->tirn = rq->tirn;
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resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
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if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
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if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
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MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) {
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resp->tir_icm_addr = MLX5_GET(
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create_tir_out, out, icm_address_31_0);
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resp->tir_icm_addr |=
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@ -1739,7 +1740,8 @@ create_tir:
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if (mucontext->devx_uid) {
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params->resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN;
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params->resp.tirn = qp->rss_qp.tirn;
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if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner)) {
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if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner) ||
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MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, sw_owner_v2)) {
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params->resp.tir_icm_addr =
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MLX5_GET(create_tir_out, out, icm_address_31_0);
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params->resp.tir_icm_addr |=
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