KVM: cpuid: extract do_cpuid_7_mask and support multiple subleafs
CPUID function 7 has multiple subleafs. Instead of having nested switch statements, move the logic to filter supported features to a separate function, and call it for each subleaf. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>alistair/sunxi64-5.4-dsi
Paolo Bonzini
parent
ab8bcf6497
commit
54d360d412
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@ -328,6 +328,71 @@ static int __do_cpuid_func_emulated(struct kvm_cpuid_entry2 *entry,
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return 0;
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}
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static inline void do_cpuid_7_mask(struct kvm_cpuid_entry2 *entry, int index)
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{
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unsigned f_invpcid = kvm_x86_ops->invpcid_supported() ? F(INVPCID) : 0;
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unsigned f_mpx = kvm_mpx_supported() ? F(MPX) : 0;
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unsigned f_umip = kvm_x86_ops->umip_emulated() ? F(UMIP) : 0;
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unsigned f_intel_pt = kvm_x86_ops->pt_supported() ? F(INTEL_PT) : 0;
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unsigned f_la57;
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/* cpuid 7.0.ebx */
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const u32 kvm_cpuid_7_0_ebx_x86_features =
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F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) |
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F(BMI2) | F(ERMS) | f_invpcid | F(RTM) | f_mpx | F(RDSEED) |
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F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) |
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F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) |
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F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | f_intel_pt;
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/* cpuid 7.0.ecx*/
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const u32 kvm_cpuid_7_0_ecx_x86_features =
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F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ |
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F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
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F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
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F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B);
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/* cpuid 7.0.edx*/
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const u32 kvm_cpuid_7_0_edx_x86_features =
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F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
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F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
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F(MD_CLEAR);
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switch (index) {
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case 0:
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entry->eax = 0;
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entry->ebx &= kvm_cpuid_7_0_ebx_x86_features;
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cpuid_mask(&entry->ebx, CPUID_7_0_EBX);
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/* TSC_ADJUST is emulated */
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entry->ebx |= F(TSC_ADJUST);
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entry->ecx &= kvm_cpuid_7_0_ecx_x86_features;
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f_la57 = entry->ecx & F(LA57);
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cpuid_mask(&entry->ecx, CPUID_7_ECX);
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/* Set LA57 based on hardware capability. */
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entry->ecx |= f_la57;
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entry->ecx |= f_umip;
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/* PKU is not yet implemented for shadow paging. */
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if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE))
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entry->ecx &= ~F(PKU);
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entry->edx &= kvm_cpuid_7_0_edx_x86_features;
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cpuid_mask(&entry->edx, CPUID_7_EDX);
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/*
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* We emulate ARCH_CAPABILITIES in software even
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* if the host doesn't support it.
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*/
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entry->edx |= F(ARCH_CAPABILITIES);
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break;
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default:
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WARN_ON_ONCE(1);
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entry->eax = 0;
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entry->ebx = 0;
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entry->ecx = 0;
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entry->edx = 0;
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break;
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}
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}
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static inline int __do_cpuid_func(struct kvm_cpuid_entry2 *entry, u32 function,
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int *nent, int maxnent)
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{
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@ -342,12 +407,8 @@ static inline int __do_cpuid_func(struct kvm_cpuid_entry2 *entry, u32 function,
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unsigned f_lm = 0;
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#endif
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unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
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unsigned f_invpcid = kvm_x86_ops->invpcid_supported() ? F(INVPCID) : 0;
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unsigned f_mpx = kvm_mpx_supported() ? F(MPX) : 0;
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unsigned f_xsaves = kvm_x86_ops->xsaves_supported() ? F(XSAVES) : 0;
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unsigned f_umip = kvm_x86_ops->umip_emulated() ? F(UMIP) : 0;
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unsigned f_intel_pt = kvm_x86_ops->pt_supported() ? F(INTEL_PT) : 0;
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unsigned f_la57 = 0;
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/* cpuid 1.edx */
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const u32 kvm_cpuid_1_edx_x86_features =
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@ -400,31 +461,10 @@ static inline int __do_cpuid_func(struct kvm_cpuid_entry2 *entry, u32 function,
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F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
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F(PMM) | F(PMM_EN);
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/* cpuid 7.0.ebx */
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const u32 kvm_cpuid_7_0_ebx_x86_features =
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F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) |
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F(BMI2) | F(ERMS) | f_invpcid | F(RTM) | f_mpx | F(RDSEED) |
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F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) |
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F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) |
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F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | f_intel_pt;
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/* cpuid 0xD.1.eax */
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const u32 kvm_cpuid_D_1_eax_x86_features =
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F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | f_xsaves;
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/* cpuid 7.0.ecx*/
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const u32 kvm_cpuid_7_0_ecx_x86_features =
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F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ |
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F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
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F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
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F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B);
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/* cpuid 7.0.edx*/
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const u32 kvm_cpuid_7_0_edx_x86_features =
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F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
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F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
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F(MD_CLEAR);
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/* all calls to cpuid_count() should be made on the same cpu */
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get_cpu();
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@ -496,30 +536,24 @@ static inline int __do_cpuid_func(struct kvm_cpuid_entry2 *entry, u32 function,
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entry->ecx = 0;
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entry->edx = 0;
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break;
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/* function 7 has additional index. */
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case 7: {
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int i;
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entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
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entry->eax = 0;
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/* Mask ebx against host capability word 9 */
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entry->ebx &= kvm_cpuid_7_0_ebx_x86_features;
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cpuid_mask(&entry->ebx, CPUID_7_0_EBX);
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// TSC_ADJUST is emulated
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entry->ebx |= F(TSC_ADJUST);
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entry->ecx &= kvm_cpuid_7_0_ecx_x86_features;
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f_la57 = entry->ecx & F(LA57);
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cpuid_mask(&entry->ecx, CPUID_7_ECX);
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/* Set LA57 based on hardware capability. */
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entry->ecx |= f_la57;
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entry->ecx |= f_umip;
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/* PKU is not yet implemented for shadow paging. */
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if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE))
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entry->ecx &= ~F(PKU);
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entry->edx &= kvm_cpuid_7_0_edx_x86_features;
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cpuid_mask(&entry->edx, CPUID_7_EDX);
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/*
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* We emulate ARCH_CAPABILITIES in software even
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* if the host doesn't support it.
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*/
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entry->edx |= F(ARCH_CAPABILITIES);
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for (i = 0; ; ) {
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do_cpuid_7_mask(&entry[i], i);
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if (i == entry->eax)
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break;
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if (*nent >= maxnent)
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goto out;
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++i;
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do_cpuid_1_ent(&entry[i], function, i);
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entry[i].flags |=
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KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
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++*nent;
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}
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break;
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}
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case 9:
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