drm/i915: Workaround erratum on i830 for TAIL pointer within last 2 cachelines
On i830 if the tail pointer is set to within 2 cachelines of the end of the buffer, the chip may hang. So instead if the tail were to land in that location, we pad the end of the buffer with NOPs, and start again at the beginning. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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@ -785,6 +785,14 @@ int intel_init_ring_buffer(struct drm_device *dev,
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if (ret)
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goto err_unmap;
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/* Workaround an erratum on the i830 which causes a hang if
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* the TAIL pointer points to within the last 2 cachelines
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* of the buffer.
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*/
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ring->effective_size = ring->size;
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if (IS_I830(ring->dev))
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ring->effective_size -= 128;
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return 0;
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err_unmap:
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@ -827,8 +835,7 @@ void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
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static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
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{
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unsigned int *virt;
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int rem;
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rem = ring->size - ring->tail;
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int rem = ring->size - ring->tail;
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if (ring->space < rem) {
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int ret = intel_wait_ring_buffer(ring, rem);
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@ -895,7 +902,7 @@ int intel_ring_begin(struct intel_ring_buffer *ring,
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int n = 4*num_dwords;
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int ret;
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if (unlikely(ring->tail + n > ring->size)) {
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if (unlikely(ring->tail + n > ring->effective_size)) {
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ret = intel_wrap_ring_buffer(ring);
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if (unlikely(ret))
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return ret;
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@ -49,6 +49,7 @@ struct intel_ring_buffer {
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u32 tail;
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int space;
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int size;
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int effective_size;
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struct intel_hw_status_page status_page;
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u32 irq_seqno; /* last seq seem at irq time */
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