Merge series "ASoC: remove obsolete drivers" from Arnd Bergmann <arnd@kernel.org>
Arnd Bergmann <arnd@arndb.de>: From: Arnd Bergmann <arnd@arndb.de> A few Arm platforms are getting removed in v5.12, this removes the corresponding sound drivers. Link: https://lore.kernel.org/linux-arm-kernel/20210120124812.2800027-1-arnd@kernel.org/T/ Arnd Bergmann (2): ASoC: remove sirf prima/atlas drivers ASoC: remove zte zx drivers .../bindings/sound/sirf-audio-codec.txt | 17 - .../devicetree/bindings/sound/sirf-usp.txt | 27 - .../devicetree/bindings/sound/zte,tdm.txt | 30 - .../bindings/sound/zte,zx-aud96p22.txt | 24 - .../devicetree/bindings/sound/zte,zx-i2s.txt | 45 -- .../bindings/sound/zte,zx-spdif.txt | 27 - sound/soc/Kconfig | 2 - sound/soc/Makefile | 2 - sound/soc/codecs/Makefile | 4 - sound/soc/codecs/sirf-audio-codec.c | 575 ------------------ sound/soc/codecs/zx_aud96p22.c | 401 ------------ sound/soc/sirf/Kconfig | 21 - sound/soc/sirf/Makefile | 8 - sound/soc/sirf/sirf-audio-port.c | 86 --- sound/soc/sirf/sirf-audio.c | 160 ----- sound/soc/sirf/sirf-usp.c | 435 ------------- sound/soc/sirf/sirf-usp.h | 292 --------- sound/soc/zte/Kconfig | 26 - sound/soc/zte/Makefile | 4 - sound/soc/zte/zx-i2s.c | 452 -------------- sound/soc/zte/zx-spdif.c | 363 ----------- sound/soc/zte/zx-tdm.c | 458 -------------- 22 files changed, 3459 deletions(-) delete mode 100644 Documentation/devicetree/bindings/sound/sirf-audio-codec.txt delete mode 100644 Documentation/devicetree/bindings/sound/sirf-usp.txt delete mode 100644 Documentation/devicetree/bindings/sound/zte,tdm.txt delete mode 100644 Documentation/devicetree/bindings/sound/zte,zx-aud96p22.txt delete mode 100644 Documentation/devicetree/bindings/sound/zte,zx-i2s.txt delete mode 100644 Documentation/devicetree/bindings/sound/zte,zx-spdif.txt delete mode 100644 sound/soc/codecs/sirf-audio-codec.c delete mode 100644 sound/soc/codecs/zx_aud96p22.c delete mode 100644 sound/soc/sirf/Kconfig delete mode 100644 sound/soc/sirf/Makefile delete mode 100644 sound/soc/sirf/sirf-audio-port.c delete mode 100644 sound/soc/sirf/sirf-audio.c delete mode 100644 sound/soc/sirf/sirf-usp.c delete mode 100644 sound/soc/sirf/sirf-usp.h delete mode 100644 sound/soc/zte/Kconfig delete mode 100644 sound/soc/zte/Makefile delete mode 100644 sound/soc/zte/zx-i2s.c delete mode 100644 sound/soc/zte/zx-spdif.c delete mode 100644 sound/soc/zte/zx-tdm.c -- 2.29.2
This commit is contained in:
commit
55331b550f
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@ -1,17 +0,0 @@
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SiRF internal audio CODEC
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Required properties:
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- compatible : "sirf,atlas6-audio-codec" or "sirf,prima2-audio-codec"
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- reg : the register address of the device.
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- clocks: the clock of SiRF internal audio codec
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Example:
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audiocodec: audiocodec@b0040000 {
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compatible = "sirf,atlas6-audio-codec";
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reg = <0xb0040000 0x10000>;
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clocks = <&clks 27>;
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};
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@ -1,27 +0,0 @@
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* SiRF SoC USP module
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Required properties:
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- compatible: "sirf,prima2-usp-pcm"
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- reg: Base address and size entries:
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- dmas: List of DMA controller phandle and DMA request line ordered pairs.
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- dma-names: Identifier string for each DMA request line in the dmas property.
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These strings correspond 1:1 with the ordered pairs in dmas.
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One of the DMA channels will be responsible for transmission (should be
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named "tx") and one for reception (should be named "rx").
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- clocks: USP controller clock source
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- pinctrl-names: Must contain a "default" entry.
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- pinctrl-NNN: One property must exist for each entry in pinctrl-names.
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Example:
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usp0: usp@b0080000 {
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compatible = "sirf,prima2-usp-pcm";
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reg = <0xb0080000 0x10000>;
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clocks = <&clks 28>;
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dmas = <&dmac1 1>, <&dmac1 2>;
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dma-names = "rx", "tx";
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pinctrl-names = "default";
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pinctrl-0 = <&usp0_only_utfs_pins_a>;
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};
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@ -1,30 +0,0 @@
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ZTE TDM DAI driver
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Required properties:
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- compatible : should be one of the following.
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* zte,zx296718-tdm
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- reg : physical base address of the controller and length of memory mapped
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region.
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- clocks : Pairs of phandle and specifier referencing the controller's clocks.
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- clock-names: "wclk" for the wclk.
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"pclk" for the pclk.
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-#clock-cells: should be 1.
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- zte,tdm-dma-sysctrl : Reference to the sysctrl controller controlling
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the dma. includes:
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phandle of sysctrl.
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register offset in sysctrl for control dma.
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mask of the register that be written to sysctrl.
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Example:
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tdm: tdm@1487000 {
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compatible = "zte,zx296718-tdm";
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reg = <0x01487000 0x1000>;
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clocks = <&audiocrm AUDIO_TDM_WCLK>, <&audiocrm AUDIO_TDM_PCLK>;
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clock-names = "wclk", "pclk";
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#clock-cells = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&tdm_global_pin>;
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zte,tdm-dma-sysctrl = <&sysctrl 0x10c 4>;
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};
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@ -1,24 +0,0 @@
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ZTE ZX AUD96P22 Audio Codec
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Required properties:
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- compatible: Must be "zte,zx-aud96p22"
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- #sound-dai-cells: Should be 0
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- reg: I2C bus slave address of AUD96P22
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Example:
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i2c0: i2c@1486000 {
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compatible = "zte,zx296718-i2c";
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reg = <0x01486000 0x1000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&audiocrm AUDIO_I2C0_WCLK>;
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clock-frequency = <1600000>;
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aud96p22: codec@22 {
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compatible = "zte,zx-aud96p22";
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#sound-dai-cells = <0>;
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reg = <0x22>;
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};
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};
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@ -1,45 +0,0 @@
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ZTE ZX296702 I2S controller
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Required properties:
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- compatible : Must be one of:
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"zte,zx296718-i2s", "zte,zx296702-i2s"
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"zte,zx296702-i2s"
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- reg : Must contain I2S core's registers location and length
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- clocks : Pairs of phandle and specifier referencing the controller's clocks.
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- clock-names: "wclk" for the wclk, "pclk" for the pclk to the I2S interface.
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- dmas: Pairs of phandle and specifier for the DMA channel that is used by
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the core. The core expects two dma channels for transmit.
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- dma-names : Must be "tx" and "rx"
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For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
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please check:
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* resource-names.txt
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* clock/clock-bindings.txt
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* dma/dma.txt
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Example:
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i2s0: i2s@b005000 {
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#sound-dai-cells = <0>;
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compatible = "zte,zx296718-i2s", "zte,zx296702-i2s";
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reg = <0x0b005000 0x1000>;
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clocks = <&audiocrm AUDIO_I2S0_WCLK>, <&audiocrm AUDIO_I2S0_PCLK>;
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clock-names = "wclk", "pclk";
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma 5>, <&dma 6>;
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dma-names = "tx", "rx";
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};
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,name = "zx296702_snd";
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simple-audio-card,format = "left_j";
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simple-audio-card,bitclock-master = <&sndcodec>;
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simple-audio-card,frame-master = <&sndcodec>;
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sndcpu: simple-audio-card,cpu {
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sound-dai = <&i2s0>;
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};
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sndcodec: simple-audio-card,codec {
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sound-dai = <&acodec>;
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};
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};
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@ -1,27 +0,0 @@
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ZTE ZX296702 SPDIF controller
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Required properties:
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- compatible : Must be "zte,zx296702-spdif"
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- reg : Must contain SPDIF core's registers location and length
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- clocks : Pairs of phandle and specifier referencing the controller's clocks.
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- clock-names: "tx" for the clock to the SPDIF interface.
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- dmas: Pairs of phandle and specifier for the DMA channel that is used by
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the core. The core expects one dma channel for transmit.
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- dma-names : Must be "tx"
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For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
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please check:
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* resource-names.txt
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* clock/clock-bindings.txt
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* dma/dma.txt
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Example:
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spdif0: spdif0@b004000 {
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compatible = "zte,zx296702-spdif";
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reg = <0x0b004000 0x1000>;
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clocks = <&lsp0clk ZX296702_SPDIF0_DIV>;
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clock-names = "tx";
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma 4>;
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dma-names = "tx";
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};
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@ -62,7 +62,6 @@ source "sound/soc/qcom/Kconfig"
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source "sound/soc/rockchip/Kconfig"
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source "sound/soc/samsung/Kconfig"
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source "sound/soc/sh/Kconfig"
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source "sound/soc/sirf/Kconfig"
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source "sound/soc/sof/Kconfig"
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source "sound/soc/spear/Kconfig"
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source "sound/soc/sprd/Kconfig"
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@ -75,7 +74,6 @@ source "sound/soc/uniphier/Kconfig"
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source "sound/soc/ux500/Kconfig"
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source "sound/soc/xilinx/Kconfig"
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source "sound/soc/xtensa/Kconfig"
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source "sound/soc/zte/Kconfig"
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# Supported codecs
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source "sound/soc/codecs/Kconfig"
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@ -45,7 +45,6 @@ obj-$(CONFIG_SND_SOC) += qcom/
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obj-$(CONFIG_SND_SOC) += rockchip/
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obj-$(CONFIG_SND_SOC) += samsung/
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obj-$(CONFIG_SND_SOC) += sh/
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obj-$(CONFIG_SND_SOC) += sirf/
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obj-$(CONFIG_SND_SOC) += sof/
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obj-$(CONFIG_SND_SOC) += spear/
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obj-$(CONFIG_SND_SOC) += sprd/
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obj-$(CONFIG_SND_SOC) += ux500/
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obj-$(CONFIG_SND_SOC) += xilinx/
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obj-$(CONFIG_SND_SOC) += xtensa/
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obj-$(CONFIG_SND_SOC) += zte/
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@ -201,7 +201,6 @@ snd-soc-sigmadsp-objs := sigmadsp.o
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snd-soc-sigmadsp-i2c-objs := sigmadsp-i2c.o
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snd-soc-sigmadsp-regmap-objs := sigmadsp-regmap.o
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snd-soc-si476x-objs := si476x.o
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snd-soc-sirf-audio-codec-objs := sirf-audio-codec.o
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snd-soc-spdif-tx-objs := spdif_transmitter.o
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snd-soc-spdif-rx-objs := spdif_receiver.o
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snd-soc-ssm2305-objs := ssm2305.o
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@ -302,7 +301,6 @@ snd-soc-wm9713-objs := wm9713.o
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snd-soc-wm-hubs-objs := wm_hubs.o
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snd-soc-wsa881x-objs := wsa881x.o
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snd-soc-zl38060-objs := zl38060.o
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snd-soc-zx-aud96p22-objs := zx_aud96p22.o
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# Amp
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snd-soc-max9877-objs := max9877.o
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snd-soc-max98504-objs := max98504.o
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@ -516,7 +514,6 @@ obj-$(CONFIG_SND_SOC_SIGMADSP_I2C) += snd-soc-sigmadsp-i2c.o
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obj-$(CONFIG_SND_SOC_SIGMADSP_REGMAP) += snd-soc-sigmadsp-regmap.o
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obj-$(CONFIG_SND_SOC_SI476X) += snd-soc-si476x.o
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obj-$(CONFIG_SND_SOC_SPDIF) += snd-soc-spdif-rx.o snd-soc-spdif-tx.o
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obj-$(CONFIG_SND_SOC_SIRF_AUDIO_CODEC) += sirf-audio-codec.o
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obj-$(CONFIG_SND_SOC_SSM2305) += snd-soc-ssm2305.o
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obj-$(CONFIG_SND_SOC_SSM2518) += snd-soc-ssm2518.o
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obj-$(CONFIG_SND_SOC_SSM2602) += snd-soc-ssm2602.o
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@ -618,7 +615,6 @@ obj-$(CONFIG_SND_SOC_WM_ADSP) += snd-soc-wm-adsp.o
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obj-$(CONFIG_SND_SOC_WM_HUBS) += snd-soc-wm-hubs.o
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obj-$(CONFIG_SND_SOC_WSA881X) += snd-soc-wsa881x.o
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obj-$(CONFIG_SND_SOC_ZL38060) += snd-soc-zl38060.o
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obj-$(CONFIG_SND_SOC_ZX_AUD96P22) += snd-soc-zx-aud96p22.o
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# Amp
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obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o
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@ -1,575 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* SiRF audio codec driver
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/regmap.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/tlv.h>
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#include <sound/soc.h>
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#include <sound/dmaengine_pcm.h>
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#include "sirf-audio-codec.h"
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struct sirf_audio_codec {
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struct clk *clk;
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struct regmap *regmap;
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u32 reg_ctrl0, reg_ctrl1;
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};
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static const char * const input_mode_mux[] = {"Single-ended",
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"Differential"};
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static const struct soc_enum input_mode_mux_enum =
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SOC_ENUM_SINGLE(AUDIO_IC_CODEC_CTRL1, 4, 2, input_mode_mux);
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static const struct snd_kcontrol_new sirf_audio_codec_input_mode_control =
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SOC_DAPM_ENUM("Route", input_mode_mux_enum);
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static const DECLARE_TLV_DB_SCALE(playback_vol_tlv, -12400, 100, 0);
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static const DECLARE_TLV_DB_SCALE(capture_vol_tlv_prima2, 500, 100, 0);
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static const DECLARE_TLV_DB_RANGE(capture_vol_tlv_atlas6,
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0, 7, TLV_DB_SCALE_ITEM(-100, 100, 0),
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0x22, 0x3F, TLV_DB_SCALE_ITEM(700, 100, 0),
|
||||
);
|
||||
|
||||
static struct snd_kcontrol_new volume_controls_atlas6[] = {
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SOC_DOUBLE_TLV("Playback Volume", AUDIO_IC_CODEC_CTRL0, 21, 14,
|
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0x7F, 0, playback_vol_tlv),
|
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SOC_DOUBLE_TLV("Capture Volume", AUDIO_IC_CODEC_CTRL1, 16, 10,
|
||||
0x3F, 0, capture_vol_tlv_atlas6),
|
||||
};
|
||||
|
||||
static struct snd_kcontrol_new volume_controls_prima2[] = {
|
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SOC_DOUBLE_TLV("Speaker Volume", AUDIO_IC_CODEC_CTRL0, 21, 14,
|
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0x7F, 0, playback_vol_tlv),
|
||||
SOC_DOUBLE_TLV("Capture Volume", AUDIO_IC_CODEC_CTRL1, 15, 10,
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0x1F, 0, capture_vol_tlv_prima2),
|
||||
};
|
||||
|
||||
static struct snd_kcontrol_new left_input_path_controls[] = {
|
||||
SOC_DAPM_SINGLE("Line Left Switch", AUDIO_IC_CODEC_CTRL1, 6, 1, 0),
|
||||
SOC_DAPM_SINGLE("Mic Left Switch", AUDIO_IC_CODEC_CTRL1, 3, 1, 0),
|
||||
};
|
||||
|
||||
static struct snd_kcontrol_new right_input_path_controls[] = {
|
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SOC_DAPM_SINGLE("Line Right Switch", AUDIO_IC_CODEC_CTRL1, 5, 1, 0),
|
||||
SOC_DAPM_SINGLE("Mic Right Switch", AUDIO_IC_CODEC_CTRL1, 2, 1, 0),
|
||||
};
|
||||
|
||||
static struct snd_kcontrol_new left_dac_to_hp_left_amp_switch_control =
|
||||
SOC_DAPM_SINGLE("Switch", AUDIO_IC_CODEC_CTRL0, 9, 1, 0);
|
||||
|
||||
static struct snd_kcontrol_new left_dac_to_hp_right_amp_switch_control =
|
||||
SOC_DAPM_SINGLE("Switch", AUDIO_IC_CODEC_CTRL0, 8, 1, 0);
|
||||
|
||||
static struct snd_kcontrol_new right_dac_to_hp_left_amp_switch_control =
|
||||
SOC_DAPM_SINGLE("Switch", AUDIO_IC_CODEC_CTRL0, 7, 1, 0);
|
||||
|
||||
static struct snd_kcontrol_new right_dac_to_hp_right_amp_switch_control =
|
||||
SOC_DAPM_SINGLE("Switch", AUDIO_IC_CODEC_CTRL0, 6, 1, 0);
|
||||
|
||||
static struct snd_kcontrol_new left_dac_to_speaker_lineout_switch_control =
|
||||
SOC_DAPM_SINGLE("Switch", AUDIO_IC_CODEC_CTRL0, 11, 1, 0);
|
||||
|
||||
static struct snd_kcontrol_new right_dac_to_speaker_lineout_switch_control =
|
||||
SOC_DAPM_SINGLE("Switch", AUDIO_IC_CODEC_CTRL0, 10, 1, 0);
|
||||
|
||||
/* After enable adc, Delay 200ms to avoid pop noise */
|
||||
static int adc_enable_delay_event(struct snd_soc_dapm_widget *w,
|
||||
struct snd_kcontrol *kcontrol, int event)
|
||||
{
|
||||
switch (event) {
|
||||
case SND_SOC_DAPM_POST_PMU:
|
||||
msleep(200);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void enable_and_reset_codec(struct regmap *regmap,
|
||||
u32 codec_enable_bits, u32 codec_reset_bits)
|
||||
{
|
||||
regmap_update_bits(regmap, AUDIO_IC_CODEC_CTRL1,
|
||||
codec_enable_bits | codec_reset_bits,
|
||||
codec_enable_bits);
|
||||
msleep(20);
|
||||
regmap_update_bits(regmap, AUDIO_IC_CODEC_CTRL1,
|
||||
codec_reset_bits, codec_reset_bits);
|
||||
}
|
||||
|
||||
static int atlas6_codec_enable_and_reset_event(struct snd_soc_dapm_widget *w,
|
||||
struct snd_kcontrol *kcontrol, int event)
|
||||
{
|
||||
#define ATLAS6_CODEC_ENABLE_BITS (1 << 29)
|
||||
#define ATLAS6_CODEC_RESET_BITS (1 << 28)
|
||||
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
|
||||
struct sirf_audio_codec *sirf_audio_codec = snd_soc_component_get_drvdata(component);
|
||||
switch (event) {
|
||||
case SND_SOC_DAPM_PRE_PMU:
|
||||
enable_and_reset_codec(sirf_audio_codec->regmap,
|
||||
ATLAS6_CODEC_ENABLE_BITS, ATLAS6_CODEC_RESET_BITS);
|
||||
break;
|
||||
case SND_SOC_DAPM_POST_PMD:
|
||||
regmap_update_bits(sirf_audio_codec->regmap,
|
||||
AUDIO_IC_CODEC_CTRL1, ATLAS6_CODEC_ENABLE_BITS, 0);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int prima2_codec_enable_and_reset_event(struct snd_soc_dapm_widget *w,
|
||||
struct snd_kcontrol *kcontrol, int event)
|
||||
{
|
||||
#define PRIMA2_CODEC_ENABLE_BITS (1 << 27)
|
||||
#define PRIMA2_CODEC_RESET_BITS (1 << 26)
|
||||
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
|
||||
struct sirf_audio_codec *sirf_audio_codec = snd_soc_component_get_drvdata(component);
|
||||
switch (event) {
|
||||
case SND_SOC_DAPM_POST_PMU:
|
||||
enable_and_reset_codec(sirf_audio_codec->regmap,
|
||||
PRIMA2_CODEC_ENABLE_BITS, PRIMA2_CODEC_RESET_BITS);
|
||||
break;
|
||||
case SND_SOC_DAPM_POST_PMD:
|
||||
regmap_update_bits(sirf_audio_codec->regmap,
|
||||
AUDIO_IC_CODEC_CTRL1, PRIMA2_CODEC_ENABLE_BITS, 0);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct snd_soc_dapm_widget atlas6_output_driver_dapm_widgets[] = {
|
||||
SND_SOC_DAPM_OUT_DRV("HP Left Driver", AUDIO_IC_CODEC_CTRL1,
|
||||
25, 0, NULL, 0),
|
||||
SND_SOC_DAPM_OUT_DRV("HP Right Driver", AUDIO_IC_CODEC_CTRL1,
|
||||
26, 0, NULL, 0),
|
||||
SND_SOC_DAPM_OUT_DRV("Speaker Driver", AUDIO_IC_CODEC_CTRL1,
|
||||
27, 0, NULL, 0),
|
||||
};
|
||||
|
||||
static const struct snd_soc_dapm_widget prima2_output_driver_dapm_widgets[] = {
|
||||
SND_SOC_DAPM_OUT_DRV("HP Left Driver", AUDIO_IC_CODEC_CTRL1,
|
||||
23, 0, NULL, 0),
|
||||
SND_SOC_DAPM_OUT_DRV("HP Right Driver", AUDIO_IC_CODEC_CTRL1,
|
||||
24, 0, NULL, 0),
|
||||
SND_SOC_DAPM_OUT_DRV("Speaker Driver", AUDIO_IC_CODEC_CTRL1,
|
||||
25, 0, NULL, 0),
|
||||
};
|
||||
|
||||
static const struct snd_soc_dapm_widget atlas6_codec_clock_dapm_widget =
|
||||
SND_SOC_DAPM_SUPPLY("codecclk", SND_SOC_NOPM, 0, 0,
|
||||
atlas6_codec_enable_and_reset_event,
|
||||
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD);
|
||||
|
||||
static const struct snd_soc_dapm_widget prima2_codec_clock_dapm_widget =
|
||||
SND_SOC_DAPM_SUPPLY("codecclk", SND_SOC_NOPM, 0, 0,
|
||||
prima2_codec_enable_and_reset_event,
|
||||
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD);
|
||||
|
||||
static const struct snd_soc_dapm_widget sirf_audio_codec_dapm_widgets[] = {
|
||||
SND_SOC_DAPM_DAC("DAC left", NULL, AUDIO_IC_CODEC_CTRL0, 1, 0),
|
||||
SND_SOC_DAPM_DAC("DAC right", NULL, AUDIO_IC_CODEC_CTRL0, 0, 0),
|
||||
SND_SOC_DAPM_SWITCH("Left dac to hp left amp", SND_SOC_NOPM, 0, 0,
|
||||
&left_dac_to_hp_left_amp_switch_control),
|
||||
SND_SOC_DAPM_SWITCH("Left dac to hp right amp", SND_SOC_NOPM, 0, 0,
|
||||
&left_dac_to_hp_right_amp_switch_control),
|
||||
SND_SOC_DAPM_SWITCH("Right dac to hp left amp", SND_SOC_NOPM, 0, 0,
|
||||
&right_dac_to_hp_left_amp_switch_control),
|
||||
SND_SOC_DAPM_SWITCH("Right dac to hp right amp", SND_SOC_NOPM, 0, 0,
|
||||
&right_dac_to_hp_right_amp_switch_control),
|
||||
SND_SOC_DAPM_OUT_DRV("HP amp left driver", AUDIO_IC_CODEC_CTRL0, 3, 0,
|
||||
NULL, 0),
|
||||
SND_SOC_DAPM_OUT_DRV("HP amp right driver", AUDIO_IC_CODEC_CTRL0, 3, 0,
|
||||
NULL, 0),
|
||||
|
||||
SND_SOC_DAPM_SWITCH("Left dac to speaker lineout", SND_SOC_NOPM, 0, 0,
|
||||
&left_dac_to_speaker_lineout_switch_control),
|
||||
SND_SOC_DAPM_SWITCH("Right dac to speaker lineout", SND_SOC_NOPM, 0, 0,
|
||||
&right_dac_to_speaker_lineout_switch_control),
|
||||
SND_SOC_DAPM_OUT_DRV("Speaker amp driver", AUDIO_IC_CODEC_CTRL0, 4, 0,
|
||||
NULL, 0),
|
||||
|
||||
SND_SOC_DAPM_OUTPUT("HPOUTL"),
|
||||
SND_SOC_DAPM_OUTPUT("HPOUTR"),
|
||||
SND_SOC_DAPM_OUTPUT("SPKOUT"),
|
||||
|
||||
SND_SOC_DAPM_ADC_E("ADC left", NULL, AUDIO_IC_CODEC_CTRL1, 8, 0,
|
||||
adc_enable_delay_event, SND_SOC_DAPM_POST_PMU),
|
||||
SND_SOC_DAPM_ADC_E("ADC right", NULL, AUDIO_IC_CODEC_CTRL1, 7, 0,
|
||||
adc_enable_delay_event, SND_SOC_DAPM_POST_PMU),
|
||||
SND_SOC_DAPM_MIXER("Left PGA mixer", AUDIO_IC_CODEC_CTRL1, 1, 0,
|
||||
&left_input_path_controls[0],
|
||||
ARRAY_SIZE(left_input_path_controls)),
|
||||
SND_SOC_DAPM_MIXER("Right PGA mixer", AUDIO_IC_CODEC_CTRL1, 0, 0,
|
||||
&right_input_path_controls[0],
|
||||
ARRAY_SIZE(right_input_path_controls)),
|
||||
|
||||
SND_SOC_DAPM_MUX("Mic input mode mux", SND_SOC_NOPM, 0, 0,
|
||||
&sirf_audio_codec_input_mode_control),
|
||||
SND_SOC_DAPM_MICBIAS("Mic Bias", AUDIO_IC_CODEC_PWR, 3, 0),
|
||||
SND_SOC_DAPM_INPUT("MICIN1"),
|
||||
SND_SOC_DAPM_INPUT("MICIN2"),
|
||||
SND_SOC_DAPM_INPUT("LINEIN1"),
|
||||
SND_SOC_DAPM_INPUT("LINEIN2"),
|
||||
|
||||
SND_SOC_DAPM_SUPPLY("HSL Phase Opposite", AUDIO_IC_CODEC_CTRL0,
|
||||
30, 0, NULL, 0),
|
||||
};
|
||||
|
||||
static const struct snd_soc_dapm_route sirf_audio_codec_map[] = {
|
||||
{"SPKOUT", NULL, "Speaker Driver"},
|
||||
{"Speaker Driver", NULL, "Speaker amp driver"},
|
||||
{"Speaker amp driver", NULL, "Left dac to speaker lineout"},
|
||||
{"Speaker amp driver", NULL, "Right dac to speaker lineout"},
|
||||
{"Left dac to speaker lineout", "Switch", "DAC left"},
|
||||
{"Right dac to speaker lineout", "Switch", "DAC right"},
|
||||
{"HPOUTL", NULL, "HP Left Driver"},
|
||||
{"HPOUTR", NULL, "HP Right Driver"},
|
||||
{"HP Left Driver", NULL, "HP amp left driver"},
|
||||
{"HP Right Driver", NULL, "HP amp right driver"},
|
||||
{"HP amp left driver", NULL, "Right dac to hp left amp"},
|
||||
{"HP amp right driver", NULL , "Right dac to hp right amp"},
|
||||
{"HP amp left driver", NULL, "Left dac to hp left amp"},
|
||||
{"HP amp right driver", NULL , "Right dac to hp right amp"},
|
||||
{"Right dac to hp left amp", "Switch", "DAC left"},
|
||||
{"Right dac to hp right amp", "Switch", "DAC right"},
|
||||
{"Left dac to hp left amp", "Switch", "DAC left"},
|
||||
{"Left dac to hp right amp", "Switch", "DAC right"},
|
||||
{"DAC left", NULL, "codecclk"},
|
||||
{"DAC right", NULL, "codecclk"},
|
||||
{"DAC left", NULL, "Playback"},
|
||||
{"DAC right", NULL, "Playback"},
|
||||
{"DAC left", NULL, "HSL Phase Opposite"},
|
||||
{"DAC right", NULL, "HSL Phase Opposite"},
|
||||
|
||||
{"Capture", NULL, "ADC left"},
|
||||
{"Capture", NULL, "ADC right"},
|
||||
{"ADC left", NULL, "codecclk"},
|
||||
{"ADC right", NULL, "codecclk"},
|
||||
{"ADC left", NULL, "Left PGA mixer"},
|
||||
{"ADC right", NULL, "Right PGA mixer"},
|
||||
{"Left PGA mixer", "Line Left Switch", "LINEIN2"},
|
||||
{"Right PGA mixer", "Line Right Switch", "LINEIN1"},
|
||||
{"Left PGA mixer", "Mic Left Switch", "MICIN2"},
|
||||
{"Right PGA mixer", "Mic Right Switch", "Mic input mode mux"},
|
||||
{"Mic input mode mux", "Single-ended", "MICIN1"},
|
||||
{"Mic input mode mux", "Differential", "MICIN1"},
|
||||
};
|
||||
|
||||
static void sirf_audio_codec_tx_enable(struct sirf_audio_codec *sirf_audio_codec)
|
||||
{
|
||||
regmap_update_bits(sirf_audio_codec->regmap, AUDIO_PORT_IC_TXFIFO_OP,
|
||||
AUDIO_FIFO_RESET, AUDIO_FIFO_RESET);
|
||||
regmap_update_bits(sirf_audio_codec->regmap, AUDIO_PORT_IC_TXFIFO_OP,
|
||||
AUDIO_FIFO_RESET, ~AUDIO_FIFO_RESET);
|
||||
regmap_write(sirf_audio_codec->regmap, AUDIO_PORT_IC_TXFIFO_INT_MSK, 0);
|
||||
regmap_write(sirf_audio_codec->regmap, AUDIO_PORT_IC_TXFIFO_OP, 0);
|
||||
regmap_update_bits(sirf_audio_codec->regmap, AUDIO_PORT_IC_TXFIFO_OP,
|
||||
AUDIO_FIFO_START, AUDIO_FIFO_START);
|
||||
regmap_update_bits(sirf_audio_codec->regmap,
|
||||
AUDIO_PORT_IC_CODEC_TX_CTRL, IC_TX_ENABLE, IC_TX_ENABLE);
|
||||
}
|
||||
|
||||
static void sirf_audio_codec_tx_disable(struct sirf_audio_codec *sirf_audio_codec)
|
||||
{
|
||||
regmap_write(sirf_audio_codec->regmap, AUDIO_PORT_IC_TXFIFO_OP, 0);
|
||||
regmap_update_bits(sirf_audio_codec->regmap,
|
||||
AUDIO_PORT_IC_CODEC_TX_CTRL, IC_TX_ENABLE, ~IC_TX_ENABLE);
|
||||
}
|
||||
|
||||
static void sirf_audio_codec_rx_enable(struct sirf_audio_codec *sirf_audio_codec,
|
||||
int channels)
|
||||
{
|
||||
regmap_update_bits(sirf_audio_codec->regmap, AUDIO_PORT_IC_RXFIFO_OP,
|
||||
AUDIO_FIFO_RESET, AUDIO_FIFO_RESET);
|
||||
regmap_update_bits(sirf_audio_codec->regmap, AUDIO_PORT_IC_RXFIFO_OP,
|
||||
AUDIO_FIFO_RESET, ~AUDIO_FIFO_RESET);
|
||||
regmap_write(sirf_audio_codec->regmap,
|
||||
AUDIO_PORT_IC_RXFIFO_INT_MSK, 0);
|
||||
regmap_write(sirf_audio_codec->regmap, AUDIO_PORT_IC_RXFIFO_OP, 0);
|
||||
regmap_update_bits(sirf_audio_codec->regmap, AUDIO_PORT_IC_RXFIFO_OP,
|
||||
AUDIO_FIFO_START, AUDIO_FIFO_START);
|
||||
if (channels == 1)
|
||||
regmap_update_bits(sirf_audio_codec->regmap,
|
||||
AUDIO_PORT_IC_CODEC_RX_CTRL,
|
||||
IC_RX_ENABLE_MONO, IC_RX_ENABLE_MONO);
|
||||
else
|
||||
regmap_update_bits(sirf_audio_codec->regmap,
|
||||
AUDIO_PORT_IC_CODEC_RX_CTRL,
|
||||
IC_RX_ENABLE_STEREO, IC_RX_ENABLE_STEREO);
|
||||
}
|
||||
|
||||
static void sirf_audio_codec_rx_disable(struct sirf_audio_codec *sirf_audio_codec)
|
||||
{
|
||||
regmap_update_bits(sirf_audio_codec->regmap,
|
||||
AUDIO_PORT_IC_CODEC_RX_CTRL,
|
||||
IC_RX_ENABLE_STEREO, ~IC_RX_ENABLE_STEREO);
|
||||
}
|
||||
|
||||
static int sirf_audio_codec_trigger(struct snd_pcm_substream *substream,
|
||||
int cmd,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct snd_soc_component *component = dai->component;
|
||||
struct sirf_audio_codec *sirf_audio_codec = snd_soc_component_get_drvdata(component);
|
||||
int playback = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
|
||||
|
||||
/*
|
||||
* This is a workaround, When stop playback,
|
||||
* need disable HP amp, avoid the current noise.
|
||||
*/
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
case SNDRV_PCM_TRIGGER_SUSPEND:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
if (playback) {
|
||||
snd_soc_component_update_bits(component, AUDIO_IC_CODEC_CTRL0,
|
||||
IC_HSLEN | IC_HSREN, 0);
|
||||
sirf_audio_codec_tx_disable(sirf_audio_codec);
|
||||
} else
|
||||
sirf_audio_codec_rx_disable(sirf_audio_codec);
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
case SNDRV_PCM_TRIGGER_RESUME:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
||||
if (playback) {
|
||||
sirf_audio_codec_tx_enable(sirf_audio_codec);
|
||||
snd_soc_component_update_bits(component, AUDIO_IC_CODEC_CTRL0,
|
||||
IC_HSLEN | IC_HSREN, IC_HSLEN | IC_HSREN);
|
||||
} else
|
||||
sirf_audio_codec_rx_enable(sirf_audio_codec,
|
||||
substream->runtime->channels);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct snd_soc_dai_ops sirf_audio_codec_dai_ops = {
|
||||
.trigger = sirf_audio_codec_trigger,
|
||||
};
|
||||
|
||||
static struct snd_soc_dai_driver sirf_audio_codec_dai = {
|
||||
.name = "sirf-audio-codec",
|
||||
.playback = {
|
||||
.stream_name = "Playback",
|
||||
.channels_min = 2,
|
||||
.channels_max = 2,
|
||||
.rates = SNDRV_PCM_RATE_48000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
||||
},
|
||||
.capture = {
|
||||
.stream_name = "Capture",
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = SNDRV_PCM_RATE_48000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
||||
},
|
||||
.ops = &sirf_audio_codec_dai_ops,
|
||||
};
|
||||
|
||||
static int sirf_audio_codec_probe(struct snd_soc_component *component)
|
||||
{
|
||||
struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
|
||||
|
||||
pm_runtime_enable(component->dev);
|
||||
|
||||
if (of_device_is_compatible(component->dev->of_node, "sirf,prima2-audio-codec")) {
|
||||
snd_soc_dapm_new_controls(dapm,
|
||||
prima2_output_driver_dapm_widgets,
|
||||
ARRAY_SIZE(prima2_output_driver_dapm_widgets));
|
||||
snd_soc_dapm_new_controls(dapm,
|
||||
&prima2_codec_clock_dapm_widget, 1);
|
||||
return snd_soc_add_component_controls(component,
|
||||
volume_controls_prima2,
|
||||
ARRAY_SIZE(volume_controls_prima2));
|
||||
}
|
||||
if (of_device_is_compatible(component->dev->of_node, "sirf,atlas6-audio-codec")) {
|
||||
snd_soc_dapm_new_controls(dapm,
|
||||
atlas6_output_driver_dapm_widgets,
|
||||
ARRAY_SIZE(atlas6_output_driver_dapm_widgets));
|
||||
snd_soc_dapm_new_controls(dapm,
|
||||
&atlas6_codec_clock_dapm_widget, 1);
|
||||
return snd_soc_add_component_controls(component,
|
||||
volume_controls_atlas6,
|
||||
ARRAY_SIZE(volume_controls_atlas6));
|
||||
}
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static void sirf_audio_codec_remove(struct snd_soc_component *component)
|
||||
{
|
||||
pm_runtime_disable(component->dev);
|
||||
}
|
||||
|
||||
static const struct snd_soc_component_driver soc_codec_device_sirf_audio_codec = {
|
||||
.probe = sirf_audio_codec_probe,
|
||||
.remove = sirf_audio_codec_remove,
|
||||
.dapm_widgets = sirf_audio_codec_dapm_widgets,
|
||||
.num_dapm_widgets = ARRAY_SIZE(sirf_audio_codec_dapm_widgets),
|
||||
.dapm_routes = sirf_audio_codec_map,
|
||||
.num_dapm_routes = ARRAY_SIZE(sirf_audio_codec_map),
|
||||
.use_pmdown_time = 1,
|
||||
.endianness = 1,
|
||||
.non_legacy_dai_naming = 1,
|
||||
};
|
||||
|
||||
static const struct of_device_id sirf_audio_codec_of_match[] = {
|
||||
{ .compatible = "sirf,prima2-audio-codec" },
|
||||
{ .compatible = "sirf,atlas6-audio-codec" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sirf_audio_codec_of_match);
|
||||
|
||||
static const struct regmap_config sirf_audio_codec_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = AUDIO_PORT_IC_RXFIFO_INT_MSK,
|
||||
.cache_type = REGCACHE_NONE,
|
||||
};
|
||||
|
||||
static int sirf_audio_codec_driver_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct sirf_audio_codec *sirf_audio_codec;
|
||||
void __iomem *base;
|
||||
|
||||
sirf_audio_codec = devm_kzalloc(&pdev->dev,
|
||||
sizeof(struct sirf_audio_codec), GFP_KERNEL);
|
||||
if (!sirf_audio_codec)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, sirf_audio_codec);
|
||||
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
sirf_audio_codec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
|
||||
&sirf_audio_codec_regmap_config);
|
||||
if (IS_ERR(sirf_audio_codec->regmap))
|
||||
return PTR_ERR(sirf_audio_codec->regmap);
|
||||
|
||||
sirf_audio_codec->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(sirf_audio_codec->clk)) {
|
||||
dev_err(&pdev->dev, "Get clock failed.\n");
|
||||
return PTR_ERR(sirf_audio_codec->clk);
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(sirf_audio_codec->clk);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Enable clock failed.\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_snd_soc_register_component(&(pdev->dev),
|
||||
&soc_codec_device_sirf_audio_codec,
|
||||
&sirf_audio_codec_dai, 1);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Register Audio Codec dai failed.\n");
|
||||
goto err_clk_put;
|
||||
}
|
||||
|
||||
/*
|
||||
* Always open charge pump, if not, when the charge pump closed the
|
||||
* adc will not stable
|
||||
*/
|
||||
regmap_update_bits(sirf_audio_codec->regmap, AUDIO_IC_CODEC_CTRL0,
|
||||
IC_CPFREQ, IC_CPFREQ);
|
||||
|
||||
if (of_device_is_compatible(pdev->dev.of_node, "sirf,atlas6-audio-codec"))
|
||||
regmap_update_bits(sirf_audio_codec->regmap,
|
||||
AUDIO_IC_CODEC_CTRL0, IC_CPEN, IC_CPEN);
|
||||
return 0;
|
||||
|
||||
err_clk_put:
|
||||
clk_disable_unprepare(sirf_audio_codec->clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sirf_audio_codec_driver_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sirf_audio_codec *sirf_audio_codec = platform_get_drvdata(pdev);
|
||||
|
||||
clk_disable_unprepare(sirf_audio_codec->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int sirf_audio_codec_suspend(struct device *dev)
|
||||
{
|
||||
struct sirf_audio_codec *sirf_audio_codec = dev_get_drvdata(dev);
|
||||
|
||||
regmap_read(sirf_audio_codec->regmap, AUDIO_IC_CODEC_CTRL0,
|
||||
&sirf_audio_codec->reg_ctrl0);
|
||||
regmap_read(sirf_audio_codec->regmap, AUDIO_IC_CODEC_CTRL1,
|
||||
&sirf_audio_codec->reg_ctrl1);
|
||||
clk_disable_unprepare(sirf_audio_codec->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sirf_audio_codec_resume(struct device *dev)
|
||||
{
|
||||
struct sirf_audio_codec *sirf_audio_codec = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(sirf_audio_codec->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
regmap_write(sirf_audio_codec->regmap, AUDIO_IC_CODEC_CTRL0,
|
||||
sirf_audio_codec->reg_ctrl0);
|
||||
regmap_write(sirf_audio_codec->regmap, AUDIO_IC_CODEC_CTRL1,
|
||||
sirf_audio_codec->reg_ctrl1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct dev_pm_ops sirf_audio_codec_pm_ops = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(sirf_audio_codec_suspend, sirf_audio_codec_resume)
|
||||
};
|
||||
|
||||
static struct platform_driver sirf_audio_codec_driver = {
|
||||
.driver = {
|
||||
.name = "sirf-audio-codec",
|
||||
.of_match_table = sirf_audio_codec_of_match,
|
||||
.pm = &sirf_audio_codec_pm_ops,
|
||||
},
|
||||
.probe = sirf_audio_codec_driver_probe,
|
||||
.remove = sirf_audio_codec_driver_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(sirf_audio_codec_driver);
|
||||
|
||||
MODULE_DESCRIPTION("SiRF audio codec driver");
|
||||
MODULE_AUTHOR("RongJun Ying <Rongjun.Ying@csr.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
|
@ -1,401 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2017 Sanechips Technology Co., Ltd.
|
||||
* Copyright 2017 Linaro Ltd.
|
||||
*
|
||||
* Author: Baoyou Xie <baoyou.xie@linaro.org>
|
||||
*/
|
||||
|
||||
#include <linux/gpio/consumer.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <sound/pcm.h>
|
||||
#include <sound/pcm_params.h>
|
||||
#include <sound/soc.h>
|
||||
#include <sound/soc-dai.h>
|
||||
#include <sound/tlv.h>
|
||||
|
||||
#define AUD96P22_RESET 0x00
|
||||
#define RST_DAC_DPZ BIT(0)
|
||||
#define RST_ADC_DPZ BIT(1)
|
||||
#define AUD96P22_I2S1_CONFIG_0 0x03
|
||||
#define I2S1_MS_MODE BIT(3)
|
||||
#define I2S1_MODE_MASK 0x7
|
||||
#define I2S1_MODE_RIGHT_J 0x0
|
||||
#define I2S1_MODE_I2S 0x1
|
||||
#define I2S1_MODE_LEFT_J 0x2
|
||||
#define AUD96P22_PD_0 0x15
|
||||
#define AUD96P22_PD_1 0x16
|
||||
#define AUD96P22_PD_3 0x18
|
||||
#define AUD96P22_PD_4 0x19
|
||||
#define AUD96P22_MUTE_0 0x1d
|
||||
#define AUD96P22_MUTE_2 0x1f
|
||||
#define AUD96P22_MUTE_4 0x21
|
||||
#define AUD96P22_RECVOL_0 0x24
|
||||
#define AUD96P22_RECVOL_1 0x25
|
||||
#define AUD96P22_PGA1VOL_0 0x26
|
||||
#define AUD96P22_PGA1VOL_1 0x27
|
||||
#define AUD96P22_LMVOL_0 0x34
|
||||
#define AUD96P22_LMVOL_1 0x35
|
||||
#define AUD96P22_HS1VOL_0 0x38
|
||||
#define AUD96P22_HS1VOL_1 0x39
|
||||
#define AUD96P22_PGA1SEL_0 0x47
|
||||
#define AUD96P22_PGA1SEL_1 0x48
|
||||
#define AUD96P22_LDR1SEL_0 0x59
|
||||
#define AUD96P22_LDR1SEL_1 0x60
|
||||
#define AUD96P22_LDR2SEL_0 0x5d
|
||||
#define AUD96P22_REG_MAX 0xfb
|
||||
|
||||
struct aud96p22_priv {
|
||||
struct regmap *regmap;
|
||||
};
|
||||
|
||||
static int aud96p22_adc_event(struct snd_soc_dapm_widget *w,
|
||||
struct snd_kcontrol *kcontrol, int event)
|
||||
{
|
||||
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
|
||||
struct aud96p22_priv *priv = snd_soc_component_get_drvdata(component);
|
||||
struct regmap *regmap = priv->regmap;
|
||||
|
||||
if (event != SND_SOC_DAPM_POST_PMU)
|
||||
return -EINVAL;
|
||||
|
||||
/* Assert/de-assert the bit to reset ADC data path */
|
||||
regmap_update_bits(regmap, AUD96P22_RESET, RST_ADC_DPZ, 0);
|
||||
regmap_update_bits(regmap, AUD96P22_RESET, RST_ADC_DPZ, RST_ADC_DPZ);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int aud96p22_dac_event(struct snd_soc_dapm_widget *w,
|
||||
struct snd_kcontrol *kcontrol, int event)
|
||||
{
|
||||
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
|
||||
struct aud96p22_priv *priv = snd_soc_component_get_drvdata(component);
|
||||
struct regmap *regmap = priv->regmap;
|
||||
|
||||
if (event != SND_SOC_DAPM_POST_PMU)
|
||||
return -EINVAL;
|
||||
|
||||
/* Assert/de-assert the bit to reset DAC data path */
|
||||
regmap_update_bits(regmap, AUD96P22_RESET, RST_DAC_DPZ, 0);
|
||||
regmap_update_bits(regmap, AUD96P22_RESET, RST_DAC_DPZ, RST_DAC_DPZ);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const DECLARE_TLV_DB_SCALE(lm_tlv, -11550, 50, 0);
|
||||
static const DECLARE_TLV_DB_SCALE(hs_tlv, -3900, 300, 0);
|
||||
static const DECLARE_TLV_DB_SCALE(rec_tlv, -9550, 50, 0);
|
||||
static const DECLARE_TLV_DB_SCALE(pga_tlv, -1800, 100, 0);
|
||||
|
||||
static const struct snd_kcontrol_new aud96p22_snd_controls[] = {
|
||||
/* Volume control */
|
||||
SOC_DOUBLE_R_TLV("Master Playback Volume", AUD96P22_LMVOL_0,
|
||||
AUD96P22_LMVOL_1, 0, 0xff, 0, lm_tlv),
|
||||
SOC_DOUBLE_R_TLV("Headphone Volume", AUD96P22_HS1VOL_0,
|
||||
AUD96P22_HS1VOL_1, 0, 0xf, 0, hs_tlv),
|
||||
SOC_DOUBLE_R_TLV("Master Capture Volume", AUD96P22_RECVOL_0,
|
||||
AUD96P22_RECVOL_1, 0, 0xff, 0, rec_tlv),
|
||||
SOC_DOUBLE_R_TLV("Analogue Capture Volume", AUD96P22_PGA1VOL_0,
|
||||
AUD96P22_PGA1VOL_1, 0, 0x37, 0, pga_tlv),
|
||||
|
||||
/* Mute control */
|
||||
SOC_DOUBLE("Master Playback Switch", AUD96P22_MUTE_2, 0, 1, 1, 1),
|
||||
SOC_DOUBLE("Headphone Switch", AUD96P22_MUTE_2, 4, 5, 1, 1),
|
||||
SOC_DOUBLE("Line Out Switch", AUD96P22_MUTE_4, 0, 1, 1, 1),
|
||||
SOC_DOUBLE("Speaker Switch", AUD96P22_MUTE_4, 2, 3, 1, 1),
|
||||
SOC_DOUBLE("Master Capture Switch", AUD96P22_MUTE_0, 0, 1, 1, 1),
|
||||
SOC_DOUBLE("Analogue Capture Switch", AUD96P22_MUTE_0, 2, 3, 1, 1),
|
||||
};
|
||||
|
||||
/* Input mux kcontrols */
|
||||
static const unsigned int ain_mux_values[] = {
|
||||
0, 1, 3, 4, 5,
|
||||
};
|
||||
|
||||
static const char * const ainl_mux_texts[] = {
|
||||
"AINL1 differential",
|
||||
"AINL1 single-ended",
|
||||
"AINL3 single-ended",
|
||||
"AINL2 differential",
|
||||
"AINL2 single-ended",
|
||||
};
|
||||
|
||||
static const char * const ainr_mux_texts[] = {
|
||||
"AINR1 differential",
|
||||
"AINR1 single-ended",
|
||||
"AINR3 single-ended",
|
||||
"AINR2 differential",
|
||||
"AINR2 single-ended",
|
||||
};
|
||||
|
||||
static SOC_VALUE_ENUM_SINGLE_DECL(ainl_mux_enum, AUD96P22_PGA1SEL_0,
|
||||
0, 0x7, ainl_mux_texts, ain_mux_values);
|
||||
static SOC_VALUE_ENUM_SINGLE_DECL(ainr_mux_enum, AUD96P22_PGA1SEL_1,
|
||||
0, 0x7, ainr_mux_texts, ain_mux_values);
|
||||
|
||||
static const struct snd_kcontrol_new ainl_mux_kcontrol =
|
||||
SOC_DAPM_ENUM("AINL Mux", ainl_mux_enum);
|
||||
static const struct snd_kcontrol_new ainr_mux_kcontrol =
|
||||
SOC_DAPM_ENUM("AINR Mux", ainr_mux_enum);
|
||||
|
||||
/* Output mixer kcontrols */
|
||||
static const struct snd_kcontrol_new ld1_left_kcontrols[] = {
|
||||
SOC_DAPM_SINGLE("DACL LD1L Switch", AUD96P22_LDR1SEL_0, 0, 1, 0),
|
||||
SOC_DAPM_SINGLE("AINL LD1L Switch", AUD96P22_LDR1SEL_0, 1, 1, 0),
|
||||
SOC_DAPM_SINGLE("AINR LD1L Switch", AUD96P22_LDR1SEL_0, 2, 1, 0),
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new ld1_right_kcontrols[] = {
|
||||
SOC_DAPM_SINGLE("DACR LD1R Switch", AUD96P22_LDR1SEL_1, 8, 1, 0),
|
||||
SOC_DAPM_SINGLE("AINR LD1R Switch", AUD96P22_LDR1SEL_1, 9, 1, 0),
|
||||
SOC_DAPM_SINGLE("AINL LD1R Switch", AUD96P22_LDR1SEL_1, 10, 1, 0),
|
||||
};
|
||||
|
||||
static const struct snd_kcontrol_new ld2_kcontrols[] = {
|
||||
SOC_DAPM_SINGLE("DACL LD2 Switch", AUD96P22_LDR2SEL_0, 0, 1, 0),
|
||||
SOC_DAPM_SINGLE("AINL LD2 Switch", AUD96P22_LDR2SEL_0, 1, 1, 0),
|
||||
SOC_DAPM_SINGLE("DACR LD2 Switch", AUD96P22_LDR2SEL_0, 2, 1, 0),
|
||||
};
|
||||
|
||||
static const struct snd_soc_dapm_widget aud96p22_dapm_widgets[] = {
|
||||
/* Overall power bit */
|
||||
SND_SOC_DAPM_SUPPLY("POWER", AUD96P22_PD_0, 0, 0, NULL, 0),
|
||||
|
||||
/* Input pins */
|
||||
SND_SOC_DAPM_INPUT("AINL1P"),
|
||||
SND_SOC_DAPM_INPUT("AINL2P"),
|
||||
SND_SOC_DAPM_INPUT("AINL3"),
|
||||
SND_SOC_DAPM_INPUT("AINL1N"),
|
||||
SND_SOC_DAPM_INPUT("AINL2N"),
|
||||
SND_SOC_DAPM_INPUT("AINR2N"),
|
||||
SND_SOC_DAPM_INPUT("AINR1N"),
|
||||
SND_SOC_DAPM_INPUT("AINR3"),
|
||||
SND_SOC_DAPM_INPUT("AINR2P"),
|
||||
SND_SOC_DAPM_INPUT("AINR1P"),
|
||||
|
||||
/* Input muxes */
|
||||
SND_SOC_DAPM_MUX("AINLMUX", AUD96P22_PD_1, 2, 0, &ainl_mux_kcontrol),
|
||||
SND_SOC_DAPM_MUX("AINRMUX", AUD96P22_PD_1, 3, 0, &ainr_mux_kcontrol),
|
||||
|
||||
/* ADCs */
|
||||
SND_SOC_DAPM_ADC_E("ADCL", "Capture Left", AUD96P22_PD_1, 0, 0,
|
||||
aud96p22_adc_event, SND_SOC_DAPM_POST_PMU),
|
||||
SND_SOC_DAPM_ADC_E("ADCR", "Capture Right", AUD96P22_PD_1, 1, 0,
|
||||
aud96p22_adc_event, SND_SOC_DAPM_POST_PMU),
|
||||
|
||||
/* DACs */
|
||||
SND_SOC_DAPM_DAC_E("DACL", "Playback Left", AUD96P22_PD_3, 0, 0,
|
||||
aud96p22_dac_event, SND_SOC_DAPM_POST_PMU),
|
||||
SND_SOC_DAPM_DAC_E("DACR", "Playback Right", AUD96P22_PD_3, 1, 0,
|
||||
aud96p22_dac_event, SND_SOC_DAPM_POST_PMU),
|
||||
|
||||
/* Output mixers */
|
||||
SND_SOC_DAPM_MIXER("LD1L", AUD96P22_PD_3, 6, 0, ld1_left_kcontrols,
|
||||
ARRAY_SIZE(ld1_left_kcontrols)),
|
||||
SND_SOC_DAPM_MIXER("LD1R", AUD96P22_PD_3, 7, 0, ld1_right_kcontrols,
|
||||
ARRAY_SIZE(ld1_right_kcontrols)),
|
||||
SND_SOC_DAPM_MIXER("LD2", AUD96P22_PD_4, 2, 0, ld2_kcontrols,
|
||||
ARRAY_SIZE(ld2_kcontrols)),
|
||||
|
||||
/* Headset power switch */
|
||||
SND_SOC_DAPM_SUPPLY("HS1L", AUD96P22_PD_3, 4, 0, NULL, 0),
|
||||
SND_SOC_DAPM_SUPPLY("HS1R", AUD96P22_PD_3, 5, 0, NULL, 0),
|
||||
|
||||
/* Output pins */
|
||||
SND_SOC_DAPM_OUTPUT("HSOUTL"),
|
||||
SND_SOC_DAPM_OUTPUT("LINEOUTL"),
|
||||
SND_SOC_DAPM_OUTPUT("LINEOUTMP"),
|
||||
SND_SOC_DAPM_OUTPUT("LINEOUTMN"),
|
||||
SND_SOC_DAPM_OUTPUT("LINEOUTR"),
|
||||
SND_SOC_DAPM_OUTPUT("HSOUTR"),
|
||||
};
|
||||
|
||||
static const struct snd_soc_dapm_route aud96p22_dapm_routes[] = {
|
||||
{ "AINLMUX", "AINL1 differential", "AINL1N" },
|
||||
{ "AINLMUX", "AINL1 single-ended", "AINL1P" },
|
||||
{ "AINLMUX", "AINL3 single-ended", "AINL3" },
|
||||
{ "AINLMUX", "AINL2 differential", "AINL2N" },
|
||||
{ "AINLMUX", "AINL2 single-ended", "AINL2P" },
|
||||
|
||||
{ "AINRMUX", "AINR1 differential", "AINR1N" },
|
||||
{ "AINRMUX", "AINR1 single-ended", "AINR1P" },
|
||||
{ "AINRMUX", "AINR3 single-ended", "AINR3" },
|
||||
{ "AINRMUX", "AINR2 differential", "AINR2N" },
|
||||
{ "AINRMUX", "AINR2 single-ended", "AINR2P" },
|
||||
|
||||
{ "ADCL", NULL, "AINLMUX" },
|
||||
{ "ADCR", NULL, "AINRMUX" },
|
||||
|
||||
{ "ADCL", NULL, "POWER" },
|
||||
{ "ADCR", NULL, "POWER" },
|
||||
{ "DACL", NULL, "POWER" },
|
||||
{ "DACR", NULL, "POWER" },
|
||||
|
||||
{ "LD1L", "DACL LD1L Switch", "DACL" },
|
||||
{ "LD1L", "AINL LD1L Switch", "AINLMUX" },
|
||||
{ "LD1L", "AINR LD1L Switch", "AINRMUX" },
|
||||
|
||||
{ "LD1R", "DACR LD1R Switch", "DACR" },
|
||||
{ "LD1R", "AINR LD1R Switch", "AINRMUX" },
|
||||
{ "LD1R", "AINL LD1R Switch", "AINLMUX" },
|
||||
|
||||
{ "LD2", "DACL LD2 Switch", "DACL" },
|
||||
{ "LD2", "AINL LD2 Switch", "AINLMUX" },
|
||||
{ "LD2", "DACR LD2 Switch", "DACR" },
|
||||
|
||||
{ "HSOUTL", NULL, "LD1L" },
|
||||
{ "HSOUTR", NULL, "LD1R" },
|
||||
{ "HSOUTL", NULL, "HS1L" },
|
||||
{ "HSOUTR", NULL, "HS1R" },
|
||||
|
||||
{ "LINEOUTL", NULL, "LD1L" },
|
||||
{ "LINEOUTR", NULL, "LD1R" },
|
||||
|
||||
{ "LINEOUTMP", NULL, "LD2" },
|
||||
{ "LINEOUTMN", NULL, "LD2" },
|
||||
};
|
||||
|
||||
static const struct snd_soc_component_driver aud96p22_driver = {
|
||||
.controls = aud96p22_snd_controls,
|
||||
.num_controls = ARRAY_SIZE(aud96p22_snd_controls),
|
||||
.dapm_widgets = aud96p22_dapm_widgets,
|
||||
.num_dapm_widgets = ARRAY_SIZE(aud96p22_dapm_widgets),
|
||||
.dapm_routes = aud96p22_dapm_routes,
|
||||
.num_dapm_routes = ARRAY_SIZE(aud96p22_dapm_routes),
|
||||
.idle_bias_on = 1,
|
||||
.use_pmdown_time = 1,
|
||||
.endianness = 1,
|
||||
.non_legacy_dai_naming = 1,
|
||||
};
|
||||
|
||||
static int aud96p22_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
|
||||
{
|
||||
struct aud96p22_priv *priv = snd_soc_component_get_drvdata(dai->component);
|
||||
struct regmap *regmap = priv->regmap;
|
||||
unsigned int val;
|
||||
|
||||
/* Master/slave mode */
|
||||
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
||||
case SND_SOC_DAIFMT_CBS_CFS:
|
||||
val = 0;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_CBM_CFM:
|
||||
val = I2S1_MS_MODE;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regmap_update_bits(regmap, AUD96P22_I2S1_CONFIG_0, I2S1_MS_MODE, val);
|
||||
|
||||
/* Audio format */
|
||||
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
||||
case SND_SOC_DAIFMT_RIGHT_J:
|
||||
val = I2S1_MODE_RIGHT_J;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_I2S:
|
||||
val = I2S1_MODE_I2S;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_LEFT_J:
|
||||
val = I2S1_MODE_LEFT_J;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regmap_update_bits(regmap, AUD96P22_I2S1_CONFIG_0, I2S1_MODE_MASK, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct snd_soc_dai_ops aud96p22_dai_ops = {
|
||||
.set_fmt = aud96p22_set_fmt,
|
||||
};
|
||||
|
||||
#define AUD96P22_RATES SNDRV_PCM_RATE_8000_192000
|
||||
#define AUD96P22_FORMATS (\
|
||||
SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
|
||||
SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE)
|
||||
|
||||
static struct snd_soc_dai_driver aud96p22_dai = {
|
||||
.name = "aud96p22-dai",
|
||||
.playback = {
|
||||
.stream_name = "Playback",
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = AUD96P22_RATES,
|
||||
.formats = AUD96P22_FORMATS,
|
||||
},
|
||||
.capture = {
|
||||
.stream_name = "Capture",
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = AUD96P22_RATES,
|
||||
.formats = AUD96P22_FORMATS,
|
||||
},
|
||||
.ops = &aud96p22_dai_ops,
|
||||
};
|
||||
|
||||
static const struct regmap_config aud96p22_regmap = {
|
||||
.reg_bits = 8,
|
||||
.val_bits = 8,
|
||||
.max_register = AUD96P22_REG_MAX,
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
};
|
||||
|
||||
static int aud96p22_i2c_probe(struct i2c_client *i2c,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
struct device *dev = &i2c->dev;
|
||||
struct aud96p22_priv *priv;
|
||||
int ret;
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (priv == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->regmap = devm_regmap_init_i2c(i2c, &aud96p22_regmap);
|
||||
if (IS_ERR(priv->regmap)) {
|
||||
ret = PTR_ERR(priv->regmap);
|
||||
dev_err(dev, "failed to init i2c regmap: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
i2c_set_clientdata(i2c, priv);
|
||||
|
||||
ret = devm_snd_soc_register_component(dev, &aud96p22_driver, &aud96p22_dai, 1);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to register component: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int aud96p22_i2c_remove(struct i2c_client *i2c)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id aud96p22_dt_ids[] = {
|
||||
{ .compatible = "zte,zx-aud96p22", },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, aud96p22_dt_ids);
|
||||
|
||||
static struct i2c_driver aud96p22_i2c_driver = {
|
||||
.driver = {
|
||||
.name = "zx_aud96p22",
|
||||
.of_match_table = aud96p22_dt_ids,
|
||||
},
|
||||
.probe = aud96p22_i2c_probe,
|
||||
.remove = aud96p22_i2c_remove,
|
||||
};
|
||||
module_i2c_driver(aud96p22_i2c_driver);
|
||||
|
||||
MODULE_DESCRIPTION("ZTE ASoC AUD96P22 CODEC driver");
|
||||
MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
|
||||
MODULE_LICENSE("GPL v2");
|
|
@ -1,21 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
config SND_SOC_SIRF
|
||||
tristate "SoC Audio for the SiRF SoC chips"
|
||||
depends on ARCH_SIRF || COMPILE_TEST
|
||||
select SND_SOC_GENERIC_DMAENGINE_PCM
|
||||
|
||||
config SND_SOC_SIRF_AUDIO
|
||||
tristate "SoC Audio support for SiRF internal audio codec"
|
||||
depends on SND_SOC_SIRF
|
||||
select SND_SOC_SIRF_AUDIO_CODEC
|
||||
select SND_SOC_SIRF_AUDIO_PORT
|
||||
|
||||
config SND_SOC_SIRF_AUDIO_PORT
|
||||
select REGMAP_MMIO
|
||||
tristate
|
||||
|
||||
config SND_SOC_SIRF_USP
|
||||
tristate "SoC Audio (I2S protocol) for SiRF SoC USP interface"
|
||||
depends on SND_SOC_SIRF
|
||||
select REGMAP_MMIO
|
||||
tristate
|
|
@ -1,8 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
snd-soc-sirf-audio-objs := sirf-audio.o
|
||||
snd-soc-sirf-audio-port-objs := sirf-audio-port.o
|
||||
snd-soc-sirf-usp-objs := sirf-usp.o
|
||||
|
||||
obj-$(CONFIG_SND_SOC_SIRF_AUDIO) += snd-soc-sirf-audio.o
|
||||
obj-$(CONFIG_SND_SOC_SIRF_AUDIO_PORT) += snd-soc-sirf-audio-port.o
|
||||
obj-$(CONFIG_SND_SOC_SIRF_USP) += snd-soc-sirf-usp.o
|
|
@ -1,86 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* SiRF Audio port driver
|
||||
*
|
||||
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <sound/soc.h>
|
||||
#include <sound/dmaengine_pcm.h>
|
||||
|
||||
struct sirf_audio_port {
|
||||
struct regmap *regmap;
|
||||
struct snd_dmaengine_dai_dma_data playback_dma_data;
|
||||
struct snd_dmaengine_dai_dma_data capture_dma_data;
|
||||
};
|
||||
|
||||
|
||||
static int sirf_audio_port_dai_probe(struct snd_soc_dai *dai)
|
||||
{
|
||||
struct sirf_audio_port *port = snd_soc_dai_get_drvdata(dai);
|
||||
|
||||
snd_soc_dai_init_dma_data(dai, &port->playback_dma_data,
|
||||
&port->capture_dma_data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct snd_soc_dai_driver sirf_audio_port_dai = {
|
||||
.probe = sirf_audio_port_dai_probe,
|
||||
.name = "sirf-audio-port",
|
||||
.id = 0,
|
||||
.playback = {
|
||||
.channels_min = 2,
|
||||
.channels_max = 2,
|
||||
.rates = SNDRV_PCM_RATE_48000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
||||
},
|
||||
.capture = {
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = SNDRV_PCM_RATE_48000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct snd_soc_component_driver sirf_audio_port_component = {
|
||||
.name = "sirf-audio-port",
|
||||
};
|
||||
|
||||
static int sirf_audio_port_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct sirf_audio_port *port;
|
||||
|
||||
port = devm_kzalloc(&pdev->dev,
|
||||
sizeof(struct sirf_audio_port), GFP_KERNEL);
|
||||
if (!port)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = devm_snd_soc_register_component(&pdev->dev,
|
||||
&sirf_audio_port_component, &sirf_audio_port_dai, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
platform_set_drvdata(pdev, port);
|
||||
return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
|
||||
}
|
||||
|
||||
static const struct of_device_id sirf_audio_port_of_match[] = {
|
||||
{ .compatible = "sirf,audio-port", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sirf_audio_port_of_match);
|
||||
|
||||
static struct platform_driver sirf_audio_port_driver = {
|
||||
.driver = {
|
||||
.name = "sirf-audio-port",
|
||||
.of_match_table = sirf_audio_port_of_match,
|
||||
},
|
||||
.probe = sirf_audio_port_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(sirf_audio_port_driver);
|
||||
|
||||
MODULE_DESCRIPTION("SiRF Audio Port driver");
|
||||
MODULE_AUTHOR("RongJun Ying <Rongjun.Ying@csr.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
|
@ -1,160 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* SiRF audio card driver
|
||||
*
|
||||
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <sound/core.h>
|
||||
#include <sound/pcm.h>
|
||||
#include <sound/soc.h>
|
||||
|
||||
struct sirf_audio_card {
|
||||
unsigned int gpio_hp_pa;
|
||||
unsigned int gpio_spk_pa;
|
||||
};
|
||||
|
||||
static int sirf_audio_hp_event(struct snd_soc_dapm_widget *w,
|
||||
struct snd_kcontrol *ctrl, int event)
|
||||
{
|
||||
struct snd_soc_dapm_context *dapm = w->dapm;
|
||||
struct snd_soc_card *card = dapm->card;
|
||||
struct sirf_audio_card *sirf_audio_card = snd_soc_card_get_drvdata(card);
|
||||
int on = !SND_SOC_DAPM_EVENT_OFF(event);
|
||||
|
||||
if (gpio_is_valid(sirf_audio_card->gpio_hp_pa))
|
||||
gpio_set_value(sirf_audio_card->gpio_hp_pa, on);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sirf_audio_spk_event(struct snd_soc_dapm_widget *w,
|
||||
struct snd_kcontrol *ctrl, int event)
|
||||
{
|
||||
struct snd_soc_dapm_context *dapm = w->dapm;
|
||||
struct snd_soc_card *card = dapm->card;
|
||||
struct sirf_audio_card *sirf_audio_card = snd_soc_card_get_drvdata(card);
|
||||
int on = !SND_SOC_DAPM_EVENT_OFF(event);
|
||||
|
||||
if (gpio_is_valid(sirf_audio_card->gpio_spk_pa))
|
||||
gpio_set_value(sirf_audio_card->gpio_spk_pa, on);
|
||||
|
||||
return 0;
|
||||
}
|
||||
static const struct snd_soc_dapm_widget sirf_audio_dapm_widgets[] = {
|
||||
SND_SOC_DAPM_HP("Hp", sirf_audio_hp_event),
|
||||
SND_SOC_DAPM_SPK("Ext Spk", sirf_audio_spk_event),
|
||||
SND_SOC_DAPM_MIC("Ext Mic", NULL),
|
||||
};
|
||||
|
||||
static const struct snd_soc_dapm_route intercon[] = {
|
||||
{"Hp", NULL, "HPOUTL"},
|
||||
{"Hp", NULL, "HPOUTR"},
|
||||
{"Ext Spk", NULL, "SPKOUT"},
|
||||
{"MICIN1", NULL, "Mic Bias"},
|
||||
{"Mic Bias", NULL, "Ext Mic"},
|
||||
};
|
||||
|
||||
/* Digital audio interface glue - connects codec <--> CPU */
|
||||
SND_SOC_DAILINK_DEFS(sirf,
|
||||
DAILINK_COMP_ARRAY(COMP_EMPTY()),
|
||||
DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "sirf-audio-codec")),
|
||||
DAILINK_COMP_ARRAY(COMP_EMPTY()));
|
||||
|
||||
static struct snd_soc_dai_link sirf_audio_dai_link[] = {
|
||||
{
|
||||
.name = "SiRF audio card",
|
||||
.stream_name = "SiRF audio HiFi",
|
||||
SND_SOC_DAILINK_REG(sirf),
|
||||
},
|
||||
};
|
||||
|
||||
/* Audio machine driver */
|
||||
static struct snd_soc_card snd_soc_sirf_audio_card = {
|
||||
.name = "SiRF audio card",
|
||||
.owner = THIS_MODULE,
|
||||
.dai_link = sirf_audio_dai_link,
|
||||
.num_links = ARRAY_SIZE(sirf_audio_dai_link),
|
||||
.dapm_widgets = sirf_audio_dapm_widgets,
|
||||
.num_dapm_widgets = ARRAY_SIZE(sirf_audio_dapm_widgets),
|
||||
.dapm_routes = intercon,
|
||||
.num_dapm_routes = ARRAY_SIZE(intercon),
|
||||
};
|
||||
|
||||
static int sirf_audio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct snd_soc_card *card = &snd_soc_sirf_audio_card;
|
||||
struct sirf_audio_card *sirf_audio_card;
|
||||
int ret;
|
||||
|
||||
sirf_audio_card = devm_kzalloc(&pdev->dev, sizeof(struct sirf_audio_card),
|
||||
GFP_KERNEL);
|
||||
if (sirf_audio_card == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
sirf_audio_dai_link[0].cpus->of_node =
|
||||
of_parse_phandle(pdev->dev.of_node, "sirf,audio-platform", 0);
|
||||
sirf_audio_dai_link[0].platforms->of_node =
|
||||
of_parse_phandle(pdev->dev.of_node, "sirf,audio-platform", 0);
|
||||
sirf_audio_dai_link[0].codecs->of_node =
|
||||
of_parse_phandle(pdev->dev.of_node, "sirf,audio-codec", 0);
|
||||
sirf_audio_card->gpio_spk_pa = of_get_named_gpio(pdev->dev.of_node,
|
||||
"spk-pa-gpios", 0);
|
||||
sirf_audio_card->gpio_hp_pa = of_get_named_gpio(pdev->dev.of_node,
|
||||
"hp-pa-gpios", 0);
|
||||
if (gpio_is_valid(sirf_audio_card->gpio_spk_pa)) {
|
||||
ret = devm_gpio_request_one(&pdev->dev,
|
||||
sirf_audio_card->gpio_spk_pa,
|
||||
GPIOF_OUT_INIT_LOW, "SPA_PA_SD");
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev,
|
||||
"Failed to request GPIO_%d for reset: %d\n",
|
||||
sirf_audio_card->gpio_spk_pa, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
if (gpio_is_valid(sirf_audio_card->gpio_hp_pa)) {
|
||||
ret = devm_gpio_request_one(&pdev->dev,
|
||||
sirf_audio_card->gpio_hp_pa,
|
||||
GPIOF_OUT_INIT_LOW, "HP_PA_SD");
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev,
|
||||
"Failed to request GPIO_%d for reset: %d\n",
|
||||
sirf_audio_card->gpio_hp_pa, ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
card->dev = &pdev->dev;
|
||||
snd_soc_card_set_drvdata(card, sirf_audio_card);
|
||||
|
||||
ret = devm_snd_soc_register_card(&pdev->dev, card);
|
||||
if (ret)
|
||||
dev_err(&pdev->dev, "snd_soc_register_card() failed:%d\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id sirf_audio_of_match[] = {
|
||||
{.compatible = "sirf,sirf-audio-card", },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sirf_audio_of_match);
|
||||
|
||||
static struct platform_driver sirf_audio_driver = {
|
||||
.driver = {
|
||||
.name = "sirf-audio-card",
|
||||
.pm = &snd_soc_pm_ops,
|
||||
.of_match_table = sirf_audio_of_match,
|
||||
},
|
||||
.probe = sirf_audio_probe,
|
||||
};
|
||||
module_platform_driver(sirf_audio_driver);
|
||||
|
||||
MODULE_AUTHOR("RongJun Ying <RongJun.Ying@csr.com>");
|
||||
MODULE_DESCRIPTION("ALSA SoC SIRF audio card driver");
|
||||
MODULE_LICENSE("GPL v2");
|
|
@ -1,435 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* SiRF USP in I2S/DSP mode
|
||||
*
|
||||
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <sound/soc.h>
|
||||
#include <sound/pcm_params.h>
|
||||
#include <sound/dmaengine_pcm.h>
|
||||
|
||||
#include "sirf-usp.h"
|
||||
|
||||
struct sirf_usp {
|
||||
struct regmap *regmap;
|
||||
struct clk *clk;
|
||||
u32 mode1_reg;
|
||||
u32 mode2_reg;
|
||||
int daifmt_format;
|
||||
struct snd_dmaengine_dai_dma_data playback_dma_data;
|
||||
struct snd_dmaengine_dai_dma_data capture_dma_data;
|
||||
};
|
||||
|
||||
static void sirf_usp_tx_enable(struct sirf_usp *usp)
|
||||
{
|
||||
regmap_update_bits(usp->regmap, USP_TX_FIFO_OP,
|
||||
USP_TX_FIFO_RESET, USP_TX_FIFO_RESET);
|
||||
regmap_write(usp->regmap, USP_TX_FIFO_OP, 0);
|
||||
|
||||
regmap_update_bits(usp->regmap, USP_TX_FIFO_OP,
|
||||
USP_TX_FIFO_START, USP_TX_FIFO_START);
|
||||
|
||||
regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
|
||||
USP_TX_ENA, USP_TX_ENA);
|
||||
}
|
||||
|
||||
static void sirf_usp_tx_disable(struct sirf_usp *usp)
|
||||
{
|
||||
regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
|
||||
USP_TX_ENA, ~USP_TX_ENA);
|
||||
/* FIFO stop */
|
||||
regmap_write(usp->regmap, USP_TX_FIFO_OP, 0);
|
||||
}
|
||||
|
||||
static void sirf_usp_rx_enable(struct sirf_usp *usp)
|
||||
{
|
||||
regmap_update_bits(usp->regmap, USP_RX_FIFO_OP,
|
||||
USP_RX_FIFO_RESET, USP_RX_FIFO_RESET);
|
||||
regmap_write(usp->regmap, USP_RX_FIFO_OP, 0);
|
||||
|
||||
regmap_update_bits(usp->regmap, USP_RX_FIFO_OP,
|
||||
USP_RX_FIFO_START, USP_RX_FIFO_START);
|
||||
|
||||
regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
|
||||
USP_RX_ENA, USP_RX_ENA);
|
||||
}
|
||||
|
||||
static void sirf_usp_rx_disable(struct sirf_usp *usp)
|
||||
{
|
||||
regmap_update_bits(usp->regmap, USP_TX_RX_ENABLE,
|
||||
USP_RX_ENA, ~USP_RX_ENA);
|
||||
/* FIFO stop */
|
||||
regmap_write(usp->regmap, USP_RX_FIFO_OP, 0);
|
||||
}
|
||||
|
||||
static int sirf_usp_pcm_dai_probe(struct snd_soc_dai *dai)
|
||||
{
|
||||
struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
|
||||
|
||||
snd_soc_dai_init_dma_data(dai, &usp->playback_dma_data,
|
||||
&usp->capture_dma_data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sirf_usp_pcm_set_dai_fmt(struct snd_soc_dai *dai,
|
||||
unsigned int fmt)
|
||||
{
|
||||
struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
|
||||
|
||||
/* set master/slave audio interface */
|
||||
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
||||
case SND_SOC_DAIFMT_CBM_CFM:
|
||||
break;
|
||||
default:
|
||||
dev_err(dai->dev, "Only CBM and CFM supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
||||
case SND_SOC_DAIFMT_I2S:
|
||||
case SND_SOC_DAIFMT_DSP_A:
|
||||
usp->daifmt_format = (fmt & SND_SOC_DAIFMT_FORMAT_MASK);
|
||||
break;
|
||||
default:
|
||||
dev_err(dai->dev, "Only I2S and DSP_A format supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
|
||||
case SND_SOC_DAIFMT_NB_NF:
|
||||
break;
|
||||
case SND_SOC_DAIFMT_IB_NF:
|
||||
usp->daifmt_format |= (fmt & SND_SOC_DAIFMT_INV_MASK);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sirf_usp_i2s_init(struct sirf_usp *usp)
|
||||
{
|
||||
/* Configure RISC mode */
|
||||
regmap_update_bits(usp->regmap, USP_RISC_DSP_MODE,
|
||||
USP_RISC_DSP_SEL, ~USP_RISC_DSP_SEL);
|
||||
|
||||
/*
|
||||
* Configure DMA IO Length register
|
||||
* Set no limit, USP can receive data continuously until it is diabled
|
||||
*/
|
||||
regmap_write(usp->regmap, USP_TX_DMA_IO_LEN, 0);
|
||||
regmap_write(usp->regmap, USP_RX_DMA_IO_LEN, 0);
|
||||
|
||||
/* Configure Mode2 register */
|
||||
regmap_write(usp->regmap, USP_MODE2, (1 << USP_RXD_DELAY_LEN_OFFSET) |
|
||||
(0 << USP_TXD_DELAY_LEN_OFFSET) |
|
||||
USP_TFS_CLK_SLAVE_MODE | USP_RFS_CLK_SLAVE_MODE);
|
||||
|
||||
/* Configure Mode1 register */
|
||||
regmap_write(usp->regmap, USP_MODE1,
|
||||
USP_SYNC_MODE | USP_EN | USP_TXD_ACT_EDGE_FALLING |
|
||||
USP_RFS_ACT_LEVEL_LOGIC1 | USP_TFS_ACT_LEVEL_LOGIC1 |
|
||||
USP_TX_UFLOW_REPEAT_ZERO | USP_CLOCK_MODE_SLAVE);
|
||||
|
||||
/* Configure RX DMA IO Control register */
|
||||
regmap_write(usp->regmap, USP_RX_DMA_IO_CTRL, 0);
|
||||
|
||||
/* Congiure RX FIFO Control register */
|
||||
regmap_write(usp->regmap, USP_RX_FIFO_CTRL,
|
||||
(USP_RX_FIFO_THRESHOLD << USP_RX_FIFO_THD_OFFSET) |
|
||||
(USP_TX_RX_FIFO_WIDTH_DWORD << USP_RX_FIFO_WIDTH_OFFSET));
|
||||
|
||||
/* Congiure RX FIFO Level Check register */
|
||||
regmap_write(usp->regmap, USP_RX_FIFO_LEVEL_CHK,
|
||||
RX_FIFO_SC(0x04) | RX_FIFO_LC(0x0E) | RX_FIFO_HC(0x1B));
|
||||
|
||||
/* Configure TX DMA IO Control register*/
|
||||
regmap_write(usp->regmap, USP_TX_DMA_IO_CTRL, 0);
|
||||
|
||||
/* Configure TX FIFO Control register */
|
||||
regmap_write(usp->regmap, USP_TX_FIFO_CTRL,
|
||||
(USP_TX_FIFO_THRESHOLD << USP_TX_FIFO_THD_OFFSET) |
|
||||
(USP_TX_RX_FIFO_WIDTH_DWORD << USP_TX_FIFO_WIDTH_OFFSET));
|
||||
/* Congiure TX FIFO Level Check register */
|
||||
regmap_write(usp->regmap, USP_TX_FIFO_LEVEL_CHK,
|
||||
TX_FIFO_SC(0x1B) | TX_FIFO_LC(0x0E) | TX_FIFO_HC(0x04));
|
||||
}
|
||||
|
||||
static int sirf_usp_pcm_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
|
||||
{
|
||||
struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
|
||||
u32 data_len, frame_len, shifter_len;
|
||||
|
||||
switch (params_format(params)) {
|
||||
case SNDRV_PCM_FORMAT_S16_LE:
|
||||
data_len = 16;
|
||||
frame_len = 16;
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S24_LE:
|
||||
data_len = 24;
|
||||
frame_len = 32;
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S24_3LE:
|
||||
data_len = 24;
|
||||
frame_len = 24;
|
||||
break;
|
||||
default:
|
||||
dev_err(dai->dev, "Format unsupported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
shifter_len = data_len;
|
||||
|
||||
switch (usp->daifmt_format & SND_SOC_DAIFMT_FORMAT_MASK) {
|
||||
case SND_SOC_DAIFMT_I2S:
|
||||
regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL,
|
||||
USP_I2S_SYNC_CHG, USP_I2S_SYNC_CHG);
|
||||
break;
|
||||
case SND_SOC_DAIFMT_DSP_A:
|
||||
regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL,
|
||||
USP_I2S_SYNC_CHG, 0);
|
||||
frame_len = data_len * params_channels(params);
|
||||
data_len = frame_len;
|
||||
break;
|
||||
default:
|
||||
dev_err(dai->dev, "Only support I2S and DSP_A mode\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (usp->daifmt_format & SND_SOC_DAIFMT_INV_MASK) {
|
||||
case SND_SOC_DAIFMT_NB_NF:
|
||||
break;
|
||||
case SND_SOC_DAIFMT_IB_NF:
|
||||
regmap_update_bits(usp->regmap, USP_MODE1,
|
||||
USP_RXD_ACT_EDGE_FALLING | USP_TXD_ACT_EDGE_FALLING,
|
||||
USP_RXD_ACT_EDGE_FALLING);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
||||
regmap_update_bits(usp->regmap, USP_TX_FRAME_CTRL,
|
||||
USP_TXC_DATA_LEN_MASK | USP_TXC_FRAME_LEN_MASK
|
||||
| USP_TXC_SHIFTER_LEN_MASK | USP_TXC_SLAVE_CLK_SAMPLE,
|
||||
((data_len - 1) << USP_TXC_DATA_LEN_OFFSET)
|
||||
| ((frame_len - 1) << USP_TXC_FRAME_LEN_OFFSET)
|
||||
| ((shifter_len - 1) << USP_TXC_SHIFTER_LEN_OFFSET)
|
||||
| USP_TXC_SLAVE_CLK_SAMPLE);
|
||||
else
|
||||
regmap_update_bits(usp->regmap, USP_RX_FRAME_CTRL,
|
||||
USP_RXC_DATA_LEN_MASK | USP_RXC_FRAME_LEN_MASK
|
||||
| USP_RXC_SHIFTER_LEN_MASK | USP_SINGLE_SYNC_MODE,
|
||||
((data_len - 1) << USP_RXC_DATA_LEN_OFFSET)
|
||||
| ((frame_len - 1) << USP_RXC_FRAME_LEN_OFFSET)
|
||||
| ((shifter_len - 1) << USP_RXC_SHIFTER_LEN_OFFSET)
|
||||
| USP_SINGLE_SYNC_MODE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sirf_usp_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct sirf_usp *usp = snd_soc_dai_get_drvdata(dai);
|
||||
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
case SNDRV_PCM_TRIGGER_RESUME:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
||||
sirf_usp_tx_enable(usp);
|
||||
else
|
||||
sirf_usp_rx_enable(usp);
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
case SNDRV_PCM_TRIGGER_SUSPEND:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
||||
sirf_usp_tx_disable(usp);
|
||||
else
|
||||
sirf_usp_rx_disable(usp);
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct snd_soc_dai_ops sirf_usp_pcm_dai_ops = {
|
||||
.trigger = sirf_usp_pcm_trigger,
|
||||
.set_fmt = sirf_usp_pcm_set_dai_fmt,
|
||||
.hw_params = sirf_usp_pcm_hw_params,
|
||||
};
|
||||
|
||||
static struct snd_soc_dai_driver sirf_usp_pcm_dai = {
|
||||
.probe = sirf_usp_pcm_dai_probe,
|
||||
.name = "sirf-usp-pcm",
|
||||
.id = 0,
|
||||
.playback = {
|
||||
.stream_name = "SiRF USP PCM Playback",
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = SNDRV_PCM_RATE_8000_192000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
|
||||
SNDRV_PCM_FMTBIT_S24_3LE,
|
||||
},
|
||||
.capture = {
|
||||
.stream_name = "SiRF USP PCM Capture",
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = SNDRV_PCM_RATE_8000_192000,
|
||||
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
|
||||
SNDRV_PCM_FMTBIT_S24_3LE,
|
||||
},
|
||||
.ops = &sirf_usp_pcm_dai_ops,
|
||||
};
|
||||
|
||||
static int sirf_usp_pcm_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct sirf_usp *usp = dev_get_drvdata(dev);
|
||||
|
||||
clk_disable_unprepare(usp->clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sirf_usp_pcm_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct sirf_usp *usp = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(usp->clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "clk_enable failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
sirf_usp_i2s_init(usp);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int sirf_usp_pcm_suspend(struct device *dev)
|
||||
{
|
||||
struct sirf_usp *usp = dev_get_drvdata(dev);
|
||||
|
||||
if (!pm_runtime_status_suspended(dev)) {
|
||||
regmap_read(usp->regmap, USP_MODE1, &usp->mode1_reg);
|
||||
regmap_read(usp->regmap, USP_MODE2, &usp->mode2_reg);
|
||||
sirf_usp_pcm_runtime_suspend(dev);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sirf_usp_pcm_resume(struct device *dev)
|
||||
{
|
||||
struct sirf_usp *usp = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
if (!pm_runtime_status_suspended(dev)) {
|
||||
ret = sirf_usp_pcm_runtime_resume(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
regmap_write(usp->regmap, USP_MODE1, usp->mode1_reg);
|
||||
regmap_write(usp->regmap, USP_MODE2, usp->mode2_reg);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct snd_soc_component_driver sirf_usp_component = {
|
||||
.name = "sirf-usp",
|
||||
};
|
||||
|
||||
static const struct regmap_config sirf_usp_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = USP_RX_FIFO_DATA,
|
||||
.cache_type = REGCACHE_NONE,
|
||||
};
|
||||
|
||||
static int sirf_usp_pcm_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct sirf_usp *usp;
|
||||
void __iomem *base;
|
||||
|
||||
usp = devm_kzalloc(&pdev->dev, sizeof(struct sirf_usp),
|
||||
GFP_KERNEL);
|
||||
if (!usp)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, usp);
|
||||
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
usp->regmap = devm_regmap_init_mmio(&pdev->dev, base,
|
||||
&sirf_usp_regmap_config);
|
||||
if (IS_ERR(usp->regmap))
|
||||
return PTR_ERR(usp->regmap);
|
||||
|
||||
usp->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(usp->clk)) {
|
||||
dev_err(&pdev->dev, "Get clock failed.\n");
|
||||
return PTR_ERR(usp->clk);
|
||||
}
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
if (!pm_runtime_enabled(&pdev->dev)) {
|
||||
ret = sirf_usp_pcm_runtime_resume(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_snd_soc_register_component(&pdev->dev, &sirf_usp_component,
|
||||
&sirf_usp_pcm_dai, 1);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Register Audio SoC dai failed.\n");
|
||||
return ret;
|
||||
}
|
||||
return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
|
||||
}
|
||||
|
||||
static int sirf_usp_pcm_remove(struct platform_device *pdev)
|
||||
{
|
||||
if (!pm_runtime_enabled(&pdev->dev))
|
||||
sirf_usp_pcm_runtime_suspend(&pdev->dev);
|
||||
else
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id sirf_usp_pcm_of_match[] = {
|
||||
{ .compatible = "sirf,prima2-usp-pcm", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sirf_usp_pcm_of_match);
|
||||
|
||||
static const struct dev_pm_ops sirf_usp_pcm_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(sirf_usp_pcm_runtime_suspend,
|
||||
sirf_usp_pcm_runtime_resume, NULL)
|
||||
SET_SYSTEM_SLEEP_PM_OPS(sirf_usp_pcm_suspend, sirf_usp_pcm_resume)
|
||||
};
|
||||
|
||||
static struct platform_driver sirf_usp_pcm_driver = {
|
||||
.driver = {
|
||||
.name = "sirf-usp-pcm",
|
||||
.of_match_table = sirf_usp_pcm_of_match,
|
||||
.pm = &sirf_usp_pcm_pm_ops,
|
||||
},
|
||||
.probe = sirf_usp_pcm_probe,
|
||||
.remove = sirf_usp_pcm_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(sirf_usp_pcm_driver);
|
||||
|
||||
MODULE_DESCRIPTION("SiRF SoC USP PCM bus driver");
|
||||
MODULE_AUTHOR("RongJun Ying <Rongjun.Ying@csr.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
|
@ -1,292 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* arch/arm/mach-prima2/include/mach/sirfsoc_usp.h
|
||||
*
|
||||
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*/
|
||||
|
||||
#ifndef _SIRF_USP_H
|
||||
#define _SIRF_USP_H
|
||||
|
||||
/* USP Registers */
|
||||
#define USP_MODE1 0x00
|
||||
#define USP_MODE2 0x04
|
||||
#define USP_TX_FRAME_CTRL 0x08
|
||||
#define USP_RX_FRAME_CTRL 0x0C
|
||||
#define USP_TX_RX_ENABLE 0x10
|
||||
#define USP_INT_ENABLE 0x14
|
||||
#define USP_INT_STATUS 0x18
|
||||
#define USP_PIN_IO_DATA 0x1C
|
||||
#define USP_RISC_DSP_MODE 0x20
|
||||
#define USP_AYSNC_PARAM_REG 0x24
|
||||
#define USP_IRDA_X_MODE_DIV 0x28
|
||||
#define USP_SM_CFG 0x2C
|
||||
#define USP_TX_DMA_IO_CTRL 0x100
|
||||
#define USP_TX_DMA_IO_LEN 0x104
|
||||
#define USP_TX_FIFO_CTRL 0x108
|
||||
#define USP_TX_FIFO_LEVEL_CHK 0x10C
|
||||
#define USP_TX_FIFO_OP 0x110
|
||||
#define USP_TX_FIFO_STATUS 0x114
|
||||
#define USP_TX_FIFO_DATA 0x118
|
||||
#define USP_RX_DMA_IO_CTRL 0x120
|
||||
#define USP_RX_DMA_IO_LEN 0x124
|
||||
#define USP_RX_FIFO_CTRL 0x128
|
||||
#define USP_RX_FIFO_LEVEL_CHK 0x12C
|
||||
#define USP_RX_FIFO_OP 0x130
|
||||
#define USP_RX_FIFO_STATUS 0x134
|
||||
#define USP_RX_FIFO_DATA 0x138
|
||||
|
||||
/* USP MODE register-1 */
|
||||
#define USP_SYNC_MODE 0x00000001
|
||||
#define USP_CLOCK_MODE_SLAVE 0x00000002
|
||||
#define USP_LOOP_BACK_EN 0x00000004
|
||||
#define USP_HPSIR_EN 0x00000008
|
||||
#define USP_ENDIAN_CTRL_LSBF 0x00000010
|
||||
#define USP_EN 0x00000020
|
||||
#define USP_RXD_ACT_EDGE_FALLING 0x00000040
|
||||
#define USP_TXD_ACT_EDGE_FALLING 0x00000080
|
||||
#define USP_RFS_ACT_LEVEL_LOGIC1 0x00000100
|
||||
#define USP_TFS_ACT_LEVEL_LOGIC1 0x00000200
|
||||
#define USP_SCLK_IDLE_MODE_TOGGLE 0x00000400
|
||||
#define USP_SCLK_IDLE_LEVEL_LOGIC1 0x00000800
|
||||
#define USP_SCLK_PIN_MODE_IO 0x00001000
|
||||
#define USP_RFS_PIN_MODE_IO 0x00002000
|
||||
#define USP_TFS_PIN_MODE_IO 0x00004000
|
||||
#define USP_RXD_PIN_MODE_IO 0x00008000
|
||||
#define USP_TXD_PIN_MODE_IO 0x00010000
|
||||
#define USP_SCLK_IO_MODE_INPUT 0x00020000
|
||||
#define USP_RFS_IO_MODE_INPUT 0x00040000
|
||||
#define USP_TFS_IO_MODE_INPUT 0x00080000
|
||||
#define USP_RXD_IO_MODE_INPUT 0x00100000
|
||||
#define USP_TXD_IO_MODE_INPUT 0x00200000
|
||||
#define USP_IRDA_WIDTH_DIV_MASK 0x3FC00000
|
||||
#define USP_IRDA_WIDTH_DIV_OFFSET 0
|
||||
#define USP_IRDA_IDLE_LEVEL_HIGH 0x40000000
|
||||
#define USP_TX_UFLOW_REPEAT_ZERO 0x80000000
|
||||
#define USP_TX_ENDIAN_MODE 0x00000020
|
||||
#define USP_RX_ENDIAN_MODE 0x00000020
|
||||
|
||||
/* USP Mode Register-2 */
|
||||
#define USP_RXD_DELAY_LEN_MASK 0x000000FF
|
||||
#define USP_RXD_DELAY_LEN_OFFSET 0
|
||||
|
||||
#define USP_TXD_DELAY_LEN_MASK 0x0000FF00
|
||||
#define USP_TXD_DELAY_LEN_OFFSET 8
|
||||
|
||||
#define USP_ENA_CTRL_MODE 0x00010000
|
||||
#define USP_FRAME_CTRL_MODE 0x00020000
|
||||
#define USP_TFS_SOURCE_MODE 0x00040000
|
||||
#define USP_TFS_MS_MODE 0x00080000
|
||||
#define USP_CLK_DIVISOR_MASK 0x7FE00000
|
||||
#define USP_CLK_DIVISOR_OFFSET 21
|
||||
|
||||
#define USP_TFS_CLK_SLAVE_MODE (1<<20)
|
||||
#define USP_RFS_CLK_SLAVE_MODE (1<<19)
|
||||
|
||||
#define USP_IRDA_DATA_WIDTH 0x80000000
|
||||
|
||||
/* USP Transmit Frame Control Register */
|
||||
|
||||
#define USP_TXC_DATA_LEN_MASK 0x000000FF
|
||||
#define USP_TXC_DATA_LEN_OFFSET 0
|
||||
|
||||
#define USP_TXC_SYNC_LEN_MASK 0x0000FF00
|
||||
#define USP_TXC_SYNC_LEN_OFFSET 8
|
||||
|
||||
#define USP_TXC_FRAME_LEN_MASK 0x00FF0000
|
||||
#define USP_TXC_FRAME_LEN_OFFSET 16
|
||||
|
||||
#define USP_TXC_SHIFTER_LEN_MASK 0x1F000000
|
||||
#define USP_TXC_SHIFTER_LEN_OFFSET 24
|
||||
|
||||
#define USP_TXC_SLAVE_CLK_SAMPLE 0x20000000
|
||||
|
||||
#define USP_TXC_CLK_DIVISOR_MASK 0xC0000000
|
||||
#define USP_TXC_CLK_DIVISOR_OFFSET 30
|
||||
|
||||
/* USP Receive Frame Control Register */
|
||||
|
||||
#define USP_RXC_DATA_LEN_MASK 0x000000FF
|
||||
#define USP_RXC_DATA_LEN_OFFSET 0
|
||||
|
||||
#define USP_RXC_FRAME_LEN_MASK 0x0000FF00
|
||||
#define USP_RXC_FRAME_LEN_OFFSET 8
|
||||
|
||||
#define USP_RXC_SHIFTER_LEN_MASK 0x001F0000
|
||||
#define USP_RXC_SHIFTER_LEN_OFFSET 16
|
||||
|
||||
#define USP_START_EDGE_MODE 0x00800000
|
||||
#define USP_I2S_SYNC_CHG 0x00200000
|
||||
|
||||
#define USP_RXC_CLK_DIVISOR_MASK 0x0F000000
|
||||
#define USP_RXC_CLK_DIVISOR_OFFSET 24
|
||||
#define USP_SINGLE_SYNC_MODE 0x00400000
|
||||
|
||||
/* Tx - RX Enable Register */
|
||||
|
||||
#define USP_RX_ENA 0x00000001
|
||||
#define USP_TX_ENA 0x00000002
|
||||
|
||||
/* USP Interrupt Enable and status Register */
|
||||
#define USP_RX_DONE_INT 0x00000001
|
||||
#define USP_TX_DONE_INT 0x00000002
|
||||
#define USP_RX_OFLOW_INT 0x00000004
|
||||
#define USP_TX_UFLOW_INT 0x00000008
|
||||
#define USP_RX_IO_DMA_INT 0x00000010
|
||||
#define USP_TX_IO_DMA_INT 0x00000020
|
||||
#define USP_RXFIFO_FULL_INT 0x00000040
|
||||
#define USP_TXFIFO_EMPTY_INT 0x00000080
|
||||
#define USP_RXFIFO_THD_INT 0x00000100
|
||||
#define USP_TXFIFO_THD_INT 0x00000200
|
||||
#define USP_UART_FRM_ERR_INT 0x00000400
|
||||
#define USP_RX_TIMEOUT_INT 0x00000800
|
||||
#define USP_TX_ALLOUT_INT 0x00001000
|
||||
#define USP_RXD_BREAK_INT 0x00008000
|
||||
|
||||
/* All possible TX interruots */
|
||||
#define USP_TX_INTERRUPT (USP_TX_DONE_INT|USP_TX_UFLOW_INT|\
|
||||
USP_TX_IO_DMA_INT|\
|
||||
USP_TXFIFO_EMPTY_INT|\
|
||||
USP_TXFIFO_THD_INT)
|
||||
/* All possible RX interruots */
|
||||
#define USP_RX_INTERRUPT (USP_RX_DONE_INT|USP_RX_OFLOW_INT|\
|
||||
USP_RX_IO_DMA_INT|\
|
||||
USP_RXFIFO_FULL_INT|\
|
||||
USP_RXFIFO_THD_INT|\
|
||||
USP_RX_TIMEOUT_INT)
|
||||
|
||||
#define USP_INT_ALL 0x1FFF
|
||||
|
||||
/* USP Pin I/O Data Register */
|
||||
|
||||
#define USP_RFS_PIN_VALUE_MASK 0x00000001
|
||||
#define USP_TFS_PIN_VALUE_MASK 0x00000002
|
||||
#define USP_RXD_PIN_VALUE_MASK 0x00000004
|
||||
#define USP_TXD_PIN_VALUE_MASK 0x00000008
|
||||
#define USP_SCLK_PIN_VALUE_MASK 0x00000010
|
||||
|
||||
/* USP RISC/DSP Mode Register */
|
||||
#define USP_RISC_DSP_SEL 0x00000001
|
||||
|
||||
/* USP ASYNC PARAMETER Register*/
|
||||
|
||||
#define USP_ASYNC_TIMEOUT_MASK 0x0000FFFF
|
||||
#define USP_ASYNC_TIMEOUT_OFFSET 0
|
||||
#define USP_ASYNC_TIMEOUT(x) (((x)&USP_ASYNC_TIMEOUT_MASK) \
|
||||
<<USP_ASYNC_TIMEOUT_OFFSET)
|
||||
|
||||
#define USP_ASYNC_DIV2_MASK 0x003F0000
|
||||
#define USP_ASYNC_DIV2_OFFSET 16
|
||||
|
||||
/* USP TX DMA I/O MODE Register */
|
||||
#define USP_TX_MODE_IO 0x00000001
|
||||
|
||||
/* USP TX DMA I/O Length Register */
|
||||
#define USP_TX_DATA_LEN_MASK 0xFFFFFFFF
|
||||
#define USP_TX_DATA_LEN_OFFSET 0
|
||||
|
||||
/* USP TX FIFO Control Register */
|
||||
#define USP_TX_FIFO_WIDTH_MASK 0x00000003
|
||||
#define USP_TX_FIFO_WIDTH_OFFSET 0
|
||||
|
||||
#define USP_TX_FIFO_THD_MASK 0x000001FC
|
||||
#define USP_TX_FIFO_THD_OFFSET 2
|
||||
|
||||
/* USP TX FIFO Level Check Register */
|
||||
#define USP_TX_FIFO_LEVEL_CHECK_MASK 0x1F
|
||||
#define USP_TX_FIFO_SC_OFFSET 0
|
||||
#define USP_TX_FIFO_LC_OFFSET 10
|
||||
#define USP_TX_FIFO_HC_OFFSET 20
|
||||
|
||||
#define TX_FIFO_SC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \
|
||||
<< USP_TX_FIFO_SC_OFFSET)
|
||||
#define TX_FIFO_LC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \
|
||||
<< USP_TX_FIFO_LC_OFFSET)
|
||||
#define TX_FIFO_HC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \
|
||||
<< USP_TX_FIFO_HC_OFFSET)
|
||||
|
||||
/* USP TX FIFO Operation Register */
|
||||
#define USP_TX_FIFO_RESET 0x00000001
|
||||
#define USP_TX_FIFO_START 0x00000002
|
||||
|
||||
/* USP TX FIFO Status Register */
|
||||
#define USP_TX_FIFO_LEVEL_MASK 0x0000007F
|
||||
#define USP_TX_FIFO_LEVEL_OFFSET 0
|
||||
|
||||
#define USP_TX_FIFO_FULL 0x00000080
|
||||
#define USP_TX_FIFO_EMPTY 0x00000100
|
||||
|
||||
/* USP TX FIFO Data Register */
|
||||
#define USP_TX_FIFO_DATA_MASK 0xFFFFFFFF
|
||||
#define USP_TX_FIFO_DATA_OFFSET 0
|
||||
|
||||
/* USP RX DMA I/O MODE Register */
|
||||
#define USP_RX_MODE_IO 0x00000001
|
||||
#define USP_RX_DMA_FLUSH 0x00000004
|
||||
|
||||
/* USP RX DMA I/O Length Register */
|
||||
#define USP_RX_DATA_LEN_MASK 0xFFFFFFFF
|
||||
#define USP_RX_DATA_LEN_OFFSET 0
|
||||
|
||||
/* USP RX FIFO Control Register */
|
||||
#define USP_RX_FIFO_WIDTH_MASK 0x00000003
|
||||
#define USP_RX_FIFO_WIDTH_OFFSET 0
|
||||
|
||||
#define USP_RX_FIFO_THD_MASK 0x000001FC
|
||||
#define USP_RX_FIFO_THD_OFFSET 2
|
||||
|
||||
/* USP RX FIFO Level Check Register */
|
||||
|
||||
#define USP_RX_FIFO_LEVEL_CHECK_MASK 0x1F
|
||||
#define USP_RX_FIFO_SC_OFFSET 0
|
||||
#define USP_RX_FIFO_LC_OFFSET 10
|
||||
#define USP_RX_FIFO_HC_OFFSET 20
|
||||
|
||||
#define RX_FIFO_SC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \
|
||||
<< USP_RX_FIFO_SC_OFFSET)
|
||||
#define RX_FIFO_LC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \
|
||||
<< USP_RX_FIFO_LC_OFFSET)
|
||||
#define RX_FIFO_HC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \
|
||||
<< USP_RX_FIFO_HC_OFFSET)
|
||||
|
||||
/* USP RX FIFO Operation Register */
|
||||
#define USP_RX_FIFO_RESET 0x00000001
|
||||
#define USP_RX_FIFO_START 0x00000002
|
||||
|
||||
/* USP RX FIFO Status Register */
|
||||
|
||||
#define USP_RX_FIFO_LEVEL_MASK 0x0000007F
|
||||
#define USP_RX_FIFO_LEVEL_OFFSET 0
|
||||
|
||||
#define USP_RX_FIFO_FULL 0x00000080
|
||||
#define USP_RX_FIFO_EMPTY 0x00000100
|
||||
|
||||
/* USP RX FIFO Data Register */
|
||||
|
||||
#define USP_RX_FIFO_DATA_MASK 0xFFFFFFFF
|
||||
#define USP_RX_FIFO_DATA_OFFSET 0
|
||||
|
||||
/*
|
||||
* When rx thd irq occur, sender just disable tx empty irq,
|
||||
* Remaining data in tx fifo wil also be sent out.
|
||||
*/
|
||||
#define USP_FIFO_SIZE 128
|
||||
#define USP_TX_FIFO_THRESHOLD (USP_FIFO_SIZE/2)
|
||||
#define USP_RX_FIFO_THRESHOLD (USP_FIFO_SIZE/2)
|
||||
|
||||
/* FIFO_WIDTH for the USP_TX_FIFO_CTRL and USP_RX_FIFO_CTRL registers */
|
||||
#define USP_FIFO_WIDTH_BYTE 0x00
|
||||
#define USP_FIFO_WIDTH_WORD 0x01
|
||||
#define USP_FIFO_WIDTH_DWORD 0x02
|
||||
|
||||
#define USP_ASYNC_DIV2 16
|
||||
|
||||
#define USP_PLUGOUT_RETRY_CNT 2
|
||||
|
||||
#define USP_TX_RX_FIFO_WIDTH_DWORD 2
|
||||
|
||||
#define SIRF_USP_DIV_MCLK 0
|
||||
|
||||
#define SIRF_USP_I2S_TFS_SYNC 0
|
||||
#define SIRF_USP_I2S_RFS_SYNC 1
|
||||
#endif
|
|
@ -1,26 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
config ZX_SPDIF
|
||||
tristate "ZTE ZX SPDIF Driver Support"
|
||||
depends on ARCH_ZX || COMPILE_TEST
|
||||
depends on COMMON_CLK
|
||||
select SND_SOC_GENERIC_DMAENGINE_PCM
|
||||
help
|
||||
Say Y or M if you want to add support for codecs attached to the
|
||||
ZTE ZX SPDIF interface
|
||||
|
||||
config ZX_I2S
|
||||
tristate "ZTE ZX I2S Driver Support"
|
||||
depends on ARCH_ZX || COMPILE_TEST
|
||||
depends on COMMON_CLK
|
||||
select SND_SOC_GENERIC_DMAENGINE_PCM
|
||||
help
|
||||
Say Y or M if you want to add support for codecs attached to the
|
||||
ZTE ZX I2S interface
|
||||
|
||||
config ZX_TDM
|
||||
tristate "ZTE ZX TDM Driver Support"
|
||||
depends on COMMON_CLK
|
||||
select SND_SOC_GENERIC_DMAENGINE_PCM
|
||||
help
|
||||
Say Y or M if you want to add support for codecs attached to the
|
||||
ZTE ZX TDM interface
|
|
@ -1,4 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-$(CONFIG_ZX_SPDIF) += zx-spdif.o
|
||||
obj-$(CONFIG_ZX_I2S) += zx-i2s.o
|
||||
obj-$(CONFIG_ZX_TDM) += zx-tdm.o
|
|
@ -1,452 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2015 Linaro
|
||||
*
|
||||
* Author: Jun Nie <jun.nie@linaro.org>
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <sound/pcm.h>
|
||||
#include <sound/pcm_params.h>
|
||||
#include <sound/soc.h>
|
||||
#include <sound/soc-dai.h>
|
||||
|
||||
#include <sound/core.h>
|
||||
#include <sound/dmaengine_pcm.h>
|
||||
#include <sound/initval.h>
|
||||
|
||||
#define ZX_I2S_PROCESS_CTRL 0x04
|
||||
#define ZX_I2S_TIMING_CTRL 0x08
|
||||
#define ZX_I2S_FIFO_CTRL 0x0C
|
||||
#define ZX_I2S_FIFO_STATUS 0x10
|
||||
#define ZX_I2S_INT_EN 0x14
|
||||
#define ZX_I2S_INT_STATUS 0x18
|
||||
#define ZX_I2S_DATA 0x1C
|
||||
#define ZX_I2S_FRAME_CNTR 0x20
|
||||
|
||||
#define I2S_DEAGULT_FIFO_THRES (0x10)
|
||||
#define I2S_MAX_FIFO_THRES (0x20)
|
||||
|
||||
#define ZX_I2S_PROCESS_TX_EN (1 << 0)
|
||||
#define ZX_I2S_PROCESS_TX_DIS (0 << 0)
|
||||
#define ZX_I2S_PROCESS_RX_EN (1 << 1)
|
||||
#define ZX_I2S_PROCESS_RX_DIS (0 << 1)
|
||||
#define ZX_I2S_PROCESS_I2S_EN (1 << 2)
|
||||
#define ZX_I2S_PROCESS_I2S_DIS (0 << 2)
|
||||
|
||||
#define ZX_I2S_TIMING_MAST (1 << 0)
|
||||
#define ZX_I2S_TIMING_SLAVE (0 << 0)
|
||||
#define ZX_I2S_TIMING_MS_MASK (1 << 0)
|
||||
#define ZX_I2S_TIMING_LOOP (1 << 1)
|
||||
#define ZX_I2S_TIMING_NOR (0 << 1)
|
||||
#define ZX_I2S_TIMING_LOOP_MASK (1 << 1)
|
||||
#define ZX_I2S_TIMING_PTNR (1 << 2)
|
||||
#define ZX_I2S_TIMING_NTPR (0 << 2)
|
||||
#define ZX_I2S_TIMING_PHASE_MASK (1 << 2)
|
||||
#define ZX_I2S_TIMING_TDM (1 << 3)
|
||||
#define ZX_I2S_TIMING_I2S (0 << 3)
|
||||
#define ZX_I2S_TIMING_TIMING_MASK (1 << 3)
|
||||
#define ZX_I2S_TIMING_LONG_SYNC (1 << 4)
|
||||
#define ZX_I2S_TIMING_SHORT_SYNC (0 << 4)
|
||||
#define ZX_I2S_TIMING_SYNC_MASK (1 << 4)
|
||||
#define ZX_I2S_TIMING_TEAK_EN (1 << 5)
|
||||
#define ZX_I2S_TIMING_TEAK_DIS (0 << 5)
|
||||
#define ZX_I2S_TIMING_TEAK_MASK (1 << 5)
|
||||
#define ZX_I2S_TIMING_STD_I2S (0 << 6)
|
||||
#define ZX_I2S_TIMING_MSB_JUSTIF (1 << 6)
|
||||
#define ZX_I2S_TIMING_LSB_JUSTIF (2 << 6)
|
||||
#define ZX_I2S_TIMING_ALIGN_MASK (3 << 6)
|
||||
#define ZX_I2S_TIMING_CHN_MASK (7 << 8)
|
||||
#define ZX_I2S_TIMING_CHN(x) ((x - 1) << 8)
|
||||
#define ZX_I2S_TIMING_LANE_MASK (3 << 11)
|
||||
#define ZX_I2S_TIMING_LANE(x) ((x - 1) << 11)
|
||||
#define ZX_I2S_TIMING_TSCFG_MASK (7 << 13)
|
||||
#define ZX_I2S_TIMING_TSCFG(x) (x << 13)
|
||||
#define ZX_I2S_TIMING_TS_WIDTH_MASK (0x1f << 16)
|
||||
#define ZX_I2S_TIMING_TS_WIDTH(x) ((x - 1) << 16)
|
||||
#define ZX_I2S_TIMING_DATA_SIZE_MASK (0x1f << 21)
|
||||
#define ZX_I2S_TIMING_DATA_SIZE(x) ((x - 1) << 21)
|
||||
#define ZX_I2S_TIMING_CFG_ERR_MASK (1 << 31)
|
||||
|
||||
#define ZX_I2S_FIFO_CTRL_TX_RST (1 << 0)
|
||||
#define ZX_I2S_FIFO_CTRL_TX_RST_MASK (1 << 0)
|
||||
#define ZX_I2S_FIFO_CTRL_RX_RST (1 << 1)
|
||||
#define ZX_I2S_FIFO_CTRL_RX_RST_MASK (1 << 1)
|
||||
#define ZX_I2S_FIFO_CTRL_TX_DMA_EN (1 << 4)
|
||||
#define ZX_I2S_FIFO_CTRL_TX_DMA_DIS (0 << 4)
|
||||
#define ZX_I2S_FIFO_CTRL_TX_DMA_MASK (1 << 4)
|
||||
#define ZX_I2S_FIFO_CTRL_RX_DMA_EN (1 << 5)
|
||||
#define ZX_I2S_FIFO_CTRL_RX_DMA_DIS (0 << 5)
|
||||
#define ZX_I2S_FIFO_CTRL_RX_DMA_MASK (1 << 5)
|
||||
#define ZX_I2S_FIFO_CTRL_TX_THRES_MASK (0x1F << 8)
|
||||
#define ZX_I2S_FIFO_CTRL_RX_THRES_MASK (0x1F << 16)
|
||||
|
||||
#define CLK_RAT (32 * 4)
|
||||
|
||||
struct zx_i2s_info {
|
||||
struct snd_dmaengine_dai_dma_data dma_playback;
|
||||
struct snd_dmaengine_dai_dma_data dma_capture;
|
||||
struct clk *dai_wclk;
|
||||
struct clk *dai_pclk;
|
||||
void __iomem *reg_base;
|
||||
int master;
|
||||
resource_size_t mapbase;
|
||||
};
|
||||
|
||||
static void zx_i2s_tx_en(void __iomem *base, bool on)
|
||||
{
|
||||
unsigned long val;
|
||||
|
||||
val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL);
|
||||
if (on)
|
||||
val |= ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN;
|
||||
else
|
||||
val &= ~(ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN);
|
||||
writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL);
|
||||
}
|
||||
|
||||
static void zx_i2s_rx_en(void __iomem *base, bool on)
|
||||
{
|
||||
unsigned long val;
|
||||
|
||||
val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL);
|
||||
if (on)
|
||||
val |= ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN;
|
||||
else
|
||||
val &= ~(ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN);
|
||||
writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL);
|
||||
}
|
||||
|
||||
static void zx_i2s_tx_dma_en(void __iomem *base, bool on)
|
||||
{
|
||||
unsigned long val;
|
||||
|
||||
val = readl_relaxed(base + ZX_I2S_FIFO_CTRL);
|
||||
val |= ZX_I2S_FIFO_CTRL_TX_RST | (I2S_DEAGULT_FIFO_THRES << 8);
|
||||
if (on)
|
||||
val |= ZX_I2S_FIFO_CTRL_TX_DMA_EN;
|
||||
else
|
||||
val &= ~ZX_I2S_FIFO_CTRL_TX_DMA_EN;
|
||||
writel_relaxed(val, base + ZX_I2S_FIFO_CTRL);
|
||||
}
|
||||
|
||||
static void zx_i2s_rx_dma_en(void __iomem *base, bool on)
|
||||
{
|
||||
unsigned long val;
|
||||
|
||||
val = readl_relaxed(base + ZX_I2S_FIFO_CTRL);
|
||||
val |= ZX_I2S_FIFO_CTRL_RX_RST | (I2S_DEAGULT_FIFO_THRES << 16);
|
||||
if (on)
|
||||
val |= ZX_I2S_FIFO_CTRL_RX_DMA_EN;
|
||||
else
|
||||
val &= ~ZX_I2S_FIFO_CTRL_RX_DMA_EN;
|
||||
writel_relaxed(val, base + ZX_I2S_FIFO_CTRL);
|
||||
}
|
||||
|
||||
#define ZX_I2S_RATES \
|
||||
(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
|
||||
SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
|
||||
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000| \
|
||||
SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
|
||||
|
||||
#define ZX_I2S_FMTBIT \
|
||||
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | \
|
||||
SNDRV_PCM_FMTBIT_S32_LE)
|
||||
|
||||
static int zx_i2s_dai_probe(struct snd_soc_dai *dai)
|
||||
{
|
||||
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
|
||||
|
||||
snd_soc_dai_set_drvdata(dai, zx_i2s);
|
||||
zx_i2s->dma_playback.addr = zx_i2s->mapbase + ZX_I2S_DATA;
|
||||
zx_i2s->dma_playback.maxburst = 16;
|
||||
zx_i2s->dma_capture.addr = zx_i2s->mapbase + ZX_I2S_DATA;
|
||||
zx_i2s->dma_capture.maxburst = 16;
|
||||
snd_soc_dai_init_dma_data(dai, &zx_i2s->dma_playback,
|
||||
&zx_i2s->dma_capture);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int zx_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
|
||||
{
|
||||
struct zx_i2s_info *i2s = snd_soc_dai_get_drvdata(cpu_dai);
|
||||
unsigned long val;
|
||||
|
||||
val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL);
|
||||
val &= ~(ZX_I2S_TIMING_TIMING_MASK | ZX_I2S_TIMING_ALIGN_MASK |
|
||||
ZX_I2S_TIMING_TEAK_MASK | ZX_I2S_TIMING_SYNC_MASK |
|
||||
ZX_I2S_TIMING_MS_MASK);
|
||||
|
||||
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
||||
case SND_SOC_DAIFMT_I2S:
|
||||
val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_STD_I2S);
|
||||
break;
|
||||
case SND_SOC_DAIFMT_LEFT_J:
|
||||
val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_MSB_JUSTIF);
|
||||
break;
|
||||
case SND_SOC_DAIFMT_RIGHT_J:
|
||||
val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_LSB_JUSTIF);
|
||||
break;
|
||||
default:
|
||||
dev_err(cpu_dai->dev, "Unknown i2s timing\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
||||
case SND_SOC_DAIFMT_CBM_CFM:
|
||||
/* Codec is master, and I2S is slave. */
|
||||
i2s->master = 0;
|
||||
val |= ZX_I2S_TIMING_SLAVE;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_CBS_CFS:
|
||||
/* Codec is slave, and I2S is master. */
|
||||
i2s->master = 1;
|
||||
val |= ZX_I2S_TIMING_MAST;
|
||||
break;
|
||||
default:
|
||||
dev_err(cpu_dai->dev, "Unknown master/slave format\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int zx_i2s_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params,
|
||||
struct snd_soc_dai *socdai)
|
||||
{
|
||||
struct zx_i2s_info *i2s = snd_soc_dai_get_drvdata(socdai);
|
||||
struct snd_dmaengine_dai_dma_data *dma_data;
|
||||
unsigned int lane, ch_num, len, ret = 0;
|
||||
unsigned int ts_width = 32;
|
||||
unsigned long val;
|
||||
unsigned long chn_cfg;
|
||||
|
||||
dma_data = snd_soc_dai_get_dma_data(socdai, substream);
|
||||
dma_data->addr_width = ts_width >> 3;
|
||||
|
||||
val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL);
|
||||
val &= ~(ZX_I2S_TIMING_TS_WIDTH_MASK | ZX_I2S_TIMING_DATA_SIZE_MASK |
|
||||
ZX_I2S_TIMING_LANE_MASK | ZX_I2S_TIMING_CHN_MASK |
|
||||
ZX_I2S_TIMING_TSCFG_MASK);
|
||||
|
||||
switch (params_format(params)) {
|
||||
case SNDRV_PCM_FORMAT_S16_LE:
|
||||
len = 16;
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S24_LE:
|
||||
len = 24;
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S32_LE:
|
||||
len = 32;
|
||||
break;
|
||||
default:
|
||||
dev_err(socdai->dev, "Unknown data format\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
val |= ZX_I2S_TIMING_TS_WIDTH(ts_width) | ZX_I2S_TIMING_DATA_SIZE(len);
|
||||
|
||||
ch_num = params_channels(params);
|
||||
switch (ch_num) {
|
||||
case 1:
|
||||
lane = 1;
|
||||
chn_cfg = 2;
|
||||
break;
|
||||
case 2:
|
||||
case 4:
|
||||
case 6:
|
||||
case 8:
|
||||
lane = ch_num / 2;
|
||||
chn_cfg = 3;
|
||||
break;
|
||||
default:
|
||||
dev_err(socdai->dev, "Not support channel num %d\n", ch_num);
|
||||
return -EINVAL;
|
||||
}
|
||||
val |= ZX_I2S_TIMING_LANE(lane);
|
||||
val |= ZX_I2S_TIMING_TSCFG(chn_cfg);
|
||||
val |= ZX_I2S_TIMING_CHN(ch_num);
|
||||
writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
|
||||
|
||||
if (i2s->master)
|
||||
ret = clk_set_rate(i2s->dai_wclk,
|
||||
params_rate(params) * ch_num * CLK_RAT);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int zx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
|
||||
int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
|
||||
int ret = 0;
|
||||
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
if (capture)
|
||||
zx_i2s_rx_dma_en(zx_i2s->reg_base, true);
|
||||
else
|
||||
zx_i2s_tx_dma_en(zx_i2s->reg_base, true);
|
||||
fallthrough;
|
||||
case SNDRV_PCM_TRIGGER_RESUME:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
||||
if (capture)
|
||||
zx_i2s_rx_en(zx_i2s->reg_base, true);
|
||||
else
|
||||
zx_i2s_tx_en(zx_i2s->reg_base, true);
|
||||
break;
|
||||
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
if (capture)
|
||||
zx_i2s_rx_dma_en(zx_i2s->reg_base, false);
|
||||
else
|
||||
zx_i2s_tx_dma_en(zx_i2s->reg_base, false);
|
||||
fallthrough;
|
||||
case SNDRV_PCM_TRIGGER_SUSPEND:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
if (capture)
|
||||
zx_i2s_rx_en(zx_i2s->reg_base, false);
|
||||
else
|
||||
zx_i2s_tx_en(zx_i2s->reg_base, false);
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int zx_i2s_startup(struct snd_pcm_substream *substream,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(zx_i2s->dai_wclk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_prepare_enable(zx_i2s->dai_pclk);
|
||||
if (ret) {
|
||||
clk_disable_unprepare(zx_i2s->dai_wclk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void zx_i2s_shutdown(struct snd_pcm_substream *substream,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct zx_i2s_info *zx_i2s = dev_get_drvdata(dai->dev);
|
||||
|
||||
clk_disable_unprepare(zx_i2s->dai_wclk);
|
||||
clk_disable_unprepare(zx_i2s->dai_pclk);
|
||||
}
|
||||
|
||||
static const struct snd_soc_dai_ops zx_i2s_dai_ops = {
|
||||
.trigger = zx_i2s_trigger,
|
||||
.hw_params = zx_i2s_hw_params,
|
||||
.set_fmt = zx_i2s_set_fmt,
|
||||
.startup = zx_i2s_startup,
|
||||
.shutdown = zx_i2s_shutdown,
|
||||
};
|
||||
|
||||
static const struct snd_soc_component_driver zx_i2s_component = {
|
||||
.name = "zx-i2s",
|
||||
};
|
||||
|
||||
static struct snd_soc_dai_driver zx_i2s_dai = {
|
||||
.name = "zx-i2s-dai",
|
||||
.id = 0,
|
||||
.probe = zx_i2s_dai_probe,
|
||||
.playback = {
|
||||
.channels_min = 1,
|
||||
.channels_max = 8,
|
||||
.rates = ZX_I2S_RATES,
|
||||
.formats = ZX_I2S_FMTBIT,
|
||||
},
|
||||
.capture = {
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = ZX_I2S_RATES,
|
||||
.formats = ZX_I2S_FMTBIT,
|
||||
},
|
||||
.ops = &zx_i2s_dai_ops,
|
||||
};
|
||||
|
||||
static int zx_i2s_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
struct zx_i2s_info *zx_i2s;
|
||||
int ret;
|
||||
|
||||
zx_i2s = devm_kzalloc(&pdev->dev, sizeof(*zx_i2s), GFP_KERNEL);
|
||||
if (!zx_i2s)
|
||||
return -ENOMEM;
|
||||
|
||||
zx_i2s->dai_wclk = devm_clk_get(&pdev->dev, "wclk");
|
||||
if (IS_ERR(zx_i2s->dai_wclk)) {
|
||||
dev_err(&pdev->dev, "Fail to get wclk\n");
|
||||
return PTR_ERR(zx_i2s->dai_wclk);
|
||||
}
|
||||
|
||||
zx_i2s->dai_pclk = devm_clk_get(&pdev->dev, "pclk");
|
||||
if (IS_ERR(zx_i2s->dai_pclk)) {
|
||||
dev_err(&pdev->dev, "Fail to get pclk\n");
|
||||
return PTR_ERR(zx_i2s->dai_pclk);
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
zx_i2s->mapbase = res->start;
|
||||
zx_i2s->reg_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(zx_i2s->reg_base)) {
|
||||
dev_err(&pdev->dev, "ioremap failed!\n");
|
||||
return PTR_ERR(zx_i2s->reg_base);
|
||||
}
|
||||
|
||||
writel_relaxed(0, zx_i2s->reg_base + ZX_I2S_FIFO_CTRL);
|
||||
platform_set_drvdata(pdev, zx_i2s);
|
||||
|
||||
ret = devm_snd_soc_register_component(&pdev->dev, &zx_i2s_component,
|
||||
&zx_i2s_dai, 1);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Register DAI failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
|
||||
if (ret)
|
||||
dev_err(&pdev->dev, "Register platform PCM failed: %d\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id zx_i2s_dt_ids[] = {
|
||||
{ .compatible = "zte,zx296702-i2s", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, zx_i2s_dt_ids);
|
||||
|
||||
static struct platform_driver i2s_driver = {
|
||||
.probe = zx_i2s_probe,
|
||||
.driver = {
|
||||
.name = "zx-i2s",
|
||||
.of_match_table = zx_i2s_dt_ids,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(i2s_driver);
|
||||
|
||||
MODULE_AUTHOR("Jun Nie <jun.nie@linaro.org>");
|
||||
MODULE_DESCRIPTION("ZTE I2S SoC DAI");
|
||||
MODULE_LICENSE("GPL");
|
|
@ -1,363 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2015 Linaro
|
||||
*
|
||||
* Author: Jun Nie <jun.nie@linaro.org>
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <sound/asoundef.h>
|
||||
#include <sound/core.h>
|
||||
#include <sound/dmaengine_pcm.h>
|
||||
#include <sound/initval.h>
|
||||
#include <sound/pcm.h>
|
||||
#include <sound/pcm_params.h>
|
||||
#include <sound/soc.h>
|
||||
#include <sound/soc-dai.h>
|
||||
|
||||
#define ZX_CTRL 0x04
|
||||
#define ZX_FIFOCTRL 0x08
|
||||
#define ZX_INT_STATUS 0x10
|
||||
#define ZX_INT_MASK 0x14
|
||||
#define ZX_DATA 0x18
|
||||
#define ZX_VALID_BIT 0x1c
|
||||
#define ZX_CH_STA_1 0x20
|
||||
#define ZX_CH_STA_2 0x24
|
||||
#define ZX_CH_STA_3 0x28
|
||||
#define ZX_CH_STA_4 0x2c
|
||||
#define ZX_CH_STA_5 0x30
|
||||
#define ZX_CH_STA_6 0x34
|
||||
|
||||
#define ZX_CTRL_MODA_16 (0 << 6)
|
||||
#define ZX_CTRL_MODA_18 BIT(6)
|
||||
#define ZX_CTRL_MODA_20 (2 << 6)
|
||||
#define ZX_CTRL_MODA_24 (3 << 6)
|
||||
#define ZX_CTRL_MODA_MASK (3 << 6)
|
||||
|
||||
#define ZX_CTRL_ENB BIT(4)
|
||||
#define ZX_CTRL_DNB (0 << 4)
|
||||
#define ZX_CTRL_ENB_MASK BIT(4)
|
||||
|
||||
#define ZX_CTRL_TX_OPEN BIT(0)
|
||||
#define ZX_CTRL_TX_CLOSE (0 << 0)
|
||||
#define ZX_CTRL_TX_MASK BIT(0)
|
||||
|
||||
#define ZX_CTRL_OPEN (ZX_CTRL_TX_OPEN | ZX_CTRL_ENB)
|
||||
#define ZX_CTRL_CLOSE (ZX_CTRL_TX_CLOSE | ZX_CTRL_DNB)
|
||||
|
||||
#define ZX_CTRL_DOUBLE_TRACK (0 << 8)
|
||||
#define ZX_CTRL_LEFT_TRACK BIT(8)
|
||||
#define ZX_CTRL_RIGHT_TRACK (2 << 8)
|
||||
#define ZX_CTRL_TRACK_MASK (3 << 8)
|
||||
|
||||
#define ZX_FIFOCTRL_TXTH_MASK (0x1f << 8)
|
||||
#define ZX_FIFOCTRL_TXTH(x) (x << 8)
|
||||
#define ZX_FIFOCTRL_TX_DMA_EN BIT(2)
|
||||
#define ZX_FIFOCTRL_TX_DMA_DIS (0 << 2)
|
||||
#define ZX_FIFOCTRL_TX_DMA_EN_MASK BIT(2)
|
||||
#define ZX_FIFOCTRL_TX_FIFO_RST BIT(0)
|
||||
#define ZX_FIFOCTRL_TX_FIFO_RST_MASK BIT(0)
|
||||
|
||||
#define ZX_VALID_DOUBLE_TRACK (0 << 0)
|
||||
#define ZX_VALID_LEFT_TRACK BIT(1)
|
||||
#define ZX_VALID_RIGHT_TRACK (2 << 0)
|
||||
#define ZX_VALID_TRACK_MASK (3 << 0)
|
||||
|
||||
#define ZX_SPDIF_CLK_RAT (2 * 32)
|
||||
|
||||
struct zx_spdif_info {
|
||||
struct snd_dmaengine_dai_dma_data dma_data;
|
||||
struct clk *dai_clk;
|
||||
void __iomem *reg_base;
|
||||
resource_size_t mapbase;
|
||||
};
|
||||
|
||||
static int zx_spdif_dai_probe(struct snd_soc_dai *dai)
|
||||
{
|
||||
struct zx_spdif_info *zx_spdif = dev_get_drvdata(dai->dev);
|
||||
|
||||
snd_soc_dai_set_drvdata(dai, zx_spdif);
|
||||
zx_spdif->dma_data.addr = zx_spdif->mapbase + ZX_DATA;
|
||||
zx_spdif->dma_data.maxburst = 8;
|
||||
snd_soc_dai_init_dma_data(dai, &zx_spdif->dma_data, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int zx_spdif_chanstats(void __iomem *base, unsigned int rate)
|
||||
{
|
||||
u32 cstas1;
|
||||
|
||||
switch (rate) {
|
||||
case 22050:
|
||||
cstas1 = IEC958_AES3_CON_FS_22050;
|
||||
break;
|
||||
case 24000:
|
||||
cstas1 = IEC958_AES3_CON_FS_24000;
|
||||
break;
|
||||
case 32000:
|
||||
cstas1 = IEC958_AES3_CON_FS_32000;
|
||||
break;
|
||||
case 44100:
|
||||
cstas1 = IEC958_AES3_CON_FS_44100;
|
||||
break;
|
||||
case 48000:
|
||||
cstas1 = IEC958_AES3_CON_FS_48000;
|
||||
break;
|
||||
case 88200:
|
||||
cstas1 = IEC958_AES3_CON_FS_88200;
|
||||
break;
|
||||
case 96000:
|
||||
cstas1 = IEC958_AES3_CON_FS_96000;
|
||||
break;
|
||||
case 176400:
|
||||
cstas1 = IEC958_AES3_CON_FS_176400;
|
||||
break;
|
||||
case 192000:
|
||||
cstas1 = IEC958_AES3_CON_FS_192000;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
cstas1 = cstas1 << 24;
|
||||
cstas1 |= IEC958_AES0_CON_NOT_COPYRIGHT;
|
||||
|
||||
writel_relaxed(cstas1, base + ZX_CH_STA_1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int zx_spdif_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params,
|
||||
struct snd_soc_dai *socdai)
|
||||
{
|
||||
struct zx_spdif_info *zx_spdif = dev_get_drvdata(socdai->dev);
|
||||
struct zx_spdif_info *spdif = snd_soc_dai_get_drvdata(socdai);
|
||||
struct snd_dmaengine_dai_dma_data *dma_data =
|
||||
snd_soc_dai_get_dma_data(socdai, substream);
|
||||
u32 val, ch_num, rate;
|
||||
int ret;
|
||||
|
||||
dma_data->addr_width = params_width(params) >> 3;
|
||||
|
||||
val = readl_relaxed(zx_spdif->reg_base + ZX_CTRL);
|
||||
val &= ~ZX_CTRL_MODA_MASK;
|
||||
switch (params_format(params)) {
|
||||
case SNDRV_PCM_FORMAT_S16_LE:
|
||||
val |= ZX_CTRL_MODA_16;
|
||||
break;
|
||||
|
||||
case SNDRV_PCM_FORMAT_S18_3LE:
|
||||
val |= ZX_CTRL_MODA_18;
|
||||
break;
|
||||
|
||||
case SNDRV_PCM_FORMAT_S20_3LE:
|
||||
val |= ZX_CTRL_MODA_20;
|
||||
break;
|
||||
|
||||
case SNDRV_PCM_FORMAT_S24_LE:
|
||||
val |= ZX_CTRL_MODA_24;
|
||||
break;
|
||||
default:
|
||||
dev_err(socdai->dev, "Format not support!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ch_num = params_channels(params);
|
||||
if (ch_num == 2)
|
||||
val |= ZX_CTRL_DOUBLE_TRACK;
|
||||
else
|
||||
val |= ZX_CTRL_LEFT_TRACK;
|
||||
writel_relaxed(val, zx_spdif->reg_base + ZX_CTRL);
|
||||
|
||||
val = readl_relaxed(zx_spdif->reg_base + ZX_VALID_BIT);
|
||||
val &= ~ZX_VALID_TRACK_MASK;
|
||||
if (ch_num == 2)
|
||||
val |= ZX_VALID_DOUBLE_TRACK;
|
||||
else
|
||||
val |= ZX_VALID_RIGHT_TRACK;
|
||||
writel_relaxed(val, zx_spdif->reg_base + ZX_VALID_BIT);
|
||||
|
||||
rate = params_rate(params);
|
||||
ret = zx_spdif_chanstats(zx_spdif->reg_base, rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
return clk_set_rate(spdif->dai_clk, rate * ch_num * ZX_SPDIF_CLK_RAT);
|
||||
}
|
||||
|
||||
static void zx_spdif_cfg_tx(void __iomem *base, int on)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl_relaxed(base + ZX_CTRL);
|
||||
val &= ~(ZX_CTRL_ENB_MASK | ZX_CTRL_TX_MASK);
|
||||
val |= on ? ZX_CTRL_OPEN : ZX_CTRL_CLOSE;
|
||||
writel_relaxed(val, base + ZX_CTRL);
|
||||
|
||||
val = readl_relaxed(base + ZX_FIFOCTRL);
|
||||
val &= ~ZX_FIFOCTRL_TX_DMA_EN_MASK;
|
||||
if (on)
|
||||
val |= ZX_FIFOCTRL_TX_DMA_EN;
|
||||
writel_relaxed(val, base + ZX_FIFOCTRL);
|
||||
}
|
||||
|
||||
static int zx_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
u32 val;
|
||||
struct zx_spdif_info *zx_spdif = dev_get_drvdata(dai->dev);
|
||||
int ret = 0;
|
||||
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
val = readl_relaxed(zx_spdif->reg_base + ZX_FIFOCTRL);
|
||||
val |= ZX_FIFOCTRL_TX_FIFO_RST;
|
||||
writel_relaxed(val, zx_spdif->reg_base + ZX_FIFOCTRL);
|
||||
fallthrough;
|
||||
case SNDRV_PCM_TRIGGER_RESUME:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
||||
zx_spdif_cfg_tx(zx_spdif->reg_base, true);
|
||||
break;
|
||||
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
case SNDRV_PCM_TRIGGER_SUSPEND:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
zx_spdif_cfg_tx(zx_spdif->reg_base, false);
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int zx_spdif_startup(struct snd_pcm_substream *substream,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct zx_spdif_info *zx_spdif = dev_get_drvdata(dai->dev);
|
||||
|
||||
return clk_prepare_enable(zx_spdif->dai_clk);
|
||||
}
|
||||
|
||||
static void zx_spdif_shutdown(struct snd_pcm_substream *substream,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct zx_spdif_info *zx_spdif = dev_get_drvdata(dai->dev);
|
||||
|
||||
clk_disable_unprepare(zx_spdif->dai_clk);
|
||||
}
|
||||
|
||||
#define ZX_RATES \
|
||||
(SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
|
||||
SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |\
|
||||
SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
|
||||
|
||||
#define ZX_FORMAT \
|
||||
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE \
|
||||
| SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE)
|
||||
|
||||
static const struct snd_soc_dai_ops zx_spdif_dai_ops = {
|
||||
.trigger = zx_spdif_trigger,
|
||||
.startup = zx_spdif_startup,
|
||||
.shutdown = zx_spdif_shutdown,
|
||||
.hw_params = zx_spdif_hw_params,
|
||||
};
|
||||
|
||||
static struct snd_soc_dai_driver zx_spdif_dai = {
|
||||
.name = "spdif",
|
||||
.id = 0,
|
||||
.probe = zx_spdif_dai_probe,
|
||||
.playback = {
|
||||
.channels_min = 1,
|
||||
.channels_max = 2,
|
||||
.rates = ZX_RATES,
|
||||
.formats = ZX_FORMAT,
|
||||
},
|
||||
.ops = &zx_spdif_dai_ops,
|
||||
};
|
||||
|
||||
static const struct snd_soc_component_driver zx_spdif_component = {
|
||||
.name = "spdif",
|
||||
};
|
||||
|
||||
static void zx_spdif_dev_init(void __iomem *base)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
writel_relaxed(0, base + ZX_CTRL);
|
||||
writel_relaxed(0, base + ZX_INT_MASK);
|
||||
writel_relaxed(0xf, base + ZX_INT_STATUS);
|
||||
writel_relaxed(0x1, base + ZX_FIFOCTRL);
|
||||
|
||||
val = readl_relaxed(base + ZX_FIFOCTRL);
|
||||
val &= ~(ZX_FIFOCTRL_TXTH_MASK | ZX_FIFOCTRL_TX_FIFO_RST_MASK);
|
||||
val |= ZX_FIFOCTRL_TXTH(8);
|
||||
writel_relaxed(val, base + ZX_FIFOCTRL);
|
||||
}
|
||||
|
||||
static int zx_spdif_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
struct zx_spdif_info *zx_spdif;
|
||||
int ret;
|
||||
|
||||
zx_spdif = devm_kzalloc(&pdev->dev, sizeof(*zx_spdif), GFP_KERNEL);
|
||||
if (!zx_spdif)
|
||||
return -ENOMEM;
|
||||
|
||||
zx_spdif->dai_clk = devm_clk_get(&pdev->dev, "tx");
|
||||
if (IS_ERR(zx_spdif->dai_clk)) {
|
||||
dev_err(&pdev->dev, "Fail to get clk\n");
|
||||
return PTR_ERR(zx_spdif->dai_clk);
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
zx_spdif->mapbase = res->start;
|
||||
zx_spdif->reg_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(zx_spdif->reg_base)) {
|
||||
return PTR_ERR(zx_spdif->reg_base);
|
||||
}
|
||||
|
||||
zx_spdif_dev_init(zx_spdif->reg_base);
|
||||
platform_set_drvdata(pdev, zx_spdif);
|
||||
|
||||
ret = devm_snd_soc_register_component(&pdev->dev, &zx_spdif_component,
|
||||
&zx_spdif_dai, 1);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Register DAI failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
|
||||
if (ret)
|
||||
dev_err(&pdev->dev, "Register platform PCM failed: %d\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id zx_spdif_dt_ids[] = {
|
||||
{ .compatible = "zte,zx296702-spdif", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, zx_spdif_dt_ids);
|
||||
|
||||
static struct platform_driver spdif_driver = {
|
||||
.probe = zx_spdif_probe,
|
||||
.driver = {
|
||||
.name = "zx-spdif",
|
||||
.of_match_table = zx_spdif_dt_ids,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(spdif_driver);
|
||||
|
||||
MODULE_AUTHOR("Jun Nie <jun.nie@linaro.org>");
|
||||
MODULE_DESCRIPTION("ZTE SPDIF SoC DAI");
|
||||
MODULE_LICENSE("GPL");
|
|
@ -1,458 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* ZTE's TDM driver
|
||||
*
|
||||
* Copyright (C) 2017 ZTE Ltd
|
||||
*
|
||||
* Author: Baoyou Xie <baoyou.xie@linaro.org>
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <sound/dmaengine_pcm.h>
|
||||
#include <sound/pcm_params.h>
|
||||
#include <sound/soc.h>
|
||||
#include <sound/soc-dai.h>
|
||||
|
||||
#define REG_TIMING_CTRL 0x04
|
||||
#define REG_TX_FIFO_CTRL 0x0C
|
||||
#define REG_RX_FIFO_CTRL 0x10
|
||||
#define REG_INT_EN 0x1C
|
||||
#define REG_INT_STATUS 0x20
|
||||
#define REG_DATABUF 0x24
|
||||
#define REG_TS_MASK0 0x44
|
||||
#define REG_PROCESS_CTRL 0x54
|
||||
|
||||
#define FIFO_CTRL_TX_RST BIT(0)
|
||||
#define FIFO_CTRL_RX_RST BIT(0)
|
||||
#define DEAGULT_FIFO_THRES GENMASK(4, 2)
|
||||
|
||||
#define FIFO_CTRL_TX_DMA_EN BIT(1)
|
||||
#define FIFO_CTRL_RX_DMA_EN BIT(1)
|
||||
|
||||
#define TX_FIFO_RST_MASK BIT(0)
|
||||
#define RX_FIFO_RST_MASK BIT(0)
|
||||
|
||||
#define FIFOCTRL_TX_FIFO_RST BIT(0)
|
||||
#define FIFOCTRL_RX_FIFO_RST BIT(0)
|
||||
|
||||
#define TXTH_MASK GENMASK(5, 2)
|
||||
#define RXTH_MASK GENMASK(5, 2)
|
||||
|
||||
#define FIFOCTRL_THRESHOLD(x) ((x) << 2)
|
||||
|
||||
#define TIMING_MS_MASK BIT(1)
|
||||
/*
|
||||
* 00: 8 clk cycles every timeslot
|
||||
* 01: 16 clk cycles every timeslot
|
||||
* 10: 32 clk cycles every timeslot
|
||||
*/
|
||||
#define TIMING_SYNC_WIDTH_MASK GENMASK(6, 5)
|
||||
#define TIMING_WIDTH_SHIFT 5
|
||||
#define TIMING_DEFAULT_WIDTH 0
|
||||
#define TIMING_TS_WIDTH(x) ((x) << TIMING_WIDTH_SHIFT)
|
||||
#define TIMING_WIDTH_FACTOR 8
|
||||
|
||||
#define TIMING_MASTER_MODE BIT(21)
|
||||
#define TIMING_LSB_FIRST BIT(20)
|
||||
#define TIMING_TS_NUM(x) (((x) - 1) << 7)
|
||||
#define TIMING_CLK_SEL_MASK GENMASK(2, 0)
|
||||
#define TIMING_CLK_SEL_DEF BIT(2)
|
||||
|
||||
#define PROCESS_TX_EN BIT(0)
|
||||
#define PROCESS_RX_EN BIT(1)
|
||||
#define PROCESS_TDM_EN BIT(2)
|
||||
#define PROCESS_DISABLE_ALL 0
|
||||
|
||||
#define INT_DISABLE_ALL 0
|
||||
#define INT_STATUS_MASK GENMASK(6, 0)
|
||||
|
||||
struct zx_tdm_info {
|
||||
struct snd_dmaengine_dai_dma_data dma_playback;
|
||||
struct snd_dmaengine_dai_dma_data dma_capture;
|
||||
resource_size_t phy_addr;
|
||||
void __iomem *regbase;
|
||||
struct clk *dai_wclk;
|
||||
struct clk *dai_pclk;
|
||||
int master;
|
||||
struct device *dev;
|
||||
};
|
||||
|
||||
static inline u32 zx_tdm_readl(struct zx_tdm_info *tdm, u16 reg)
|
||||
{
|
||||
return readl_relaxed(tdm->regbase + reg);
|
||||
}
|
||||
|
||||
static inline void zx_tdm_writel(struct zx_tdm_info *tdm, u16 reg, u32 val)
|
||||
{
|
||||
writel_relaxed(val, tdm->regbase + reg);
|
||||
}
|
||||
|
||||
static void zx_tdm_tx_en(struct zx_tdm_info *tdm, bool on)
|
||||
{
|
||||
unsigned long val;
|
||||
|
||||
val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);
|
||||
if (on)
|
||||
val |= PROCESS_TX_EN | PROCESS_TDM_EN;
|
||||
else
|
||||
val &= ~(PROCESS_TX_EN | PROCESS_TDM_EN);
|
||||
zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);
|
||||
}
|
||||
|
||||
static void zx_tdm_rx_en(struct zx_tdm_info *tdm, bool on)
|
||||
{
|
||||
unsigned long val;
|
||||
|
||||
val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);
|
||||
if (on)
|
||||
val |= PROCESS_RX_EN | PROCESS_TDM_EN;
|
||||
else
|
||||
val &= ~(PROCESS_RX_EN | PROCESS_TDM_EN);
|
||||
zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);
|
||||
}
|
||||
|
||||
static void zx_tdm_tx_dma_en(struct zx_tdm_info *tdm, bool on)
|
||||
{
|
||||
unsigned long val;
|
||||
|
||||
val = zx_tdm_readl(tdm, REG_TX_FIFO_CTRL);
|
||||
val |= FIFO_CTRL_TX_RST | DEAGULT_FIFO_THRES;
|
||||
if (on)
|
||||
val |= FIFO_CTRL_TX_DMA_EN;
|
||||
else
|
||||
val &= ~FIFO_CTRL_TX_DMA_EN;
|
||||
zx_tdm_writel(tdm, REG_TX_FIFO_CTRL, val);
|
||||
}
|
||||
|
||||
static void zx_tdm_rx_dma_en(struct zx_tdm_info *tdm, bool on)
|
||||
{
|
||||
unsigned long val;
|
||||
|
||||
val = zx_tdm_readl(tdm, REG_RX_FIFO_CTRL);
|
||||
val |= FIFO_CTRL_RX_RST | DEAGULT_FIFO_THRES;
|
||||
if (on)
|
||||
val |= FIFO_CTRL_RX_DMA_EN;
|
||||
else
|
||||
val &= ~FIFO_CTRL_RX_DMA_EN;
|
||||
zx_tdm_writel(tdm, REG_RX_FIFO_CTRL, val);
|
||||
}
|
||||
|
||||
#define ZX_TDM_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000)
|
||||
|
||||
#define ZX_TDM_FMTBIT \
|
||||
(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_MU_LAW | \
|
||||
SNDRV_PCM_FMTBIT_A_LAW)
|
||||
|
||||
static int zx_tdm_dai_probe(struct snd_soc_dai *dai)
|
||||
{
|
||||
struct zx_tdm_info *zx_tdm = dev_get_drvdata(dai->dev);
|
||||
|
||||
snd_soc_dai_set_drvdata(dai, zx_tdm);
|
||||
zx_tdm->dma_playback.addr = zx_tdm->phy_addr + REG_DATABUF;
|
||||
zx_tdm->dma_playback.maxburst = 16;
|
||||
zx_tdm->dma_capture.addr = zx_tdm->phy_addr + REG_DATABUF;
|
||||
zx_tdm->dma_capture.maxburst = 16;
|
||||
snd_soc_dai_init_dma_data(dai, &zx_tdm->dma_playback,
|
||||
&zx_tdm->dma_capture);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int zx_tdm_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
|
||||
{
|
||||
struct zx_tdm_info *tdm = snd_soc_dai_get_drvdata(cpu_dai);
|
||||
unsigned long val;
|
||||
|
||||
val = zx_tdm_readl(tdm, REG_TIMING_CTRL);
|
||||
val &= ~(TIMING_SYNC_WIDTH_MASK | TIMING_MS_MASK);
|
||||
val |= TIMING_DEFAULT_WIDTH << TIMING_WIDTH_SHIFT;
|
||||
|
||||
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
||||
case SND_SOC_DAIFMT_CBM_CFM:
|
||||
tdm->master = 1;
|
||||
val |= TIMING_MASTER_MODE;
|
||||
break;
|
||||
case SND_SOC_DAIFMT_CBS_CFS:
|
||||
tdm->master = 0;
|
||||
val &= ~TIMING_MASTER_MODE;
|
||||
break;
|
||||
default:
|
||||
dev_err(cpu_dai->dev, "Unknown master/slave format\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
||||
zx_tdm_writel(tdm, REG_TIMING_CTRL, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int zx_tdm_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params,
|
||||
struct snd_soc_dai *socdai)
|
||||
{
|
||||
struct zx_tdm_info *tdm = snd_soc_dai_get_drvdata(socdai);
|
||||
struct snd_dmaengine_dai_dma_data *dma_data;
|
||||
unsigned int ts_width = TIMING_DEFAULT_WIDTH;
|
||||
unsigned int ch_num = 32;
|
||||
unsigned int mask = 0;
|
||||
unsigned int ret = 0;
|
||||
unsigned long val;
|
||||
|
||||
dma_data = snd_soc_dai_get_dma_data(socdai, substream);
|
||||
dma_data->addr_width = ch_num >> 3;
|
||||
|
||||
switch (params_format(params)) {
|
||||
case SNDRV_PCM_FORMAT_MU_LAW:
|
||||
case SNDRV_PCM_FORMAT_A_LAW:
|
||||
case SNDRV_PCM_FORMAT_S16_LE:
|
||||
ts_width = 1;
|
||||
break;
|
||||
default:
|
||||
dev_err(socdai->dev, "Unknown data format\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
val = zx_tdm_readl(tdm, REG_TIMING_CTRL);
|
||||
val |= TIMING_TS_WIDTH(ts_width) | TIMING_TS_NUM(1);
|
||||
zx_tdm_writel(tdm, REG_TIMING_CTRL, val);
|
||||
zx_tdm_writel(tdm, REG_TS_MASK0, mask);
|
||||
|
||||
if (tdm->master)
|
||||
ret = clk_set_rate(tdm->dai_wclk,
|
||||
params_rate(params) * TIMING_WIDTH_FACTOR * ch_num);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int zx_tdm_trigger(struct snd_pcm_substream *substream, int cmd,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
|
||||
struct zx_tdm_info *zx_tdm = dev_get_drvdata(dai->dev);
|
||||
unsigned int val;
|
||||
int ret = 0;
|
||||
|
||||
switch (cmd) {
|
||||
case SNDRV_PCM_TRIGGER_START:
|
||||
if (capture) {
|
||||
val = zx_tdm_readl(zx_tdm, REG_RX_FIFO_CTRL);
|
||||
val |= FIFOCTRL_RX_FIFO_RST;
|
||||
zx_tdm_writel(zx_tdm, REG_RX_FIFO_CTRL, val);
|
||||
|
||||
zx_tdm_rx_dma_en(zx_tdm, true);
|
||||
} else {
|
||||
val = zx_tdm_readl(zx_tdm, REG_TX_FIFO_CTRL);
|
||||
val |= FIFOCTRL_TX_FIFO_RST;
|
||||
zx_tdm_writel(zx_tdm, REG_TX_FIFO_CTRL, val);
|
||||
|
||||
zx_tdm_tx_dma_en(zx_tdm, true);
|
||||
}
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_RESUME:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
||||
if (capture)
|
||||
zx_tdm_rx_en(zx_tdm, true);
|
||||
else
|
||||
zx_tdm_tx_en(zx_tdm, true);
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_STOP:
|
||||
if (capture)
|
||||
zx_tdm_rx_dma_en(zx_tdm, false);
|
||||
else
|
||||
zx_tdm_tx_dma_en(zx_tdm, false);
|
||||
break;
|
||||
case SNDRV_PCM_TRIGGER_SUSPEND:
|
||||
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
||||
if (capture)
|
||||
zx_tdm_rx_en(zx_tdm, false);
|
||||
else
|
||||
zx_tdm_tx_en(zx_tdm, false);
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int zx_tdm_startup(struct snd_pcm_substream *substream,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct zx_tdm_info *zx_tdm = dev_get_drvdata(dai->dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(zx_tdm->dai_wclk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_prepare_enable(zx_tdm->dai_pclk);
|
||||
if (ret) {
|
||||
clk_disable_unprepare(zx_tdm->dai_wclk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void zx_tdm_shutdown(struct snd_pcm_substream *substream,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
struct zx_tdm_info *zx_tdm = dev_get_drvdata(dai->dev);
|
||||
|
||||
clk_disable_unprepare(zx_tdm->dai_pclk);
|
||||
clk_disable_unprepare(zx_tdm->dai_wclk);
|
||||
}
|
||||
|
||||
static const struct snd_soc_dai_ops zx_tdm_dai_ops = {
|
||||
.trigger = zx_tdm_trigger,
|
||||
.hw_params = zx_tdm_hw_params,
|
||||
.set_fmt = zx_tdm_set_fmt,
|
||||
.startup = zx_tdm_startup,
|
||||
.shutdown = zx_tdm_shutdown,
|
||||
};
|
||||
|
||||
static const struct snd_soc_component_driver zx_tdm_component = {
|
||||
.name = "zx-tdm",
|
||||
};
|
||||
|
||||
static void zx_tdm_init_state(struct zx_tdm_info *tdm)
|
||||
{
|
||||
unsigned int val;
|
||||
|
||||
zx_tdm_writel(tdm, REG_PROCESS_CTRL, PROCESS_DISABLE_ALL);
|
||||
|
||||
val = zx_tdm_readl(tdm, REG_TIMING_CTRL);
|
||||
val |= TIMING_LSB_FIRST;
|
||||
val &= ~TIMING_CLK_SEL_MASK;
|
||||
val |= TIMING_CLK_SEL_DEF;
|
||||
zx_tdm_writel(tdm, REG_TIMING_CTRL, val);
|
||||
|
||||
zx_tdm_writel(tdm, REG_INT_EN, INT_DISABLE_ALL);
|
||||
/*
|
||||
* write INT_STATUS register to clear it.
|
||||
*/
|
||||
zx_tdm_writel(tdm, REG_INT_STATUS, INT_STATUS_MASK);
|
||||
zx_tdm_writel(tdm, REG_RX_FIFO_CTRL, FIFOCTRL_RX_FIFO_RST);
|
||||
zx_tdm_writel(tdm, REG_TX_FIFO_CTRL, FIFOCTRL_TX_FIFO_RST);
|
||||
|
||||
val = zx_tdm_readl(tdm, REG_RX_FIFO_CTRL);
|
||||
val &= ~(RXTH_MASK | RX_FIFO_RST_MASK);
|
||||
val |= FIFOCTRL_THRESHOLD(8);
|
||||
zx_tdm_writel(tdm, REG_RX_FIFO_CTRL, val);
|
||||
|
||||
val = zx_tdm_readl(tdm, REG_TX_FIFO_CTRL);
|
||||
val &= ~(TXTH_MASK | TX_FIFO_RST_MASK);
|
||||
val |= FIFOCTRL_THRESHOLD(8);
|
||||
zx_tdm_writel(tdm, REG_TX_FIFO_CTRL, val);
|
||||
}
|
||||
|
||||
static struct snd_soc_dai_driver zx_tdm_dai = {
|
||||
.name = "zx-tdm-dai",
|
||||
.id = 0,
|
||||
.probe = zx_tdm_dai_probe,
|
||||
.playback = {
|
||||
.channels_min = 1,
|
||||
.channels_max = 4,
|
||||
.rates = ZX_TDM_RATES,
|
||||
.formats = ZX_TDM_FMTBIT,
|
||||
},
|
||||
.capture = {
|
||||
.channels_min = 1,
|
||||
.channels_max = 4,
|
||||
.rates = ZX_TDM_RATES,
|
||||
.formats = ZX_TDM_FMTBIT,
|
||||
},
|
||||
.ops = &zx_tdm_dai_ops,
|
||||
};
|
||||
|
||||
static int zx_tdm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct of_phandle_args out_args;
|
||||
unsigned int dma_reg_offset;
|
||||
struct zx_tdm_info *zx_tdm;
|
||||
unsigned int dma_mask;
|
||||
struct resource *res;
|
||||
struct regmap *regmap_sysctrl;
|
||||
int ret;
|
||||
|
||||
zx_tdm = devm_kzalloc(&pdev->dev, sizeof(*zx_tdm), GFP_KERNEL);
|
||||
if (!zx_tdm)
|
||||
return -ENOMEM;
|
||||
|
||||
zx_tdm->dev = &pdev->dev;
|
||||
|
||||
zx_tdm->dai_wclk = devm_clk_get(&pdev->dev, "wclk");
|
||||
if (IS_ERR(zx_tdm->dai_wclk)) {
|
||||
dev_err(&pdev->dev, "Fail to get wclk\n");
|
||||
return PTR_ERR(zx_tdm->dai_wclk);
|
||||
}
|
||||
|
||||
zx_tdm->dai_pclk = devm_clk_get(&pdev->dev, "pclk");
|
||||
if (IS_ERR(zx_tdm->dai_pclk)) {
|
||||
dev_err(&pdev->dev, "Fail to get pclk\n");
|
||||
return PTR_ERR(zx_tdm->dai_pclk);
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
zx_tdm->phy_addr = res->start;
|
||||
zx_tdm->regbase = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(zx_tdm->regbase))
|
||||
return PTR_ERR(zx_tdm->regbase);
|
||||
|
||||
ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
|
||||
"zte,tdm-dma-sysctrl", 2, 0, &out_args);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Fail to get zte,tdm-dma-sysctrl\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
dma_reg_offset = out_args.args[0];
|
||||
dma_mask = out_args.args[1];
|
||||
regmap_sysctrl = syscon_node_to_regmap(out_args.np);
|
||||
if (IS_ERR(regmap_sysctrl)) {
|
||||
of_node_put(out_args.np);
|
||||
return PTR_ERR(regmap_sysctrl);
|
||||
}
|
||||
|
||||
regmap_update_bits(regmap_sysctrl, dma_reg_offset, dma_mask, dma_mask);
|
||||
of_node_put(out_args.np);
|
||||
|
||||
zx_tdm_init_state(zx_tdm);
|
||||
platform_set_drvdata(pdev, zx_tdm);
|
||||
|
||||
ret = devm_snd_soc_register_component(&pdev->dev, &zx_tdm_component,
|
||||
&zx_tdm_dai, 1);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Register DAI failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
|
||||
if (ret)
|
||||
dev_err(&pdev->dev, "Register platform PCM failed: %d\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id zx_tdm_dt_ids[] = {
|
||||
{ .compatible = "zte,zx296718-tdm", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, zx_tdm_dt_ids);
|
||||
|
||||
static struct platform_driver tdm_driver = {
|
||||
.probe = zx_tdm_probe,
|
||||
.driver = {
|
||||
.name = "zx-tdm",
|
||||
.of_match_table = zx_tdm_dt_ids,
|
||||
},
|
||||
};
|
||||
module_platform_driver(tdm_driver);
|
||||
|
||||
MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
|
||||
MODULE_DESCRIPTION("ZTE TDM DAI driver");
|
||||
MODULE_LICENSE("GPL v2");
|
Loading…
Reference in a new issue