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@ -15,6 +15,10 @@
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifdef CONFIG_MSM_OCMEM
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# include <mach/ocmem.h>
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#endif
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#include "a3xx_gpu.h"
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#define A3XX_INT0_MASK \
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@ -63,6 +67,7 @@ static void a3xx_me_init(struct msm_gpu *gpu)
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static int a3xx_hw_init(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct a3xx_gpu *a3xx_gpu = to_a3xx_gpu(adreno_gpu);
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uint32_t *ptr, len;
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int i, ret;
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@ -105,6 +110,21 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
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gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x000000ff);
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gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
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} else if (adreno_is_a330v2(adreno_gpu)) {
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/*
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* Most of the VBIF registers on 8974v2 have the correct
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* values at power on, so we won't modify those if we don't
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* need to
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*/
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/* Enable 1k sort: */
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gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f);
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gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
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/* Enable WR-REQ: */
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gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003f);
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gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);
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/* Set up VBIF_ROUND_ROBIN_QOS_ARB: */
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gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
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} else if (adreno_is_a330(adreno_gpu)) {
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/* Set up 16 deep read/write request queues: */
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gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);
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@ -121,10 +141,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
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/* Set up VBIF_ROUND_ROBIN_QOS_ARB: */
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gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0001);
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/* Set up AOOO: */
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gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000ffff);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0xffffffff);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003f);
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gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003f003f);
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/* Enable 1K sort: */
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gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001ffff);
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gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f);
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gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
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/* Disable VBIF clock gating. This is to enable AXI running
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* higher frequency than GPU:
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@ -162,14 +182,23 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
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gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);
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/* Enable Clock gating: */
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gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);
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if (adreno_is_a320(adreno_gpu))
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gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);
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else if (adreno_is_a330v2(adreno_gpu))
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gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
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else if (adreno_is_a330(adreno_gpu))
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gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbffcffff);
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/* Set the OCMEM base address for A330 */
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//TODO:
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// if (adreno_is_a330(adreno_gpu)) {
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// gpu_write(gpu, REG_A3XX_RB_GMEM_BASE_ADDR,
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// (unsigned int)(a3xx_gpu->ocmem_base >> 14));
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// }
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if (adreno_is_a330v2(adreno_gpu))
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gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x05515455);
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else if (adreno_is_a330(adreno_gpu))
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gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x00000000);
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/* Set the OCMEM base address for A330, etc */
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if (a3xx_gpu->ocmem_hdl) {
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gpu_write(gpu, REG_A3XX_RB_GMEM_BASE_ADDR,
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(unsigned int)(a3xx_gpu->ocmem_base >> 14));
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}
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/* Turn on performance counters: */
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gpu_write(gpu, REG_A3XX_RBBM_PERFCTR_CTL, 0x01);
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@ -238,12 +267,19 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
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gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);
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/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */
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if (adreno_is_a305(adreno_gpu) || adreno_is_a320(adreno_gpu))
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if (adreno_is_a305(adreno_gpu) || adreno_is_a320(adreno_gpu)) {
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gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,
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AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |
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AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |
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AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(14));
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} else if (adreno_is_a330(adreno_gpu)) {
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/* NOTE: this (value take from downstream android driver)
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* includes some bits outside of the known bitfields. But
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* A330 has this "MERCIU queue" thing too, which might
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* explain a new bitfield or reshuffling:
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*/
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gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, 0x003e2008);
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}
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/* clear ME_HALT to start micro engine */
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gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0);
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@ -253,6 +289,14 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
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return 0;
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}
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static void a3xx_recover(struct msm_gpu *gpu)
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{
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gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 1);
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gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD);
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gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 0);
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adreno_recover(gpu);
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}
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static void a3xx_destroy(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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@ -261,6 +305,12 @@ static void a3xx_destroy(struct msm_gpu *gpu)
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DBG("%s", gpu->name);
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adreno_gpu_cleanup(adreno_gpu);
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#ifdef CONFIG_MSM_OCMEM
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if (a3xx_gpu->ocmem_base)
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ocmem_free(OCMEM_GRAPHICS, a3xx_gpu->ocmem_hdl);
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#endif
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put_device(&a3xx_gpu->pdev->dev);
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kfree(a3xx_gpu);
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}
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@ -371,7 +421,7 @@ static const struct adreno_gpu_funcs funcs = {
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.hw_init = a3xx_hw_init,
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.pm_suspend = msm_gpu_pm_suspend,
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.pm_resume = msm_gpu_pm_resume,
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.recover = adreno_recover,
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.recover = a3xx_recover,
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.last_fence = adreno_last_fence,
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.submit = adreno_submit,
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.flush = adreno_flush,
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@ -387,6 +437,7 @@ static const struct adreno_gpu_funcs funcs = {
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struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
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{
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struct a3xx_gpu *a3xx_gpu = NULL;
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struct adreno_gpu *adreno_gpu;
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struct msm_gpu *gpu;
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struct platform_device *pdev = a3xx_pdev;
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struct adreno_platform_config *config;
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@ -406,7 +457,8 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
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goto fail;
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}
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gpu = &a3xx_gpu->base.base;
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adreno_gpu = &a3xx_gpu->base;
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gpu = &adreno_gpu->base;
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get_device(&pdev->dev);
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a3xx_gpu->pdev = pdev;
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@ -421,11 +473,25 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
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DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
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gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
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ret = adreno_gpu_init(dev, pdev, &a3xx_gpu->base,
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&funcs, config->rev);
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ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, config->rev);
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if (ret)
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goto fail;
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/* if needed, allocate gmem: */
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if (adreno_is_a330(adreno_gpu)) {
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#ifdef CONFIG_MSM_OCMEM
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/* TODO this is different/missing upstream: */
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struct ocmem_buf *ocmem_hdl =
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ocmem_allocate(OCMEM_GRAPHICS, adreno_gpu->gmem);
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a3xx_gpu->ocmem_hdl = ocmem_hdl;
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a3xx_gpu->ocmem_base = ocmem_hdl->addr;
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adreno_gpu->gmem = ocmem_hdl->len;
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DBG("using %dK of OCMEM at 0x%08x", adreno_gpu->gmem / 1024,
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a3xx_gpu->ocmem_base);
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#endif
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}
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if (!gpu->mmu) {
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/* TODO we think it is possible to configure the GPU to
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* restrict access to VRAM carveout. But the required
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@ -460,7 +526,42 @@ static int a3xx_probe(struct platform_device *pdev)
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{
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static struct adreno_platform_config config = {};
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#ifdef CONFIG_OF
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/* TODO */
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struct device_node *child, *node = pdev->dev.of_node;
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u32 val;
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int ret;
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ret = of_property_read_u32(node, "qcom,chipid", &val);
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if (ret) {
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dev_err(&pdev->dev, "could not find chipid: %d\n", ret);
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return ret;
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}
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config.rev = ADRENO_REV((val >> 24) & 0xff,
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(val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
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/* find clock rates: */
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config.fast_rate = 0;
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config.slow_rate = ~0;
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for_each_child_of_node(node, child) {
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if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
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struct device_node *pwrlvl;
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for_each_child_of_node(child, pwrlvl) {
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ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val);
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if (ret) {
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dev_err(&pdev->dev, "could not find gpu-freq: %d\n", ret);
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return ret;
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}
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config.fast_rate = max(config.fast_rate, val);
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config.slow_rate = min(config.slow_rate, val);
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}
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}
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}
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if (!config.fast_rate) {
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dev_err(&pdev->dev, "could not find clk rates\n");
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return -ENXIO;
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}
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#else
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struct kgsl_device_platform_data *pdata = pdev->dev.platform_data;
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uint32_t version = socinfo_get_version();
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@ -519,10 +620,19 @@ static int a3xx_remove(struct platform_device *pdev)
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return 0;
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}
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static const struct of_device_id dt_match[] = {
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{ .compatible = "qcom,kgsl-3d0" },
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{}
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};
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MODULE_DEVICE_TABLE(of, dt_match);
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static struct platform_driver a3xx_driver = {
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.probe = a3xx_probe,
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.remove = a3xx_remove,
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.driver.name = "kgsl-3d0",
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.driver = {
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.name = "kgsl-3d0",
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.of_match_table = dt_match,
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},
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};
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void __init a3xx_register(void)
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