Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull intel drm fixes from Dave Airlie: "Intel fixes came in late, but since I debugged one of them I'll send them on, Two reverts, a quirk and one warn regression" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: Revert "drm/i915: reverse dp link param selection, prefer fast over wide again" drm/i915: Track the primary plane correctly when reassigning planes drm/i915: Ignore VBT backlight presence check on HP Chromebook 14 Revert "drm/i915: Don't set the 8to6 dither flag when not scaling"
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commit
5556ea4df6
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@ -11673,6 +11673,9 @@ static struct intel_quirk intel_quirks[] = {
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/* Toshiba CB35 Chromebook (Celeron 2955U) */
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/* Toshiba CB35 Chromebook (Celeron 2955U) */
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{ 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
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{ 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
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/* HP Chromebook 14 (Celeron 2955U) */
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{ 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
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};
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};
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static void intel_init_quirks(struct drm_device *dev)
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static void intel_init_quirks(struct drm_device *dev)
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@ -11911,6 +11914,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
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* ... */
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* ... */
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plane = crtc->plane;
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plane = crtc->plane;
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crtc->plane = !plane;
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crtc->plane = !plane;
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crtc->primary_enabled = true;
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dev_priv->display.crtc_disable(&crtc->base);
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dev_priv->display.crtc_disable(&crtc->base);
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crtc->plane = plane;
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crtc->plane = plane;
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@ -906,8 +906,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
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mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
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bpp);
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bpp);
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for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
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for (clock = min_clock; clock <= max_clock; clock++) {
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for (clock = min_clock; clock <= max_clock; clock++) {
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for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
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link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
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link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
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link_avail = intel_dp_max_data_rate(link_clock,
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link_avail = intel_dp_max_data_rate(link_clock,
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lane_count);
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lane_count);
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@ -111,6 +111,13 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
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pipe_config->adjusted_mode.flags |= flags;
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pipe_config->adjusted_mode.flags |= flags;
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/* gen2/3 store dither state in pfit control, needs to match */
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if (INTEL_INFO(dev)->gen < 4) {
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tmp = I915_READ(PFIT_CONTROL);
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pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
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}
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dotclock = pipe_config->port_clock;
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dotclock = pipe_config->port_clock;
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if (HAS_PCH_SPLIT(dev_priv->dev))
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if (HAS_PCH_SPLIT(dev_priv->dev))
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@ -361,16 +361,16 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
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pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
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pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
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PFIT_FILTER_FUZZY);
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PFIT_FILTER_FUZZY);
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/* Make sure pre-965 set dither correctly for 18bpp panels. */
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if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
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pfit_control |= PANEL_8TO6_DITHER_ENABLE;
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out:
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out:
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if ((pfit_control & PFIT_ENABLE) == 0) {
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if ((pfit_control & PFIT_ENABLE) == 0) {
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pfit_control = 0;
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pfit_control = 0;
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pfit_pgm_ratios = 0;
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pfit_pgm_ratios = 0;
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}
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}
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/* Make sure pre-965 set dither correctly for 18bpp panels. */
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if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
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pfit_control |= PANEL_8TO6_DITHER_ENABLE;
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pipe_config->gmch_pfit.control = pfit_control;
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pipe_config->gmch_pfit.control = pfit_control;
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pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
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pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
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pipe_config->gmch_pfit.lvds_border_bits = border;
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pipe_config->gmch_pfit.lvds_border_bits = border;
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