arm: omap: intc: switch over to linear irq domain
now that we don't need to support legacy board-files, we can completely switch over to a linear irq domain and make use of irq_alloc_domain_generic_chips() to allocate all generic irq chips for us. Signed-off-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -188,14 +188,51 @@ void omap3_intc_suspend(void)
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omap_ack_irq(NULL);
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}
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static __init void
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omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
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static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base)
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{
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int ret;
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int i;
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ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC",
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handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE,
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IRQ_LEVEL, 0);
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if (ret) {
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pr_warn("Failed to allocate irq chips\n");
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return ret;
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}
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for (i = 0; i < omap_nr_pending; i++) {
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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gc = irq_get_domain_generic_chip(d, 32 * i);
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gc->reg_base = base;
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ct = gc->chip_types;
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ct->type = IRQ_TYPE_LEVEL_MASK;
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ct->handler = handle_level_irq;
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ct->chip.irq_ack = omap_mask_ack_irq;
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ct->chip.irq_mask = irq_gc_mask_disable_reg;
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ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
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ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
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ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i;
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ct->regs.disable = INTC_MIR_SET0 + 32 * i;
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}
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return 0;
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}
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static void __init omap_alloc_gc_legacy(void __iomem *base,
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unsigned int irq_start, unsigned int num)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
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handle_level_irq);
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handle_level_irq);
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ct = gc->chip_types;
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ct->chip.irq_ack = omap_mask_ack_irq;
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ct->chip.irq_mask = irq_gc_mask_disable_reg;
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@ -205,16 +242,36 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
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ct->regs.enable = INTC_MIR_CLEAR0;
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ct->regs.disable = INTC_MIR_SET0;
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irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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}
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static void __init omap_init_irq(u32 base, struct device_node *node)
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static int __init omap_init_irq_of(struct device_node *node)
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{
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int ret;
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omap_irq_base = of_iomap(node, 0);
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if (WARN_ON(!omap_irq_base))
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return -ENOMEM;
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domain = irq_domain_add_linear(node, omap_nr_irqs,
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&irq_generic_chip_ops, NULL);
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omap_irq_soft_reset();
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ret = omap_alloc_gc_of(domain, omap_irq_base);
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if (ret < 0)
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irq_domain_remove(domain);
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return ret;
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}
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static int __init omap_init_irq_legacy(u32 base)
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{
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int j, irq_base;
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omap_irq_base = ioremap(base, SZ_4K);
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if (WARN_ON(!omap_irq_base))
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return;
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return -ENOMEM;
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irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
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if (irq_base < 0) {
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@ -222,13 +279,23 @@ static void __init omap_init_irq(u32 base, struct device_node *node)
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irq_base = 0;
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}
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domain = irq_domain_add_legacy(node, omap_nr_irqs, irq_base, 0,
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domain = irq_domain_add_legacy(NULL, omap_nr_irqs, irq_base, 0,
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&irq_domain_simple_ops, NULL);
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omap_irq_soft_reset();
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for (j = 0; j < omap_nr_irqs; j += 32)
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omap_alloc_gc(omap_irq_base + j, j + irq_base, 32);
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omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32);
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return 0;
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}
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static int __init omap_init_irq(u32 base, struct device_node *node)
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{
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if (node)
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return omap_init_irq_of(node);
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else
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return omap_init_irq_legacy(base);
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}
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static asmlinkage void __exception_irq_entry
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@ -294,6 +361,7 @@ static int __init intc_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct resource res;
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int ret;
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omap_nr_pending = 3;
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omap_nr_irqs = 96;
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@ -311,7 +379,9 @@ static int __init intc_of_init(struct device_node *node,
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omap_nr_pending = 4;
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}
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omap_init_irq(res.start, of_node_get(node));
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ret = omap_init_irq(-1, of_node_get(node));
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if (ret < 0)
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return ret;
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set_handle_irq(omap_intc_handle_irq);
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