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clk: tegra: Changes for v5.11-rc1 

This set consists of two fixes for minor issues that rarely, if ever,
 happen, so not urgent enough for these to go into v5.10.
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Merge tag 'for-5.11-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-tegra

Pull a couple Tegra clk driver updates from Thierry Reding:

This set consists of two fixes for minor issues that rarely, if ever,
happen, so not urgent enough for these to go into v5.10.

* tag 'for-5.11-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra: bpmp: Clamp clock rates on requests
  clk: tegra: Do not return 0 on failure
zero-sugar-mainline-defconfig
Stephen Boyd 2020-11-27 12:19:48 -08:00
parent 3650b228f8 a886c310d9
commit 55cd03e809
2 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/clk/tegra/clk-bpmp.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2016 NVIDIA Corporation
* Copyright (C) 2016-2020 NVIDIA Corporation
*/
#include <linux/clk-provider.h>
@ -174,7 +174,7 @@ static long tegra_bpmp_clk_round_rate(struct clk_hw *hw, unsigned long rate,
int err;
memset(&request, 0, sizeof(request));
request.rate = rate;
request.rate = min_t(u64, rate, S64_MAX);
memset(&msg, 0, sizeof(msg));
msg.cmd = CMD_CLK_ROUND_RATE;
@ -256,7 +256,7 @@ static int tegra_bpmp_clk_set_rate(struct clk_hw *hw, unsigned long rate,
struct tegra_bpmp_clk_message msg;
memset(&request, 0, sizeof(request));
request.rate = rate;
request.rate = min_t(u64, rate, S64_MAX);
memset(&msg, 0, sizeof(msg));
msg.cmd = CMD_CLK_SET_RATE;

4
drivers/clk/tegra/clk-dfll.c
View File

@ -1856,13 +1856,13 @@ static int dfll_fetch_pwm_params(struct tegra_dfll *td)
&td->reg_init_uV);
if (!ret) {
dev_err(td->dev, "couldn't get initialized voltage\n");
return ret;
return -EINVAL;
}
ret = read_dt_param(td, "nvidia,pwm-period-nanoseconds", &pwm_period);
if (!ret) {
dev_err(td->dev, "couldn't get PWM period\n");
return ret;
return -EINVAL;
}
td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1);