redonkable/alistair23-linux
redonkable/alistair23-linux
1
0
Fork 0
Code Releases Activity

drm/amd/powerplay: add function disable_dpm_tasks for Fiji

Browse source 
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Huang 2016-05-31 17:06:14 -04:00 committed by Alex Deucher
parent 80597521e6
commit 55d74fc921
3 changed files with 281 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

220
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
View file

@ -1236,6 +1236,34 @@ static int fiji_program_voting_clients(struct pp_hwmgr *hwmgr)
return 0;
}
static int fiji_clear_voting_clients(struct pp_hwmgr *hwmgr)
{
/* Reset voting clients before disabling DPM */
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixCG_FREQ_TRAN_VOTING_0, 0);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixCG_FREQ_TRAN_VOTING_1, 0);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixCG_FREQ_TRAN_VOTING_2, 0);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixCG_FREQ_TRAN_VOTING_3, 0);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixCG_FREQ_TRAN_VOTING_4, 0);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixCG_FREQ_TRAN_VOTING_5, 0);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixCG_FREQ_TRAN_VOTING_6, 0);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixCG_FREQ_TRAN_VOTING_7, 0);
return 0;
}
/**
* Get the location of various tables inside the FW image.
*
@ -1362,6 +1390,17 @@ static int fiji_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
return 0;
}
/**
* Call SMC to reset S0/S1 to S1 and Reset SMIO to initial value
*
* @param hwmgr the address of the powerplay hardware manager.
* @return if success then 0;
*/
static int fiji_reset_to_default(struct pp_hwmgr *hwmgr)
{
return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults);
}
/**
* Initial switch from ARB F0->F1
*
@ -1375,6 +1414,21 @@ static int fiji_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
}
static int fiji_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
{
uint32_t tmp;
tmp = (cgs_read_ind_register(hwmgr->device,
CGS_IND_REG__SMC, ixSMC_SCRATCH9) &
0x0000ff00) >> 8;
if (tmp == MC_CG_ARB_FREQ_F0)
return 0;
return fiji_copy_and_switch_arb_sets(hwmgr,
tmp, MC_CG_ARB_FREQ_F0);
}
static int fiji_reset_single_dpm_table(struct pp_hwmgr *hwmgr,
struct fiji_single_dpm_table *dpm_table, uint32_t count)
{
@ -3177,6 +3231,17 @@ static int fiji_enable_ulv(struct pp_hwmgr *hwmgr)
return 0;
}
static int fiji_disable_ulv(struct pp_hwmgr *hwmgr)
{
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
struct fiji_ulv_parm *ulv = &(data->ulv);
if (ulv->ulv_supported)
return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DisableULV);
return 0;
}
static int fiji_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
@ -3197,6 +3262,21 @@ static int fiji_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
return 0;
}
static int fiji_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
{
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep)) {
if (smum_send_msg_to_smc(hwmgr->smumgr,
PPSMC_MSG_MASTER_DeepSleep_OFF)) {
PP_ASSERT_WITH_CODE(false,
"Attempt to disable Master Deep Sleep switch failed!",
return -1);
}
}
return 0;
}
static int fiji_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
{
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
@ -3357,6 +3437,70 @@ static int fiji_start_dpm(struct pp_hwmgr *hwmgr)
return 0;
}
static int fiji_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
{
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
/* disable SCLK dpm */
if (!data->sclk_dpm_key_disabled)
PP_ASSERT_WITH_CODE(
(smum_send_msg_to_smc(hwmgr->smumgr,
PPSMC_MSG_DPM_Disable) == 0),
"Failed to disable SCLK DPM!",
return -1);
/* disable MCLK dpm */
if (!data->mclk_dpm_key_disabled) {
PP_ASSERT_WITH_CODE(
(smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
PPSMC_MSG_MCLKDPM_SetEnabledMask, 1) == 0),
"Failed to force MCLK DPM0!",
return -1);
PP_ASSERT_WITH_CODE(
(smum_send_msg_to_smc(hwmgr->smumgr,
PPSMC_MSG_MCLKDPM_Disable) == 0),
"Failed to disable MCLK DPM!",
return -1);
}
return 0;
}
static int fiji_stop_dpm(struct pp_hwmgr *hwmgr)
{
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
/* disable general power management */
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
GLOBAL_PWRMGT_EN, 0);
/* disable sclk deep sleep */
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
DYNAMIC_PM_EN, 0);
/* disable PCIE dpm */
if (!data->pcie_dpm_key_disabled) {
PP_ASSERT_WITH_CODE(
(smum_send_msg_to_smc(hwmgr->smumgr,
PPSMC_MSG_PCIeDPM_Disable) == 0),
"Failed to disable pcie DPM during DPM Stop Function!",
return -1);
}
if (fiji_disable_sclk_mclk_dpm(hwmgr)) {
printk(KERN_ERR "Failed to disable Sclk DPM and Mclk DPM!");
return -1;
}
PP_ASSERT_WITH_CODE(
(smum_send_msg_to_smc(hwmgr->smumgr,
PPSMC_MSG_Voltage_Cntl_Disable) == 0),
"Failed to disable voltage DPM during DPM Stop Function!",
return -1);
return 0;
}
static void fiji_set_dpm_event_sources(struct pp_hwmgr *hwmgr,
uint32_t sources)
{
@ -3415,6 +3559,23 @@ static int fiji_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
return fiji_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
}
static int fiji_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
PHM_AutoThrottleSource source)
{
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
if (data->active_auto_throttle_sources & (1 << source)) {
data->active_auto_throttle_sources &= ~(1 << source);
fiji_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
}
return 0;
}
static int fiji_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
{
return fiji_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
}
static int fiji_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
int tmp_result, result = 0;
@ -3529,6 +3690,64 @@ static int fiji_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
return result;
}
static int fiji_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
int tmp_result, result = 0;
tmp_result = (fiji_is_dpm_running(hwmgr)) ? 0 : -1;
PP_ASSERT_WITH_CODE(tmp_result == 0,
"DPM is not running right now, no need to disable DPM!",
return 0);
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ThermalController))
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1);
tmp_result = fiji_disable_power_containment(hwmgr);
PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to disable power containment!", result = tmp_result);
tmp_result = fiji_disable_smc_cac(hwmgr);
PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to disable SMC CAC!", result = tmp_result);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
CG_SPLL_SPREAD_SPECTRUM, SSEN, 0);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0);
tmp_result = fiji_disable_thermal_auto_throttle(hwmgr);
PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to disable thermal auto throttle!", result = tmp_result);
tmp_result = fiji_stop_dpm(hwmgr);
PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to stop DPM!", result = tmp_result);
tmp_result = fiji_disable_deep_sleep_master_switch(hwmgr);
PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to disable deep sleep master switch!", result = tmp_result);
tmp_result = fiji_disable_ulv(hwmgr);
PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to disable ULV!", result = tmp_result);
tmp_result = fiji_clear_voting_clients(hwmgr);
PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to clear voting clients!", result = tmp_result);
tmp_result = fiji_reset_to_default(hwmgr);
PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to reset to default!", result = tmp_result);
tmp_result = fiji_force_switch_to_arbf0(hwmgr);
PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to force to switch arbf0!", result = tmp_result);
return result;
}
static int fiji_force_dpm_highest(struct pp_hwmgr *hwmgr)
{
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
@ -5365,6 +5584,7 @@ static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
.backend_fini = &fiji_hwmgr_backend_fini,
.asic_setup = &fiji_setup_asic_task,
.dynamic_state_management_enable = &fiji_enable_dpm_tasks,
.dynamic_state_management_disable = &fiji_disable_dpm_tasks,
.force_dpm_level = &fiji_dpm_force_dpm_level,
.get_num_of_pp_table_entries = &tonga_get_number_of_powerplay_table_entries,
.get_power_state_size = &fiji_get_power_state_size,

59
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.c
View file

@ -460,6 +460,23 @@ int fiji_enable_smc_cac(struct pp_hwmgr *hwmgr)
return result;
}
int fiji_disable_smc_cac(struct pp_hwmgr *hwmgr)
{
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
int result = 0;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_CAC) && data->cac_enabled) {
int smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
(uint16_t)(PPSMC_MSG_DisableCac));
PP_ASSERT_WITH_CODE((smc_result == 0),
"Failed to disable CAC in SMC.", result = -1);
data->cac_enabled = false;
}
return result;
}
int fiji_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
{
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
@ -529,6 +546,48 @@ int fiji_enable_power_containment(struct pp_hwmgr *hwmgr)
return result;
}
int fiji_disable_power_containment(struct pp_hwmgr *hwmgr)
{
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
int result = 0;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment) &&
data->power_containment_features) {
int smc_result;
if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_TDCLimit) {
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
(uint16_t)(PPSMC_MSG_TDCLimitDisable));
PP_ASSERT_WITH_CODE((smc_result == 0),
"Failed to disable TDCLimit in SMC.",
result = smc_result);
}
if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_DTE) {
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
(uint16_t)(PPSMC_MSG_DisableDTE));
PP_ASSERT_WITH_CODE((smc_result == 0),
"Failed to disable DTE in SMC.",
result = smc_result);
}
if (data->power_containment_features &
POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
(uint16_t)(PPSMC_MSG_PkgPwrLimitDisable));
PP_ASSERT_WITH_CODE((smc_result == 0),
"Failed to disable PkgPwrTracking in SMC.",
result = smc_result);
}
data->power_containment_features = 0;
}
return result;
}
int fiji_power_control_set_level(struct pp_hwmgr *hwmgr)
{
struct phm_ppt_v1_information *table_info =

2
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_powertune.h
View file

@ -58,7 +58,9 @@ void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr);
int fiji_enable_smc_cac(struct pp_hwmgr *hwmgr);
int fiji_disable_smc_cac(struct pp_hwmgr *hwmgr);
int fiji_enable_power_containment(struct pp_hwmgr *hwmgr);
int fiji_disable_power_containment(struct pp_hwmgr *hwmgr);
int fiji_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
int fiji_power_control_set_level(struct pp_hwmgr *hwmgr);