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staging: rtl8188eu: Rework function _PHY_SetBWMode92C()

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Rename CamelCase variables and function name.

Signed-off-by: navin patidar <navin.patidar@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
navin patidar 2014-08-31 12:14:26 +05:30 committed by Greg Kroah-Hartman
parent a8b74c3ec7
commit 55d8dfbfaf
1 changed files with 37 additions and 61 deletions
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98
drivers/staging/rtl8188eu/hal/rtl8188e_phycfg.c
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@ -259,102 +259,78 @@ PHY_SetTxPowerLevel8188E(
rtl8188e_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0], channel); rtl8188e_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], &BW20PowerLevel[0], &BW40PowerLevel[0], channel);
} }
/*----------------------------------------------------------------------------- static void phy_set_bw_mode_callback(struct adapter *adapt)
* Function: PHY_SetBWModeCallback8192C()
*
* Overview: Timer callback function for SetSetBWMode
*
* Input: PRT_TIMER pTimer
*
* Output: NONE
*
* Return: NONE
*
* Note: (1) We do not take j mode into consideration now
* (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
* concurrently?
*---------------------------------------------------------------------------*/
static void
_PHY_SetBWMode92C(
struct adapter *Adapter
)
{ {
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter); struct hal_data_8188e *hal_data = GET_HAL_DATA(adapt);
u8 regBwOpMode; u8 reg_bw_opmode;
u8 regRRSR_RSC; u8 reg_prsr_rsc;
if (pHalData->rf_chip == RF_PSEUDO_11N) if (hal_data->rf_chip == RF_PSEUDO_11N)
return; return;
/* There is no 40MHz mode in RF_8225. */ /* There is no 40MHz mode in RF_8225. */
if (pHalData->rf_chip == RF_8225) if (hal_data->rf_chip == RF_8225)
return; return;
if (Adapter->bDriverStopped) if (adapt->bDriverStopped)
return; return;
/* 3 */ /* Set MAC register */
/* 3<1>Set MAC register */
/* 3 */
regBwOpMode = usb_read8(Adapter, REG_BWOPMODE); reg_bw_opmode = usb_read8(adapt, REG_BWOPMODE);
regRRSR_RSC = usb_read8(Adapter, REG_RRSR+2); reg_prsr_rsc = usb_read8(adapt, REG_RRSR+2);
switch (pHalData->CurrentChannelBW) { switch (hal_data->CurrentChannelBW) {
case HT_CHANNEL_WIDTH_20: case HT_CHANNEL_WIDTH_20:
regBwOpMode |= BW_OPMODE_20MHZ; reg_bw_opmode |= BW_OPMODE_20MHZ;
/* 2007/02/07 Mark by Emily because we have not verify whether this register works */ usb_write8(adapt, REG_BWOPMODE, reg_bw_opmode);
usb_write8(Adapter, REG_BWOPMODE, regBwOpMode);
break; break;
case HT_CHANNEL_WIDTH_40: case HT_CHANNEL_WIDTH_40:
regBwOpMode &= ~BW_OPMODE_20MHZ; reg_bw_opmode &= ~BW_OPMODE_20MHZ;
/* 2007/02/07 Mark by Emily because we have not verify whether this register works */ usb_write8(adapt, REG_BWOPMODE, reg_bw_opmode);
usb_write8(Adapter, REG_BWOPMODE, regBwOpMode); reg_prsr_rsc = (reg_prsr_rsc&0x90) |
regRRSR_RSC = (regRRSR_RSC&0x90) | (pHalData->nCur40MhzPrimeSC<<5); (hal_data->nCur40MhzPrimeSC<<5);
usb_write8(Adapter, REG_RRSR+2, regRRSR_RSC); usb_write8(adapt, REG_RRSR+2, reg_prsr_rsc);
break; break;
default: default:
break; break;
} }
/* 3 */ /* Set PHY related register */
/* 3 <2>Set PHY related register */ switch (hal_data->CurrentChannelBW) {
/* 3 */
switch (pHalData->CurrentChannelBW) {
/* 20 MHz channel*/
case HT_CHANNEL_WIDTH_20: case HT_CHANNEL_WIDTH_20:
phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x0);
phy_set_bb_reg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0); phy_set_bb_reg(adapt, rFPGA1_RFMOD, bRFMOD, 0x0);
break; break;
/* 40 MHz channel*/
case HT_CHANNEL_WIDTH_40: case HT_CHANNEL_WIDTH_40:
phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x1);
phy_set_bb_reg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1); phy_set_bb_reg(adapt, rFPGA1_RFMOD, bRFMOD, 0x1);
/* Set Control channel to upper or lower. These settings are required only for 40MHz */ /* Set Control channel to upper or lower.
phy_set_bb_reg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1)); * These settings are required only for 40MHz
phy_set_bb_reg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); */
phy_set_bb_reg(Adapter, 0x818, (BIT26 | BIT27), phy_set_bb_reg(adapt, rCCK0_System, bCCKSideBand,
(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); (hal_data->nCur40MhzPrimeSC>>1));
phy_set_bb_reg(adapt, rOFDM1_LSTF, 0xC00,
hal_data->nCur40MhzPrimeSC);
phy_set_bb_reg(adapt, 0x818, (BIT26 | BIT27),
(hal_data->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
break; break;
default: default:
break; break;
} }
/* Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 */
/* 3<3>Set RF related register */ /* Set RF related register */
switch (pHalData->rf_chip) { switch (hal_data->rf_chip) {
case RF_8225: case RF_8225:
break; break;
case RF_8256: case RF_8256:
/* Please implement this function in Hal8190PciPhy8256.c */
break; break;
case RF_8258: case RF_8258:
/* Please implement this function in Hal8190PciPhy8258.c */
break; break;
case RF_PSEUDO_11N: case RF_PSEUDO_11N:
break; break;
case RF_6052: case RF_6052:
rtl8188e_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW); rtl8188e_PHY_RF6052SetBandwidth(adapt, hal_data->CurrentChannelBW);
break; break;
default: default:
break; break;
@ -386,7 +362,7 @@ void PHY_SetBWMode8188E(struct adapter *Adapter, enum ht_channel_width Bandwidth
pHalData->nCur40MhzPrimeSC = Offset; pHalData->nCur40MhzPrimeSC = Offset;
if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
_PHY_SetBWMode92C(Adapter); phy_set_bw_mode_callback(Adapter);
else else
pHalData->CurrentChannelBW = tmpBW; pHalData->CurrentChannelBW = tmpBW;
} }