ARM: ixp4xx: Switch to use new IRQ+GPIO drivers
This deletes the old irq+gpiochip combo from the IXP4xx machine and switches it over to use the new drivers merged in respective subsystem. Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>hifive-unleashed-5.2
Linus Walleij
parent
813e7d36f2
commit
55ec465e73
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@ -434,10 +434,11 @@ config ARCH_IXP4XX
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select DMABOUNCE if PCI
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select GENERIC_CLOCKEVENTS
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select GENERIC_IRQ_MULTI_HANDLER
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select GPIO_IXP4XX
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select GPIOLIB
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select HAVE_PCI
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select IXP4XX_IRQ
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select NEED_MACH_IO_H
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select SPARSE_IRQ
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select USB_EHCI_BIG_ENDIAN_DESC
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select USB_EHCI_BIG_ENDIAN_MMIO
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help
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@ -27,11 +27,11 @@
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <linux/export.h>
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#include <linux/gpio/driver.h>
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#include <linux/cpu.h>
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#include <linux/pci.h>
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#include <linux/sched_clock.h>
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#include <linux/bitops.h>
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#include <linux/irqchip/irq-ixp4xx.h>
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#include <mach/udc.h>
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#include <mach/hardware.h>
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#include <mach/io.h>
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@ -58,7 +58,6 @@
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(IXP4XX_OST_RELOAD_MASK + 1) * HZ) * \
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(IXP4XX_OST_RELOAD_MASK + 1)
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static struct irq_domain *ixp4xx_irqdomain;
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static void __init ixp4xx_clocksource_init(void);
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static void __init ixp4xx_clockevent_init(void);
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static struct clock_event_device clockevent_ixp4xx;
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@ -95,266 +94,18 @@ void __init ixp4xx_map_io(void)
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iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
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}
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/*
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* GPIO-functions
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*/
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/*
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* The following converted to the real HW bits the gpio_line_config
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*/
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/* GPIO pin types */
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#define IXP4XX_GPIO_OUT 0x1
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#define IXP4XX_GPIO_IN 0x2
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/* GPIO signal types */
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#define IXP4XX_GPIO_LOW 0
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#define IXP4XX_GPIO_HIGH 1
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/* GPIO Clocks */
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#define IXP4XX_GPIO_CLK_0 14
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#define IXP4XX_GPIO_CLK_1 15
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static void gpio_line_config(u8 line, u32 direction)
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{
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if (direction == IXP4XX_GPIO_IN)
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*IXP4XX_GPIO_GPOER |= (1 << line);
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else
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*IXP4XX_GPIO_GPOER &= ~(1 << line);
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}
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static void gpio_line_get(u8 line, int *value)
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{
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*value = (*IXP4XX_GPIO_GPINR >> line) & 0x1;
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}
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static void gpio_line_set(u8 line, int value)
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{
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if (value == IXP4XX_GPIO_HIGH)
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*IXP4XX_GPIO_GPOUTR |= (1 << line);
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else if (value == IXP4XX_GPIO_LOW)
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*IXP4XX_GPIO_GPOUTR &= ~(1 << line);
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}
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/*************************************************************************
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* IXP4xx chipset IRQ handling
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*
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* TODO: GPIO IRQs should be marked invalid until the user of the IRQ
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* (be it PCI or something else) configures that GPIO line
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* as an IRQ.
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**************************************************************************/
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enum ixp4xx_irq_type {
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IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
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};
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/* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
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static unsigned long long ixp4xx_irq_edge = 0;
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/*
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* IRQ -> GPIO mapping table
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*/
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static signed char irq2gpio[32] = {
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-1, -1, -1, -1, -1, -1, 0, 1,
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-1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, 2, 3, 4, 5, 6,
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7, 8, 9, 10, 11, 12, -1, -1,
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};
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static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
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{
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int irq;
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for (irq = 0; irq < 32; irq++) {
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if (irq2gpio[irq] == gpio)
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return irq;
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}
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return -EINVAL;
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}
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static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
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{
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int line = irq2gpio[d->hwirq];
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u32 int_style;
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enum ixp4xx_irq_type irq_type;
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volatile u32 *int_reg;
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/*
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* Only for GPIO IRQs
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* all other IRQs are simply active low
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*/
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if (line < 0)
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return 0;
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switch (type){
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case IRQ_TYPE_EDGE_BOTH:
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int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
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irq_type = IXP4XX_IRQ_EDGE;
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break;
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case IRQ_TYPE_EDGE_RISING:
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int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
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irq_type = IXP4XX_IRQ_EDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
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irq_type = IXP4XX_IRQ_EDGE;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
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irq_type = IXP4XX_IRQ_LEVEL;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
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irq_type = IXP4XX_IRQ_LEVEL;
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break;
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default:
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return -EINVAL;
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}
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if (irq_type == IXP4XX_IRQ_EDGE)
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ixp4xx_irq_edge |= (1 << d->hwirq);
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else
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ixp4xx_irq_edge &= ~(1 << d->hwirq);
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if (line >= 8) { /* pins 8-15 */
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line -= 8;
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int_reg = IXP4XX_GPIO_GPIT2R;
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} else { /* pins 0-7 */
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int_reg = IXP4XX_GPIO_GPIT1R;
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}
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/* Clear the style for the appropriate pin */
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*int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
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(line * IXP4XX_GPIO_STYLE_SIZE));
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*IXP4XX_GPIO_GPISR = (1 << line);
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/* Set the new style */
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*int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
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/* Configure the line as an input */
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gpio_line_config(irq2gpio[d->hwirq], IXP4XX_GPIO_IN);
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return 0;
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}
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static void ixp4xx_irq_mask(struct irq_data *d)
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{
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if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->hwirq >= 32)
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*IXP4XX_ICMR2 &= ~(1 << (d->hwirq - 32));
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else
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*IXP4XX_ICMR &= ~(1 << d->hwirq);
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}
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static void ixp4xx_irq_ack(struct irq_data *d)
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{
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int line = (d->hwirq < 32) ? irq2gpio[d->hwirq] : -1;
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if (line >= 0)
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*IXP4XX_GPIO_GPISR = (1 << line);
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}
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/*
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* Level triggered interrupts on GPIO lines can only be cleared when the
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* interrupt condition disappears.
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*/
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static void ixp4xx_irq_unmask(struct irq_data *d)
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{
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if (!(ixp4xx_irq_edge & (1 << d->hwirq)))
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ixp4xx_irq_ack(d);
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if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->hwirq >= 32)
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*IXP4XX_ICMR2 |= (1 << (d->hwirq - 32));
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else
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*IXP4XX_ICMR |= (1 << d->hwirq);
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}
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static struct irq_chip ixp4xx_irq_chip = {
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.name = "IXP4xx",
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.irq_ack = ixp4xx_irq_ack,
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.irq_mask = ixp4xx_irq_mask,
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.irq_unmask = ixp4xx_irq_unmask,
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.irq_set_type = ixp4xx_set_irq_type,
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};
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asmlinkage void __exception_irq_entry ixp4xx_handle_irq(struct pt_regs *regs)
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{
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unsigned long status;
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int i;
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status = *IXP4XX_ICIP;
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for_each_set_bit(i, &status, 32)
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handle_domain_irq(ixp4xx_irqdomain, i, regs);
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/*
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* IXP465/IXP435 has an upper IRQ status register
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*/
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if ((cpu_is_ixp46x() || cpu_is_ixp43x())) {
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status = *IXP4XX_ICIP2;
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for_each_set_bit(i, &status, 32)
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handle_domain_irq(ixp4xx_irqdomain, i + 32, regs);
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}
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}
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static int ixp4xx_irqdomain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_data(irq, &ixp4xx_irq_chip);
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irq_set_chip_and_handler(irq, &ixp4xx_irq_chip, handle_level_irq);
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irq_set_probe(irq);
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return 0;
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}
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static void ixp4xx_irqdomain_unmap(struct irq_domain *d, unsigned int irq)
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{
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irq_set_chip_and_handler(irq, NULL, NULL);
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irq_set_chip_data(irq, NULL);
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}
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static const struct irq_domain_ops ixp4xx_irqdomain_ops = {
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.map = ixp4xx_irqdomain_map,
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.unmap = ixp4xx_irqdomain_unmap,
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};
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void __init ixp4xx_init_irq(void)
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{
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int nr_irqs;
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/*
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* ixp4xx does not implement the XScale PWRMODE register
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* so it must not call cpu_do_idle().
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*/
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cpu_idle_poll_ctrl(true);
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/* Route all sources to IRQ instead of FIQ */
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*IXP4XX_ICLR = 0x0;
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/* Disable all interrupt */
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*IXP4XX_ICMR = 0x0;
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if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
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/* Route upper 32 sources to IRQ instead of FIQ */
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*IXP4XX_ICLR2 = 0x00;
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/* Disable upper 32 interrupts */
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*IXP4XX_ICMR2 = 0x00;
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nr_irqs = 64;
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} else {
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nr_irqs = 32;
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}
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ixp4xx_irqdomain = irq_domain_add_simple(NULL, nr_irqs, IRQ_IXP4XX_BASE,
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&ixp4xx_irqdomain_ops,
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NULL);
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if (!ixp4xx_irqdomain) {
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pr_crit("can not add primary irqdomain\n");
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return;
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}
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set_handle_irq(ixp4xx_handle_irq);
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ixp4xx_irq_init(IXP4XX_INTC_BASE_PHYS,
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(cpu_is_ixp46x() || cpu_is_ixp43x()));
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}
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/*************************************************************************
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* IXP4xx timer tick
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* We use OS timer1 on the CPU for the timer tick and the timestamp
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@ -408,6 +159,24 @@ static struct resource ixp4xx_udc_resources[] = {
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},
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};
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static struct resource ixp4xx_gpio_resource[] = {
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{
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.start = IXP4XX_GPIO_BASE_PHYS,
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.end = IXP4XX_GPIO_BASE_PHYS + 0xfff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device ixp4xx_gpio_device = {
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.name = "ixp4xx-gpio",
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.id = -1,
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.dev = {
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.resource = ixp4xx_gpio_resource,
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.num_resources = ARRAY_SIZE(ixp4xx_gpio_resource),
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};
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/*
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* USB device controller. The IXP4xx uses the same controller as PXA25X,
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* so we just use the same device.
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@ -423,6 +192,7 @@ static struct platform_device ixp4xx_udc_device = {
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};
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static struct platform_device *ixp4xx_devices[] __initdata = {
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&ixp4xx_gpio_device,
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&ixp4xx_udc_device,
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};
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@ -457,56 +227,12 @@ static struct platform_device *ixp46x_devices[] __initdata = {
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unsigned long ixp4xx_exp_bus_size;
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EXPORT_SYMBOL(ixp4xx_exp_bus_size);
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static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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{
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gpio_line_config(gpio, IXP4XX_GPIO_IN);
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return 0;
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}
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static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
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int level)
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{
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gpio_line_set(gpio, level);
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gpio_line_config(gpio, IXP4XX_GPIO_OUT);
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return 0;
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}
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static int ixp4xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
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{
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int value;
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gpio_line_get(gpio, &value);
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return value;
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}
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static void ixp4xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
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int value)
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{
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gpio_line_set(gpio, value);
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}
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static struct gpio_chip ixp4xx_gpio_chip = {
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.label = "IXP4XX_GPIO_CHIP",
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.direction_input = ixp4xx_gpio_direction_input,
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.direction_output = ixp4xx_gpio_direction_output,
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.get = ixp4xx_gpio_get_value,
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.set = ixp4xx_gpio_set_value,
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.to_irq = ixp4xx_gpio_to_irq,
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.base = 0,
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.ngpio = 16,
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};
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void __init ixp4xx_sys_init(void)
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{
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ixp4xx_exp_bus_size = SZ_16M;
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platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
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gpiochip_add_data(&ixp4xx_gpio_chip, NULL);
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if (cpu_is_ixp46x()) {
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int region;
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@ -270,9 +270,6 @@ static void __init dsmg600_init(void)
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{
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ixp4xx_sys_init();
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/* Make sure that GPIO14 and GPIO15 are not used as clocks */
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*IXP4XX_GPIO_GPCLKR = 0;
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dsmg600_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
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dsmg600_flash_resource.end =
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IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
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@ -147,95 +147,6 @@
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#define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
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#define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
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/*
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* Constants to make it easy to access Interrupt Controller registers
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*/
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#define IXP4XX_ICPR_OFFSET 0x00 /* Interrupt Status */
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#define IXP4XX_ICMR_OFFSET 0x04 /* Interrupt Enable */
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#define IXP4XX_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */
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#define IXP4XX_ICIP_OFFSET 0x0C /* IRQ Status */
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#define IXP4XX_ICFP_OFFSET 0x10 /* FIQ Status */
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#define IXP4XX_ICHR_OFFSET 0x14 /* Interrupt Priority */
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#define IXP4XX_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */
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#define IXP4XX_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */
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/*
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* IXP465-only
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*/
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#define IXP4XX_ICPR2_OFFSET 0x20 /* Interrupt Status 2 */
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#define IXP4XX_ICMR2_OFFSET 0x24 /* Interrupt Enable 2 */
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#define IXP4XX_ICLR2_OFFSET 0x28 /* Interrupt IRQ/FIQ Select 2 */
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#define IXP4XX_ICIP2_OFFSET 0x2C /* IRQ Status */
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#define IXP4XX_ICFP2_OFFSET 0x30 /* FIQ Status */
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#define IXP4XX_ICEEN_OFFSET 0x34 /* Error High Pri Enable */
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/*
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* Interrupt Controller Register Definitions.
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*/
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#define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x)))
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#define IXP4XX_ICPR IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET)
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#define IXP4XX_ICMR IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET)
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#define IXP4XX_ICLR IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET)
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#define IXP4XX_ICIP IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET)
|
||||
#define IXP4XX_ICFP IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET)
|
||||
#define IXP4XX_ICHR IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)
|
||||
#define IXP4XX_ICIH IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET)
|
||||
#define IXP4XX_ICFH IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)
|
||||
#define IXP4XX_ICPR2 IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET)
|
||||
#define IXP4XX_ICMR2 IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET)
|
||||
#define IXP4XX_ICLR2 IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET)
|
||||
#define IXP4XX_ICIP2 IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET)
|
||||
#define IXP4XX_ICFP2 IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET)
|
||||
#define IXP4XX_ICEEN IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET)
|
||||
|
||||
/*
|
||||
* Constants to make it easy to access GPIO registers
|
||||
*/
|
||||
#define IXP4XX_GPIO_GPOUTR_OFFSET 0x00
|
||||
#define IXP4XX_GPIO_GPOER_OFFSET 0x04
|
||||
#define IXP4XX_GPIO_GPINR_OFFSET 0x08
|
||||
#define IXP4XX_GPIO_GPISR_OFFSET 0x0C
|
||||
#define IXP4XX_GPIO_GPIT1R_OFFSET 0x10
|
||||
#define IXP4XX_GPIO_GPIT2R_OFFSET 0x14
|
||||
#define IXP4XX_GPIO_GPCLKR_OFFSET 0x18
|
||||
#define IXP4XX_GPIO_GPDBSELR_OFFSET 0x1C
|
||||
|
||||
/*
|
||||
* GPIO Register Definitions.
|
||||
* [Only perform 32bit reads/writes]
|
||||
*/
|
||||
#define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x)))
|
||||
|
||||
#define IXP4XX_GPIO_GPOUTR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET)
|
||||
#define IXP4XX_GPIO_GPOER IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET)
|
||||
#define IXP4XX_GPIO_GPINR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET)
|
||||
#define IXP4XX_GPIO_GPISR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET)
|
||||
#define IXP4XX_GPIO_GPIT1R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET)
|
||||
#define IXP4XX_GPIO_GPIT2R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET)
|
||||
#define IXP4XX_GPIO_GPCLKR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET)
|
||||
#define IXP4XX_GPIO_GPDBSELR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET)
|
||||
|
||||
/*
|
||||
* GPIO register bit definitions
|
||||
*/
|
||||
|
||||
/* Interrupt styles
|
||||
*/
|
||||
#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0
|
||||
#define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1
|
||||
#define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2
|
||||
#define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3
|
||||
#define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4
|
||||
|
||||
/*
|
||||
* Mask used to clear interrupt styles
|
||||
*/
|
||||
#define IXP4XX_GPIO_STYLE_CLEAR 0x7
|
||||
#define IXP4XX_GPIO_STYLE_SIZE 3
|
||||
|
||||
/*
|
||||
* Constants to make it easy to access Timer Control/Status registers
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -281,9 +281,6 @@ static void __init nas100d_init(void)
|
|||
|
||||
ixp4xx_sys_init();
|
||||
|
||||
/* gpio 14 and 15 are _not_ clocks */
|
||||
*IXP4XX_GPIO_GPCLKR = 0;
|
||||
|
||||
nas100d_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
|
||||
nas100d_flash_resource.end =
|
||||
IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue