Merge branches 'amba', 'devel-stable', 'kexec-for-next' and 'misc' into for-linus
This commit is contained in:
commit
5632a9fbcd
1
.mailmap
1
.mailmap
|
@ -33,6 +33,7 @@ Björn Steinbrink <B.Steinbrink@gmx.de>
|
|||
Brian Avery <b.avery@hp.com>
|
||||
Brian King <brking@us.ibm.com>
|
||||
Christoph Hellwig <hch@lst.de>
|
||||
Christophe Ricard <christophe.ricard@gmail.com>
|
||||
Corey Minyard <minyard@acm.org>
|
||||
Damian Hobson-Garcia <dhobsong@igel.co.jp>
|
||||
David Brownell <david-b@pacbell.net>
|
||||
|
|
|
@ -1,23 +1,18 @@
|
|||
What: /sys/devices/platform/<i2c-demux-name>/cur_master
|
||||
What: /sys/devices/platform/<i2c-demux-name>/available_masters
|
||||
Date: January 2016
|
||||
KernelVersion: 4.6
|
||||
Contact: Wolfram Sang <wsa@the-dreams.de>
|
||||
Description:
|
||||
Reading the file will give you a list of masters which can be
|
||||
selected for a demultiplexed bus. The format is
|
||||
"<index>:<name>". Example from a Renesas Lager board:
|
||||
|
||||
This file selects the active I2C master for a demultiplexed bus.
|
||||
0:/i2c@e6500000 1:/i2c@e6508000
|
||||
|
||||
Write 0 there for the first master, 1 for the second etc. Reading the file will
|
||||
give you a list with the active master marked. Example from a Renesas Lager
|
||||
board:
|
||||
|
||||
root@Lager:~# cat /sys/devices/platform/i2c@8/cur_master
|
||||
* 0 - /i2c@9
|
||||
1 - /i2c@e6520000
|
||||
2 - /i2c@e6530000
|
||||
|
||||
root@Lager:~# echo 2 > /sys/devices/platform/i2c@8/cur_master
|
||||
|
||||
root@Lager:~# cat /sys/devices/platform/i2c@8/cur_master
|
||||
0 - /i2c@9
|
||||
1 - /i2c@e6520000
|
||||
* 2 - /i2c@e6530000
|
||||
What: /sys/devices/platform/<i2c-demux-name>/current_master
|
||||
Date: January 2016
|
||||
KernelVersion: 4.6
|
||||
Contact: Wolfram Sang <wsa@the-dreams.de>
|
||||
Description:
|
||||
This file selects/shows the active I2C master for a demultiplexed
|
||||
bus. It uses the <index> value from the file 'available_masters'.
|
||||
|
|
|
@ -84,6 +84,12 @@ Optional properties:
|
|||
- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (retain settings set by
|
||||
firmware)
|
||||
- arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly
|
||||
disable), <1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferrably retain firmware settings)
|
||||
- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferrably retain firmware settings)
|
||||
|
||||
Example:
|
||||
|
||||
|
|
|
@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
|
|||
The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
|
||||
|
||||
Required Properties:
|
||||
- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following
|
||||
- compatible: has to be "qca,<soctype>-pll" and one of the following
|
||||
fallbacks:
|
||||
- "qca,ar7100-pll"
|
||||
- "qca,ar7240-pll"
|
||||
|
@ -21,8 +21,8 @@ Optional properties:
|
|||
|
||||
Example:
|
||||
|
||||
memory-controller@18050000 {
|
||||
compatible = "qca,ar9132-ppl", "qca,ar9130-pll";
|
||||
pll-controller@18050000 {
|
||||
compatible = "qca,ar9132-pll", "qca,ar9130-pll";
|
||||
reg = <0x18050000 0x20>;
|
||||
|
||||
clock-names = "ref";
|
||||
|
|
|
@ -134,12 +134,12 @@ mfio80 ddr_debug, mips_trace_data, mips_debug
|
|||
mfio81 dreq0, mips_trace_data, eth_debug
|
||||
mfio82 dreq1, mips_trace_data, eth_debug
|
||||
mfio83 mips_pll_lock, mips_trace_data, usb_debug
|
||||
mfio84 sys_pll_lock, mips_trace_data, usb_debug
|
||||
mfio85 wifi_pll_lock, mips_trace_data, sdhost_debug
|
||||
mfio86 bt_pll_lock, mips_trace_data, sdhost_debug
|
||||
mfio87 rpu_v_pll_lock, dreq2, socif_debug
|
||||
mfio88 rpu_l_pll_lock, dreq3, socif_debug
|
||||
mfio89 audio_pll_lock, dreq4, dreq5
|
||||
mfio84 audio_pll_lock, mips_trace_data, usb_debug
|
||||
mfio85 rpu_v_pll_lock, mips_trace_data, sdhost_debug
|
||||
mfio86 rpu_l_pll_lock, mips_trace_data, sdhost_debug
|
||||
mfio87 sys_pll_lock, dreq2, socif_debug
|
||||
mfio88 wifi_pll_lock, dreq3, socif_debug
|
||||
mfio89 bt_pll_lock, dreq4, dreq5
|
||||
tck
|
||||
trstn
|
||||
tdi
|
||||
|
|
|
@ -38,7 +38,7 @@ the update lasts only as long as the inode is cached in memory, after
|
|||
which the timestamp reverts to 1970, i.e. moves backwards in time.
|
||||
|
||||
Currently, cramfs must be written and read with architectures of the
|
||||
same endianness, and can be read only by kernels with PAGE_CACHE_SIZE
|
||||
same endianness, and can be read only by kernels with PAGE_SIZE
|
||||
== 4096. At least the latter of these is a bug, but it hasn't been
|
||||
decided what the best fix is. For the moment if you have larger pages
|
||||
you can just change the #define in mkcramfs.c, so long as you don't
|
||||
|
|
|
@ -60,7 +60,7 @@ size: The limit of allocated bytes for this tmpfs instance. The
|
|||
default is half of your physical RAM without swap. If you
|
||||
oversize your tmpfs instances the machine will deadlock
|
||||
since the OOM handler will not be able to free that memory.
|
||||
nr_blocks: The same as size, but in blocks of PAGE_CACHE_SIZE.
|
||||
nr_blocks: The same as size, but in blocks of PAGE_SIZE.
|
||||
nr_inodes: The maximum number of inodes for this instance. The default
|
||||
is half of the number of your physical RAM pages, or (on a
|
||||
machine with highmem) the number of lowmem RAM pages,
|
||||
|
|
|
@ -708,9 +708,9 @@ struct address_space_operations {
|
|||
from the address space. This generally corresponds to either a
|
||||
truncation, punch hole or a complete invalidation of the address
|
||||
space (in the latter case 'offset' will always be 0 and 'length'
|
||||
will be PAGE_CACHE_SIZE). Any private data associated with the page
|
||||
will be PAGE_SIZE). Any private data associated with the page
|
||||
should be updated to reflect this truncation. If offset is 0 and
|
||||
length is PAGE_CACHE_SIZE, then the private data should be released,
|
||||
length is PAGE_SIZE, then the private data should be released,
|
||||
because the page must be able to be completely discarded. This may
|
||||
be done by calling the ->releasepage function, but in this case the
|
||||
release MUST succeed.
|
||||
|
|
|
@ -263,12 +263,6 @@ The syntax is:
|
|||
crashkernel=<range1>:<size1>[,<range2>:<size2>,...][@offset]
|
||||
range=start-[end]
|
||||
|
||||
Please note, on arm, the offset is required.
|
||||
crashkernel=<range1>:<size1>[,<range2>:<size2>,...]@offset
|
||||
range=start-[end]
|
||||
|
||||
'start' is inclusive and 'end' is exclusive.
|
||||
|
||||
For example:
|
||||
|
||||
crashkernel=512M-2G:64M,2G-:128M
|
||||
|
@ -307,10 +301,9 @@ Boot into System Kernel
|
|||
on the memory consumption of the kdump system. In general this is not
|
||||
dependent on the memory size of the production system.
|
||||
|
||||
On arm, use "crashkernel=Y@X". Note that the start address of the kernel
|
||||
will be aligned to 128MiB (0x08000000), so if the start address is not then
|
||||
any space below the alignment point may be overwritten by the dump-capture kernel,
|
||||
which means it is possible that the vmcore is not that precise as expected.
|
||||
On arm, the use of "crashkernel=Y@X" is no longer necessary; the
|
||||
kernel will automatically locate the crash kernel image within the
|
||||
first 512MB of RAM if X is not given.
|
||||
|
||||
|
||||
Load the Dump-capture Kernel
|
||||
|
|
|
@ -2921,11 +2921,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
|
|||
for broken drivers that don't call it.
|
||||
skip_isa_align [X86] do not align io start addr, so can
|
||||
handle more pci cards
|
||||
firmware [ARM] Do not re-enumerate the bus but instead
|
||||
just use the configuration from the
|
||||
bootloader. This is currently used on
|
||||
IXP2000 systems where the bus has to be
|
||||
configured a certain way for adjunct CPUs.
|
||||
noearly [X86] Don't do any early type 1 scanning.
|
||||
This might help on some broken boards which
|
||||
machine check when some devices' config space
|
||||
|
|
|
@ -386,7 +386,7 @@ used. First phase is to "prepare" anything needed, including various checks,
|
|||
memory allocation, etc. The goal is to handle the stuff that is not unlikely
|
||||
to fail here. The second phase is to "commit" the actual changes.
|
||||
|
||||
Switchdev provides an inftrastructure for sharing items (for example memory
|
||||
Switchdev provides an infrastructure for sharing items (for example memory
|
||||
allocations) between the two phases.
|
||||
|
||||
The object created by a driver in "prepare" phase and it is queued up by:
|
||||
|
|
|
@ -586,6 +586,10 @@ drivers to make their ->remove() callbacks avoid races with runtime PM directly,
|
|||
but also it allows of more flexibility in the handling of devices during the
|
||||
removal of their drivers.
|
||||
|
||||
Drivers in ->remove() callback should undo the runtime PM changes done
|
||||
in ->probe(). Usually this means calling pm_runtime_disable(),
|
||||
pm_runtime_dont_use_autosuspend() etc.
|
||||
|
||||
The user space can effectively disallow the driver of the device to power manage
|
||||
it at run time by changing the value of its /sys/devices/.../power/control
|
||||
attribute to "on", which causes pm_runtime_forbid() to be called. In principle,
|
||||
|
|
208
Documentation/x86/topology.txt
Normal file
208
Documentation/x86/topology.txt
Normal file
|
@ -0,0 +1,208 @@
|
|||
x86 Topology
|
||||
============
|
||||
|
||||
This documents and clarifies the main aspects of x86 topology modelling and
|
||||
representation in the kernel. Update/change when doing changes to the
|
||||
respective code.
|
||||
|
||||
The architecture-agnostic topology definitions are in
|
||||
Documentation/cputopology.txt. This file holds x86-specific
|
||||
differences/specialities which must not necessarily apply to the generic
|
||||
definitions. Thus, the way to read up on Linux topology on x86 is to start
|
||||
with the generic one and look at this one in parallel for the x86 specifics.
|
||||
|
||||
Needless to say, code should use the generic functions - this file is *only*
|
||||
here to *document* the inner workings of x86 topology.
|
||||
|
||||
Started by Thomas Gleixner <tglx@linutronix.de> and Borislav Petkov <bp@alien8.de>.
|
||||
|
||||
The main aim of the topology facilities is to present adequate interfaces to
|
||||
code which needs to know/query/use the structure of the running system wrt
|
||||
threads, cores, packages, etc.
|
||||
|
||||
The kernel does not care about the concept of physical sockets because a
|
||||
socket has no relevance to software. It's an electromechanical component. In
|
||||
the past a socket always contained a single package (see below), but with the
|
||||
advent of Multi Chip Modules (MCM) a socket can hold more than one package. So
|
||||
there might be still references to sockets in the code, but they are of
|
||||
historical nature and should be cleaned up.
|
||||
|
||||
The topology of a system is described in the units of:
|
||||
|
||||
- packages
|
||||
- cores
|
||||
- threads
|
||||
|
||||
* Package:
|
||||
|
||||
Packages contain a number of cores plus shared resources, e.g. DRAM
|
||||
controller, shared caches etc.
|
||||
|
||||
AMD nomenclature for package is 'Node'.
|
||||
|
||||
Package-related topology information in the kernel:
|
||||
|
||||
- cpuinfo_x86.x86_max_cores:
|
||||
|
||||
The number of cores in a package. This information is retrieved via CPUID.
|
||||
|
||||
- cpuinfo_x86.phys_proc_id:
|
||||
|
||||
The physical ID of the package. This information is retrieved via CPUID
|
||||
and deduced from the APIC IDs of the cores in the package.
|
||||
|
||||
- cpuinfo_x86.logical_id:
|
||||
|
||||
The logical ID of the package. As we do not trust BIOSes to enumerate the
|
||||
packages in a consistent way, we introduced the concept of logical package
|
||||
ID so we can sanely calculate the number of maximum possible packages in
|
||||
the system and have the packages enumerated linearly.
|
||||
|
||||
- topology_max_packages():
|
||||
|
||||
The maximum possible number of packages in the system. Helpful for per
|
||||
package facilities to preallocate per package information.
|
||||
|
||||
|
||||
* Cores:
|
||||
|
||||
A core consists of 1 or more threads. It does not matter whether the threads
|
||||
are SMT- or CMT-type threads.
|
||||
|
||||
AMDs nomenclature for a CMT core is "Compute Unit". The kernel always uses
|
||||
"core".
|
||||
|
||||
Core-related topology information in the kernel:
|
||||
|
||||
- smp_num_siblings:
|
||||
|
||||
The number of threads in a core. The number of threads in a package can be
|
||||
calculated by:
|
||||
|
||||
threads_per_package = cpuinfo_x86.x86_max_cores * smp_num_siblings
|
||||
|
||||
|
||||
* Threads:
|
||||
|
||||
A thread is a single scheduling unit. It's the equivalent to a logical Linux
|
||||
CPU.
|
||||
|
||||
AMDs nomenclature for CMT threads is "Compute Unit Core". The kernel always
|
||||
uses "thread".
|
||||
|
||||
Thread-related topology information in the kernel:
|
||||
|
||||
- topology_core_cpumask():
|
||||
|
||||
The cpumask contains all online threads in the package to which a thread
|
||||
belongs.
|
||||
|
||||
The number of online threads is also printed in /proc/cpuinfo "siblings."
|
||||
|
||||
- topology_sibling_mask():
|
||||
|
||||
The cpumask contains all online threads in the core to which a thread
|
||||
belongs.
|
||||
|
||||
- topology_logical_package_id():
|
||||
|
||||
The logical package ID to which a thread belongs.
|
||||
|
||||
- topology_physical_package_id():
|
||||
|
||||
The physical package ID to which a thread belongs.
|
||||
|
||||
- topology_core_id();
|
||||
|
||||
The ID of the core to which a thread belongs. It is also printed in /proc/cpuinfo
|
||||
"core_id."
|
||||
|
||||
|
||||
|
||||
System topology examples
|
||||
|
||||
Note:
|
||||
|
||||
The alternative Linux CPU enumeration depends on how the BIOS enumerates the
|
||||
threads. Many BIOSes enumerate all threads 0 first and then all threads 1.
|
||||
That has the "advantage" that the logical Linux CPU numbers of threads 0 stay
|
||||
the same whether threads are enabled or not. That's merely an implementation
|
||||
detail and has no practical impact.
|
||||
|
||||
1) Single Package, Single Core
|
||||
|
||||
[package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
|
||||
|
||||
2) Single Package, Dual Core
|
||||
|
||||
a) One thread per core
|
||||
|
||||
[package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
|
||||
-> [core 1] -> [thread 0] -> Linux CPU 1
|
||||
|
||||
b) Two threads per core
|
||||
|
||||
[package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
|
||||
-> [thread 1] -> Linux CPU 1
|
||||
-> [core 1] -> [thread 0] -> Linux CPU 2
|
||||
-> [thread 1] -> Linux CPU 3
|
||||
|
||||
Alternative enumeration:
|
||||
|
||||
[package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
|
||||
-> [thread 1] -> Linux CPU 2
|
||||
-> [core 1] -> [thread 0] -> Linux CPU 1
|
||||
-> [thread 1] -> Linux CPU 3
|
||||
|
||||
AMD nomenclature for CMT systems:
|
||||
|
||||
[node 0] -> [Compute Unit 0] -> [Compute Unit Core 0] -> Linux CPU 0
|
||||
-> [Compute Unit Core 1] -> Linux CPU 1
|
||||
-> [Compute Unit 1] -> [Compute Unit Core 0] -> Linux CPU 2
|
||||
-> [Compute Unit Core 1] -> Linux CPU 3
|
||||
|
||||
4) Dual Package, Dual Core
|
||||
|
||||
a) One thread per core
|
||||
|
||||
[package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
|
||||
-> [core 1] -> [thread 0] -> Linux CPU 1
|
||||
|
||||
[package 1] -> [core 0] -> [thread 0] -> Linux CPU 2
|
||||
-> [core 1] -> [thread 0] -> Linux CPU 3
|
||||
|
||||
b) Two threads per core
|
||||
|
||||
[package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
|
||||
-> [thread 1] -> Linux CPU 1
|
||||
-> [core 1] -> [thread 0] -> Linux CPU 2
|
||||
-> [thread 1] -> Linux CPU 3
|
||||
|
||||
[package 1] -> [core 0] -> [thread 0] -> Linux CPU 4
|
||||
-> [thread 1] -> Linux CPU 5
|
||||
-> [core 1] -> [thread 0] -> Linux CPU 6
|
||||
-> [thread 1] -> Linux CPU 7
|
||||
|
||||
Alternative enumeration:
|
||||
|
||||
[package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
|
||||
-> [thread 1] -> Linux CPU 4
|
||||
-> [core 1] -> [thread 0] -> Linux CPU 1
|
||||
-> [thread 1] -> Linux CPU 5
|
||||
|
||||
[package 1] -> [core 0] -> [thread 0] -> Linux CPU 2
|
||||
-> [thread 1] -> Linux CPU 6
|
||||
-> [core 1] -> [thread 0] -> Linux CPU 3
|
||||
-> [thread 1] -> Linux CPU 7
|
||||
|
||||
AMD nomenclature for CMT systems:
|
||||
|
||||
[node 0] -> [Compute Unit 0] -> [Compute Unit Core 0] -> Linux CPU 0
|
||||
-> [Compute Unit Core 1] -> Linux CPU 1
|
||||
-> [Compute Unit 1] -> [Compute Unit Core 0] -> Linux CPU 2
|
||||
-> [Compute Unit Core 1] -> Linux CPU 3
|
||||
|
||||
[node 1] -> [Compute Unit 0] -> [Compute Unit Core 0] -> Linux CPU 4
|
||||
-> [Compute Unit Core 1] -> Linux CPU 5
|
||||
-> [Compute Unit 1] -> [Compute Unit Core 0] -> Linux CPU 6
|
||||
-> [Compute Unit Core 1] -> Linux CPU 7
|
44
MAINTAINERS
44
MAINTAINERS
|
@ -4302,7 +4302,7 @@ F: drivers/net/ethernet/agere/
|
|||
|
||||
ETHERNET BRIDGE
|
||||
M: Stephen Hemminger <stephen@networkplumber.org>
|
||||
L: bridge@lists.linux-foundation.org
|
||||
L: bridge@lists.linux-foundation.org (moderated for non-subscribers)
|
||||
L: netdev@vger.kernel.org
|
||||
W: http://www.linuxfoundation.org/en/Net:Bridge
|
||||
S: Maintained
|
||||
|
@ -5042,6 +5042,7 @@ F: include/linux/hw_random.h
|
|||
HARDWARE SPINLOCK CORE
|
||||
M: Ohad Ben-Cohen <ohad@wizery.com>
|
||||
M: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
L: linux-remoteproc@vger.kernel.org
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ohad/hwspinlock.git
|
||||
F: Documentation/hwspinlock.txt
|
||||
|
@ -5750,7 +5751,7 @@ R: Don Skidmore <donald.c.skidmore@intel.com>
|
|||
R: Bruce Allan <bruce.w.allan@intel.com>
|
||||
R: John Ronciak <john.ronciak@intel.com>
|
||||
R: Mitch Williams <mitch.a.williams@intel.com>
|
||||
L: intel-wired-lan@lists.osuosl.org
|
||||
L: intel-wired-lan@lists.osuosl.org (moderated for non-subscribers)
|
||||
W: http://www.intel.com/support/feedback.htm
|
||||
W: http://e1000.sourceforge.net/
|
||||
Q: http://patchwork.ozlabs.org/project/intel-wired-lan/list/
|
||||
|
@ -6402,7 +6403,7 @@ KPROBES
|
|||
M: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
|
||||
M: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
|
||||
M: "David S. Miller" <davem@davemloft.net>
|
||||
M: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
|
||||
M: Masami Hiramatsu <mhiramat@kernel.org>
|
||||
S: Maintained
|
||||
F: Documentation/kprobes.txt
|
||||
F: include/linux/kprobes.h
|
||||
|
@ -7575,7 +7576,7 @@ F: drivers/infiniband/hw/nes/
|
|||
|
||||
NETEM NETWORK EMULATOR
|
||||
M: Stephen Hemminger <stephen@networkplumber.org>
|
||||
L: netem@lists.linux-foundation.org
|
||||
L: netem@lists.linux-foundation.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: net/sched/sch_netem.c
|
||||
|
||||
|
@ -8253,7 +8254,7 @@ F: Documentation/filesystems/overlayfs.txt
|
|||
|
||||
ORANGEFS FILESYSTEM
|
||||
M: Mike Marshall <hubcap@omnibond.com>
|
||||
L: pvfs2-developers@beowulf-underground.org
|
||||
L: pvfs2-developers@beowulf-underground.org (subscribers-only)
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux.git
|
||||
S: Supported
|
||||
F: fs/orangefs/
|
||||
|
@ -8711,6 +8712,8 @@ F: drivers/pinctrl/sh-pfc/
|
|||
|
||||
PIN CONTROLLER - SAMSUNG
|
||||
M: Tomasz Figa <tomasz.figa@gmail.com>
|
||||
M: Krzysztof Kozlowski <k.kozlowski@samsung.com>
|
||||
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
|
@ -9139,6 +9142,13 @@ T: git git://github.com/KrasnikovEugene/wcn36xx.git
|
|||
S: Supported
|
||||
F: drivers/net/wireless/ath/wcn36xx/
|
||||
|
||||
QEMU MACHINE EMULATOR AND VIRTUALIZER SUPPORT
|
||||
M: Gabriel Somlo <somlo@cmu.edu>
|
||||
M: "Michael S. Tsirkin" <mst@redhat.com>
|
||||
L: qemu-devel@nongnu.org
|
||||
S: Maintained
|
||||
F: drivers/firmware/qemu_fw_cfg.c
|
||||
|
||||
RADOS BLOCK DEVICE (RBD)
|
||||
M: Ilya Dryomov <idryomov@gmail.com>
|
||||
M: Sage Weil <sage@redhat.com>
|
||||
|
@ -9314,6 +9324,7 @@ F: include/linux/regmap.h
|
|||
REMOTE PROCESSOR (REMOTEPROC) SUBSYSTEM
|
||||
M: Ohad Ben-Cohen <ohad@wizery.com>
|
||||
M: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
L: linux-remoteproc@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ohad/remoteproc.git
|
||||
S: Maintained
|
||||
F: drivers/remoteproc/
|
||||
|
@ -9323,6 +9334,7 @@ F: include/linux/remoteproc.h
|
|||
REMOTE PROCESSOR MESSAGING (RPMSG) SUBSYSTEM
|
||||
M: Ohad Ben-Cohen <ohad@wizery.com>
|
||||
M: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
L: linux-remoteproc@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ohad/rpmsg.git
|
||||
S: Maintained
|
||||
F: drivers/rpmsg/
|
||||
|
@ -10583,6 +10595,14 @@ L: linux-tegra@vger.kernel.org
|
|||
S: Maintained
|
||||
F: drivers/staging/nvec/
|
||||
|
||||
STAGING - OLPC SECONDARY DISPLAY CONTROLLER (DCON)
|
||||
M: Jens Frederich <jfrederich@gmail.com>
|
||||
M: Daniel Drake <dsd@laptop.org>
|
||||
M: Jon Nettleton <jon.nettleton@gmail.com>
|
||||
W: http://wiki.laptop.org/go/DCON
|
||||
S: Maintained
|
||||
F: drivers/staging/olpc_dcon/
|
||||
|
||||
STAGING - REALTEK RTL8712U DRIVERS
|
||||
M: Larry Finger <Larry.Finger@lwfinger.net>
|
||||
M: Florian Schilhabel <florian.c.schilhabel@googlemail.com>.
|
||||
|
@ -11137,8 +11157,8 @@ F: include/uapi/linux/tipc*.h
|
|||
F: net/tipc/
|
||||
|
||||
TILE ARCHITECTURE
|
||||
M: Chris Metcalf <cmetcalf@ezchip.com>
|
||||
W: http://www.ezchip.com/scm/
|
||||
M: Chris Metcalf <cmetcalf@mellanox.com>
|
||||
W: http://www.mellanox.com/repository/solutions/tile-scm/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile.git
|
||||
S: Supported
|
||||
F: arch/tile/
|
||||
|
@ -12202,9 +12222,9 @@ S: Maintained
|
|||
F: drivers/media/tuners/tuner-xc2028.*
|
||||
|
||||
XEN HYPERVISOR INTERFACE
|
||||
M: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
|
||||
M: Boris Ostrovsky <boris.ostrovsky@oracle.com>
|
||||
M: David Vrabel <david.vrabel@citrix.com>
|
||||
M: Juergen Gross <jgross@suse.com>
|
||||
L: xen-devel@lists.xenproject.org (moderated for non-subscribers)
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git
|
||||
S: Supported
|
||||
|
@ -12216,16 +12236,16 @@ F: include/xen/
|
|||
F: include/uapi/xen/
|
||||
|
||||
XEN HYPERVISOR ARM
|
||||
M: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
|
||||
M: Stefano Stabellini <sstabellini@kernel.org>
|
||||
L: xen-devel@lists.xenproject.org (moderated for non-subscribers)
|
||||
S: Supported
|
||||
S: Maintained
|
||||
F: arch/arm/xen/
|
||||
F: arch/arm/include/asm/xen/
|
||||
|
||||
XEN HYPERVISOR ARM64
|
||||
M: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
|
||||
M: Stefano Stabellini <sstabellini@kernel.org>
|
||||
L: xen-devel@lists.xenproject.org (moderated for non-subscribers)
|
||||
S: Supported
|
||||
S: Maintained
|
||||
F: arch/arm64/xen/
|
||||
F: arch/arm64/include/asm/xen/
|
||||
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 4
|
||||
PATCHLEVEL = 6
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc1
|
||||
EXTRAVERSION = -rc3
|
||||
NAME = Blurry Fish Butt
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -628,7 +628,7 @@ void flush_dcache_page(struct page *page)
|
|||
|
||||
/* kernel reading from page with U-mapping */
|
||||
phys_addr_t paddr = (unsigned long)page_address(page);
|
||||
unsigned long vaddr = page->index << PAGE_CACHE_SHIFT;
|
||||
unsigned long vaddr = page->index << PAGE_SHIFT;
|
||||
|
||||
if (addr_not_cache_congruent(paddr, vaddr))
|
||||
__flush_dcache_page(paddr, vaddr);
|
||||
|
|
|
@ -88,7 +88,7 @@ $(obj)/bootpImage: $(obj)/bootp/bootp FORCE
|
|||
$(call if_changed,objcopy)
|
||||
@$(kecho) ' Kernel: $@ is ready'
|
||||
|
||||
PHONY += initrd
|
||||
PHONY += initrd install zinstall uinstall
|
||||
initrd:
|
||||
@test "$(INITRD_PHYS)" != "" || \
|
||||
(echo This machine does not support INITRD; exit -1)
|
||||
|
|
|
@ -162,8 +162,6 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
|
|||
|
||||
static inline void dma_mark_clean(void *addr, size_t size) { }
|
||||
|
||||
extern int arm_dma_set_mask(struct device *dev, u64 dma_mask);
|
||||
|
||||
/**
|
||||
* arm_dma_alloc - allocate consistent memory for DMA
|
||||
* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
|
||||
|
|
|
@ -392,9 +392,18 @@ void __iomem *ioremap(resource_size_t res_cookie, size_t size);
|
|||
#define ioremap ioremap
|
||||
#define ioremap_nocache ioremap
|
||||
|
||||
/*
|
||||
* Do not use ioremap_cache for mapping memory. Use memremap instead.
|
||||
*/
|
||||
void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size);
|
||||
#define ioremap_cache ioremap_cache
|
||||
|
||||
/*
|
||||
* Do not use ioremap_cached in new code. Provided for the benefit of
|
||||
* the pxa2xx-flash MTD driver only.
|
||||
*/
|
||||
void __iomem *ioremap_cached(resource_size_t res_cookie, size_t size);
|
||||
|
||||
void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size);
|
||||
#define ioremap_wc ioremap_wc
|
||||
#define ioremap_wt ioremap_wc
|
||||
|
@ -402,6 +411,9 @@ void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size);
|
|||
void iounmap(volatile void __iomem *iomem_cookie);
|
||||
#define iounmap iounmap
|
||||
|
||||
void *arch_memremap_wb(phys_addr_t phys_addr, size_t size);
|
||||
#define arch_memremap_wb arch_memremap_wb
|
||||
|
||||
/*
|
||||
* io{read,write}{16,32}be() macros
|
||||
*/
|
||||
|
|
|
@ -288,19 +288,43 @@ static inline void *phys_to_virt(phys_addr_t x)
|
|||
#define __va(x) ((void *)__phys_to_virt((phys_addr_t)(x)))
|
||||
#define pfn_to_kaddr(pfn) __va((phys_addr_t)(pfn) << PAGE_SHIFT)
|
||||
|
||||
extern unsigned long (*arch_virt_to_idmap)(unsigned long x);
|
||||
extern long long arch_phys_to_idmap_offset;
|
||||
|
||||
/*
|
||||
* These are for systems that have a hardware interconnect supported alias of
|
||||
* physical memory for idmap purposes. Most cases should leave these
|
||||
* These are for systems that have a hardware interconnect supported alias
|
||||
* of physical memory for idmap purposes. Most cases should leave these
|
||||
* untouched. Note: this can only return addresses less than 4GiB.
|
||||
*/
|
||||
static inline bool arm_has_idmap_alias(void)
|
||||
{
|
||||
return IS_ENABLED(CONFIG_MMU) && arch_phys_to_idmap_offset != 0;
|
||||
}
|
||||
|
||||
#define IDMAP_INVALID_ADDR ((u32)~0)
|
||||
|
||||
static inline unsigned long phys_to_idmap(phys_addr_t addr)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_MMU) && arch_phys_to_idmap_offset) {
|
||||
addr += arch_phys_to_idmap_offset;
|
||||
if (addr > (u32)~0)
|
||||
addr = IDMAP_INVALID_ADDR;
|
||||
}
|
||||
return addr;
|
||||
}
|
||||
|
||||
static inline phys_addr_t idmap_to_phys(unsigned long idmap)
|
||||
{
|
||||
phys_addr_t addr = idmap;
|
||||
|
||||
if (IS_ENABLED(CONFIG_MMU) && arch_phys_to_idmap_offset)
|
||||
addr -= arch_phys_to_idmap_offset;
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
static inline unsigned long __virt_to_idmap(unsigned long x)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_MMU) && arch_virt_to_idmap)
|
||||
return arch_virt_to_idmap(x);
|
||||
else
|
||||
return __virt_to_phys(x);
|
||||
return phys_to_idmap(__virt_to_phys(x));
|
||||
}
|
||||
|
||||
#define virt_to_idmap(x) __virt_to_idmap((unsigned long)(x))
|
||||
|
|
|
@ -19,7 +19,7 @@
|
|||
* This may need to be greater than __NR_last_syscall+1 in order to
|
||||
* account for the padding in the syscall table
|
||||
*/
|
||||
#define __NR_syscalls (392)
|
||||
#define __NR_syscalls (396)
|
||||
|
||||
#define __ARCH_WANT_STAT64
|
||||
#define __ARCH_WANT_SYS_GETHOSTNAME
|
||||
|
|
|
@ -418,6 +418,8 @@
|
|||
#define __NR_membarrier (__NR_SYSCALL_BASE+389)
|
||||
#define __NR_mlock2 (__NR_SYSCALL_BASE+390)
|
||||
#define __NR_copy_file_range (__NR_SYSCALL_BASE+391)
|
||||
#define __NR_preadv2 (__NR_SYSCALL_BASE+392)
|
||||
#define __NR_pwritev2 (__NR_SYSCALL_BASE+393)
|
||||
|
||||
/*
|
||||
* The following SWIs are ARM private.
|
||||
|
|
|
@ -550,9 +550,6 @@ char * __init pcibios_setup(char *str)
|
|||
if (!strcmp(str, "debug")) {
|
||||
debug_pci = 1;
|
||||
return NULL;
|
||||
} else if (!strcmp(str, "firmware")) {
|
||||
pci_add_flags(PCI_PROBE_ONLY);
|
||||
return NULL;
|
||||
}
|
||||
return str;
|
||||
}
|
||||
|
|
|
@ -399,8 +399,10 @@
|
|||
CALL(sys_execveat)
|
||||
CALL(sys_userfaultfd)
|
||||
CALL(sys_membarrier)
|
||||
CALL(sys_mlock2)
|
||||
/* 390 */ CALL(sys_mlock2)
|
||||
CALL(sys_copy_file_range)
|
||||
CALL(sys_preadv2)
|
||||
CALL(sys_pwritev2)
|
||||
#ifndef syscalls_counted
|
||||
.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
|
||||
#define syscalls_counted
|
||||
|
|
|
@ -104,8 +104,6 @@ void machine_halt(void)
|
|||
{
|
||||
local_irq_disable();
|
||||
smp_send_stop();
|
||||
|
||||
local_irq_disable();
|
||||
while (1);
|
||||
}
|
||||
|
||||
|
@ -150,6 +148,5 @@ void machine_restart(char *cmd)
|
|||
|
||||
/* Whoops - the platform was unable to reboot. Tell the user! */
|
||||
printk("Reboot failed -- System halted\n");
|
||||
local_irq_disable();
|
||||
while (1);
|
||||
}
|
||||
|
|
|
@ -430,11 +430,13 @@ static void __init patch_aeabi_idiv(void)
|
|||
pr_info("CPU: div instructions available: patching division code\n");
|
||||
|
||||
fn_addr = ((uintptr_t)&__aeabi_uidiv) & ~1;
|
||||
asm ("" : "+g" (fn_addr));
|
||||
((u32 *)fn_addr)[0] = udiv_instruction();
|
||||
((u32 *)fn_addr)[1] = bx_lr_instruction();
|
||||
flush_icache_range(fn_addr, fn_addr + 8);
|
||||
|
||||
fn_addr = ((uintptr_t)&__aeabi_idiv) & ~1;
|
||||
asm ("" : "+g" (fn_addr));
|
||||
((u32 *)fn_addr)[0] = sdiv_instruction();
|
||||
((u32 *)fn_addr)[1] = bx_lr_instruction();
|
||||
flush_icache_range(fn_addr, fn_addr + 8);
|
||||
|
@ -938,6 +940,12 @@ static int __init init_machine_late(void)
|
|||
late_initcall(init_machine_late);
|
||||
|
||||
#ifdef CONFIG_KEXEC
|
||||
/*
|
||||
* The crash region must be aligned to 128MB to avoid
|
||||
* zImage relocating below the reserved region.
|
||||
*/
|
||||
#define CRASH_ALIGN (128 << 20)
|
||||
|
||||
static inline unsigned long long get_total_mem(void)
|
||||
{
|
||||
unsigned long total;
|
||||
|
@ -965,6 +973,26 @@ static void __init reserve_crashkernel(void)
|
|||
if (ret)
|
||||
return;
|
||||
|
||||
if (crash_base <= 0) {
|
||||
unsigned long long crash_max = idmap_to_phys((u32)~0);
|
||||
crash_base = memblock_find_in_range(CRASH_ALIGN, crash_max,
|
||||
crash_size, CRASH_ALIGN);
|
||||
if (!crash_base) {
|
||||
pr_err("crashkernel reservation failed - No suitable area found.\n");
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
unsigned long long start;
|
||||
|
||||
start = memblock_find_in_range(crash_base,
|
||||
crash_base + crash_size,
|
||||
crash_size, SECTION_SIZE);
|
||||
if (start != crash_base) {
|
||||
pr_err("crashkernel reservation failed - memory is in use.\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
ret = memblock_reserve(crash_base, crash_size);
|
||||
if (ret < 0) {
|
||||
pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n",
|
||||
|
|
|
@ -1061,15 +1061,27 @@ static void cpu_init_hyp_mode(void *dummy)
|
|||
kvm_arm_init_debug();
|
||||
}
|
||||
|
||||
static void cpu_hyp_reinit(void)
|
||||
{
|
||||
if (is_kernel_in_hyp_mode()) {
|
||||
/*
|
||||
* cpu_init_stage2() is safe to call even if the PM
|
||||
* event was cancelled before the CPU was reset.
|
||||
*/
|
||||
cpu_init_stage2(NULL);
|
||||
} else {
|
||||
if (__hyp_get_vectors() == hyp_default_vectors)
|
||||
cpu_init_hyp_mode(NULL);
|
||||
}
|
||||
}
|
||||
|
||||
static int hyp_init_cpu_notify(struct notifier_block *self,
|
||||
unsigned long action, void *cpu)
|
||||
{
|
||||
switch (action) {
|
||||
case CPU_STARTING:
|
||||
case CPU_STARTING_FROZEN:
|
||||
if (__hyp_get_vectors() == hyp_default_vectors)
|
||||
cpu_init_hyp_mode(NULL);
|
||||
break;
|
||||
cpu_hyp_reinit();
|
||||
}
|
||||
|
||||
return NOTIFY_OK;
|
||||
|
@ -1084,9 +1096,8 @@ static int hyp_init_cpu_pm_notifier(struct notifier_block *self,
|
|||
unsigned long cmd,
|
||||
void *v)
|
||||
{
|
||||
if (cmd == CPU_PM_EXIT &&
|
||||
__hyp_get_vectors() == hyp_default_vectors) {
|
||||
cpu_init_hyp_mode(NULL);
|
||||
if (cmd == CPU_PM_EXIT) {
|
||||
cpu_hyp_reinit();
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
|
@ -1127,6 +1138,22 @@ static int init_subsystems(void)
|
|||
{
|
||||
int err;
|
||||
|
||||
/*
|
||||
* Register CPU Hotplug notifier
|
||||
*/
|
||||
cpu_notifier_register_begin();
|
||||
err = __register_cpu_notifier(&hyp_init_cpu_nb);
|
||||
cpu_notifier_register_done();
|
||||
if (err) {
|
||||
kvm_err("Cannot register KVM init CPU notifier (%d)\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* Register CPU lower-power notifier
|
||||
*/
|
||||
hyp_cpu_pm_init();
|
||||
|
||||
/*
|
||||
* Init HYP view of VGIC
|
||||
*/
|
||||
|
@ -1270,19 +1297,6 @@ static int init_hyp_mode(void)
|
|||
free_boot_hyp_pgd();
|
||||
#endif
|
||||
|
||||
cpu_notifier_register_begin();
|
||||
|
||||
err = __register_cpu_notifier(&hyp_init_cpu_nb);
|
||||
|
||||
cpu_notifier_register_done();
|
||||
|
||||
if (err) {
|
||||
kvm_err("Cannot register HYP init CPU notifier (%d)\n", err);
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
hyp_cpu_pm_init();
|
||||
|
||||
/* set size of VMID supported by CPU */
|
||||
kvm_vmid_bits = kvm_get_vmid_bits();
|
||||
kvm_info("%d-bit VMID\n", kvm_vmid_bits);
|
||||
|
|
|
@ -63,11 +63,6 @@ static void __init keystone_init(void)
|
|||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static unsigned long keystone_virt_to_idmap(unsigned long x)
|
||||
{
|
||||
return (phys_addr_t)(x) - CONFIG_PAGE_OFFSET + KEYSTONE_LOW_PHYS_START;
|
||||
}
|
||||
|
||||
static long long __init keystone_pv_fixup(void)
|
||||
{
|
||||
long long offset;
|
||||
|
@ -91,7 +86,7 @@ static long long __init keystone_pv_fixup(void)
|
|||
offset = KEYSTONE_HIGH_PHYS_START - KEYSTONE_LOW_PHYS_START;
|
||||
|
||||
/* Populate the arch idmap hook */
|
||||
arch_virt_to_idmap = keystone_virt_to_idmap;
|
||||
arch_phys_to_idmap_offset = -offset;
|
||||
|
||||
return offset;
|
||||
}
|
||||
|
|
|
@ -647,11 +647,6 @@ static void __init l2c310_enable(void __iomem *base, unsigned num_lock)
|
|||
aux &= ~(L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP);
|
||||
}
|
||||
|
||||
/* r3p0 or later has power control register */
|
||||
if (rev >= L310_CACHE_ID_RTL_R3P0)
|
||||
l2x0_saved_regs.pwr_ctrl = L310_DYNAMIC_CLK_GATING_EN |
|
||||
L310_STNDBY_MODE_EN;
|
||||
|
||||
/*
|
||||
* Always enable non-secure access to the lockdown registers -
|
||||
* we write to them as part of the L2C enable sequence so they
|
||||
|
@ -1141,6 +1136,7 @@ static void __init l2c310_of_parse(const struct device_node *np,
|
|||
u32 filter[2] = { 0, 0 };
|
||||
u32 assoc;
|
||||
u32 prefetch;
|
||||
u32 power;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
|
@ -1271,6 +1267,26 @@ static void __init l2c310_of_parse(const struct device_node *np,
|
|||
}
|
||||
|
||||
l2x0_saved_regs.prefetch_ctrl = prefetch;
|
||||
|
||||
power = l2x0_saved_regs.pwr_ctrl |
|
||||
L310_DYNAMIC_CLK_GATING_EN | L310_STNDBY_MODE_EN;
|
||||
|
||||
ret = of_property_read_u32(np, "arm,dynamic-clock-gating", &val);
|
||||
if (!ret) {
|
||||
if (!val)
|
||||
power &= ~L310_DYNAMIC_CLK_GATING_EN;
|
||||
} else if (ret != -EINVAL) {
|
||||
pr_err("L2C-310 OF dynamic-clock-gating property value is missing or invalid\n");
|
||||
}
|
||||
ret = of_property_read_u32(np, "arm,standby-mode", &val);
|
||||
if (!ret) {
|
||||
if (!val)
|
||||
power &= ~L310_STNDBY_MODE_EN;
|
||||
} else if (ret != -EINVAL) {
|
||||
pr_err("L2C-310 OF standby-mode property value is missing or invalid\n");
|
||||
}
|
||||
|
||||
l2x0_saved_regs.pwr_ctrl = power;
|
||||
}
|
||||
|
||||
static const struct l2c_init_data of_l2c310_data __initconst = {
|
||||
|
|
|
@ -96,6 +96,7 @@ struct uniphier_cache_data {
|
|||
void __iomem *ctrl_base;
|
||||
void __iomem *rev_base;
|
||||
void __iomem *op_base;
|
||||
void __iomem *way_ctrl_base;
|
||||
u32 way_present_mask;
|
||||
u32 way_locked_mask;
|
||||
u32 nsets;
|
||||
|
@ -256,10 +257,13 @@ static void __init __uniphier_cache_set_locked_ways(
|
|||
struct uniphier_cache_data *data,
|
||||
u32 way_mask)
|
||||
{
|
||||
unsigned int cpu;
|
||||
|
||||
data->way_locked_mask = way_mask & data->way_present_mask;
|
||||
|
||||
writel_relaxed(~data->way_locked_mask & data->way_present_mask,
|
||||
data->ctrl_base + UNIPHIER_SSCLPDAWCR);
|
||||
for_each_possible_cpu(cpu)
|
||||
writel_relaxed(~data->way_locked_mask & data->way_present_mask,
|
||||
data->way_ctrl_base + 4 * cpu);
|
||||
}
|
||||
|
||||
static void uniphier_cache_maint_range(unsigned long start, unsigned long end,
|
||||
|
@ -459,6 +463,8 @@ static int __init __uniphier_cache_init(struct device_node *np,
|
|||
goto err;
|
||||
}
|
||||
|
||||
data->way_ctrl_base = data->ctrl_base + 0xc00;
|
||||
|
||||
if (*cache_level == 2) {
|
||||
u32 revision = readl(data->rev_base + UNIPHIER_SSCID);
|
||||
/*
|
||||
|
@ -467,6 +473,22 @@ static int __init __uniphier_cache_init(struct device_node *np,
|
|||
*/
|
||||
if (revision <= 0x16)
|
||||
data->range_op_max_size = (u32)1 << 22;
|
||||
|
||||
/*
|
||||
* Unfortunatly, the offset address of active way control base
|
||||
* varies from SoC to SoC.
|
||||
*/
|
||||
switch (revision) {
|
||||
case 0x11: /* sLD3 */
|
||||
data->way_ctrl_base = data->ctrl_base + 0x870;
|
||||
break;
|
||||
case 0x12: /* LD4 */
|
||||
case 0x16: /* sld8 */
|
||||
data->way_ctrl_base = data->ctrl_base + 0x840;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
data->range_op_max_size -= data->line_size;
|
||||
|
|
|
@ -190,7 +190,6 @@ struct dma_map_ops arm_dma_ops = {
|
|||
.sync_single_for_device = arm_dma_sync_single_for_device,
|
||||
.sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
|
||||
.sync_sg_for_device = arm_dma_sync_sg_for_device,
|
||||
.set_dma_mask = arm_dma_set_mask,
|
||||
};
|
||||
EXPORT_SYMBOL(arm_dma_ops);
|
||||
|
||||
|
@ -209,7 +208,6 @@ struct dma_map_ops arm_coherent_dma_ops = {
|
|||
.get_sgtable = arm_dma_get_sgtable,
|
||||
.map_page = arm_coherent_dma_map_page,
|
||||
.map_sg = arm_dma_map_sg,
|
||||
.set_dma_mask = arm_dma_set_mask,
|
||||
};
|
||||
EXPORT_SYMBOL(arm_coherent_dma_ops);
|
||||
|
||||
|
@ -1142,16 +1140,6 @@ int dma_supported(struct device *dev, u64 mask)
|
|||
}
|
||||
EXPORT_SYMBOL(dma_supported);
|
||||
|
||||
int arm_dma_set_mask(struct device *dev, u64 dma_mask)
|
||||
{
|
||||
if (!dev->dma_mask || !dma_supported(dev, dma_mask))
|
||||
return -EIO;
|
||||
|
||||
*dev->dma_mask = dma_mask;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define PREALLOC_DMA_DEBUG_ENTRIES 4096
|
||||
|
||||
static int __init dma_debug_do_init(void)
|
||||
|
@ -2005,8 +1993,6 @@ struct dma_map_ops iommu_ops = {
|
|||
.unmap_sg = arm_iommu_unmap_sg,
|
||||
.sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
|
||||
.sync_sg_for_device = arm_iommu_sync_sg_for_device,
|
||||
|
||||
.set_dma_mask = arm_dma_set_mask,
|
||||
};
|
||||
|
||||
struct dma_map_ops iommu_coherent_ops = {
|
||||
|
@ -2020,8 +2006,6 @@ struct dma_map_ops iommu_coherent_ops = {
|
|||
|
||||
.map_sg = arm_coherent_iommu_map_sg,
|
||||
.unmap_sg = arm_coherent_iommu_unmap_sg,
|
||||
|
||||
.set_dma_mask = arm_dma_set_mask,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
@ -235,7 +235,7 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page)
|
|||
*/
|
||||
if (mapping && cache_is_vipt_aliasing())
|
||||
flush_pfn_alias(page_to_pfn(page),
|
||||
page->index << PAGE_CACHE_SHIFT);
|
||||
page->index << PAGE_SHIFT);
|
||||
}
|
||||
|
||||
static void __flush_dcache_aliases(struct address_space *mapping, struct page *page)
|
||||
|
@ -250,7 +250,7 @@ static void __flush_dcache_aliases(struct address_space *mapping, struct page *p
|
|||
* data in the current VM view associated with this page.
|
||||
* - aliasing VIPT: we only need to find one mapping of this page.
|
||||
*/
|
||||
pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
|
||||
pgoff = page->index;
|
||||
|
||||
flush_dcache_mmap_lock(mapping);
|
||||
vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
|
||||
|
|
|
@ -15,7 +15,7 @@
|
|||
* page tables.
|
||||
*/
|
||||
pgd_t *idmap_pgd;
|
||||
unsigned long (*arch_virt_to_idmap)(unsigned long x);
|
||||
long long arch_phys_to_idmap_offset;
|
||||
|
||||
#ifdef CONFIG_ARM_LPAE
|
||||
static void idmap_add_pmd(pud_t *pud, unsigned long addr, unsigned long end,
|
||||
|
|
|
@ -297,9 +297,10 @@ static void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
|
|||
}
|
||||
|
||||
/*
|
||||
* Don't allow RAM to be mapped - this causes problems with ARMv6+
|
||||
* Don't allow RAM to be mapped with mismatched attributes - this
|
||||
* causes problems with ARMv6+
|
||||
*/
|
||||
if (WARN_ON(pfn_valid(pfn)))
|
||||
if (WARN_ON(pfn_valid(pfn) && mtype != MT_MEMORY_RW))
|
||||
return NULL;
|
||||
|
||||
area = get_vm_area_caller(size, VM_IOREMAP, caller);
|
||||
|
@ -380,11 +381,15 @@ void __iomem *ioremap(resource_size_t res_cookie, size_t size)
|
|||
EXPORT_SYMBOL(ioremap);
|
||||
|
||||
void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size)
|
||||
__alias(ioremap_cached);
|
||||
|
||||
void __iomem *ioremap_cached(resource_size_t res_cookie, size_t size)
|
||||
{
|
||||
return arch_ioremap_caller(res_cookie, size, MT_DEVICE_CACHED,
|
||||
__builtin_return_address(0));
|
||||
}
|
||||
EXPORT_SYMBOL(ioremap_cache);
|
||||
EXPORT_SYMBOL(ioremap_cached);
|
||||
|
||||
void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size)
|
||||
{
|
||||
|
@ -414,6 +419,13 @@ __arm_ioremap_exec(phys_addr_t phys_addr, size_t size, bool cached)
|
|||
__builtin_return_address(0));
|
||||
}
|
||||
|
||||
void *arch_memremap_wb(phys_addr_t phys_addr, size_t size)
|
||||
{
|
||||
return (__force void *)arch_ioremap_caller(phys_addr, size,
|
||||
MT_MEMORY_RW,
|
||||
__builtin_return_address(0));
|
||||
}
|
||||
|
||||
void __iounmap(volatile void __iomem *io_addr)
|
||||
{
|
||||
void *addr = (void *)(PAGE_MASK & (unsigned long)io_addr);
|
||||
|
|
|
@ -367,11 +367,15 @@ void __iomem *ioremap(resource_size_t res_cookie, size_t size)
|
|||
EXPORT_SYMBOL(ioremap);
|
||||
|
||||
void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size)
|
||||
__alias(ioremap_cached);
|
||||
|
||||
void __iomem *ioremap_cached(resource_size_t res_cookie, size_t size)
|
||||
{
|
||||
return __arm_ioremap_caller(res_cookie, size, MT_DEVICE_CACHED,
|
||||
__builtin_return_address(0));
|
||||
}
|
||||
EXPORT_SYMBOL(ioremap_cache);
|
||||
EXPORT_SYMBOL(ioremap_cached);
|
||||
|
||||
void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size)
|
||||
{
|
||||
|
@ -380,6 +384,11 @@ void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size)
|
|||
}
|
||||
EXPORT_SYMBOL(ioremap_wc);
|
||||
|
||||
void *arch_memremap_wb(phys_addr_t phys_addr, size_t size)
|
||||
{
|
||||
return (void *)phys_addr;
|
||||
}
|
||||
|
||||
void __iounmap(volatile void __iomem *addr)
|
||||
{
|
||||
}
|
||||
|
|
|
@ -281,12 +281,12 @@ __v7_ca17mp_setup:
|
|||
bl v7_invalidate_l1
|
||||
ldmia r12, {r1-r6, lr}
|
||||
#ifdef CONFIG_SMP
|
||||
orr r10, r10, #(1 << 6) @ Enable SMP/nAMP mode
|
||||
ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
|
||||
ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
|
||||
tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
|
||||
orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
|
||||
orreq r0, r0, r10 @ Enable CPU-specific SMP bits
|
||||
mcreq p15, 0, r0, c1, c0, 1
|
||||
ALT_UP(mov r0, r10) @ fake it for UP
|
||||
orr r10, r10, r0 @ Set required bits
|
||||
teq r10, r0 @ Were they already set?
|
||||
mcrne p15, 0, r10, c1, c0, 1 @ No, update register
|
||||
#endif
|
||||
b __v7_setup_cont
|
||||
|
||||
|
|
|
@ -4,7 +4,10 @@
|
|||
# Copyright (C) 2001 Russell King
|
||||
#
|
||||
|
||||
include/generated/mach-types.h: $(src)/gen-mach-types $(src)/mach-types
|
||||
@$(kecho) ' Generating $@'
|
||||
@mkdir -p $(dir $@)
|
||||
$(Q)$(AWK) -f $^ > $@ || { rm -f $@; /bin/false; }
|
||||
quiet_cmd_gen_mach = GEN $@
|
||||
cmd_gen_mach = mkdir -p $(dir $@) && \
|
||||
$(AWK) -f $(filter-out $(PHONY),$^) > $@ || \
|
||||
{ rm -f $@; /bin/false; }
|
||||
|
||||
include/generated/mach-types.h: $(src)/gen-mach-types $(src)/mach-types FORCE
|
||||
$(call if_changed,gen_mach)
|
||||
|
|
|
@ -68,11 +68,13 @@ CONFIG_KSM=y
|
|||
CONFIG_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_CMA=y
|
||||
CONFIG_XEN=y
|
||||
CONFIG_CMDLINE="console=ttyAMA0"
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_COMPAT=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_ARM_CPUIDLE=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_ARM_BIG_LITTLE_CPUFREQ=y
|
||||
CONFIG_ARM_SCPI_CPUFREQ=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
@ -80,7 +82,6 @@ CONFIG_INET=y
|
|||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_BPF_JIT=y
|
||||
# CONFIG_WIRELESS is not set
|
||||
|
@ -144,16 +145,18 @@ CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
|
|||
CONFIG_SERIAL_MVEBU_UART=y
|
||||
CONFIG_VIRTIO_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
CONFIG_I2C_MV64XXX=y
|
||||
CONFIG_I2C_QUP=y
|
||||
CONFIG_I2C_TEGRA=y
|
||||
CONFIG_I2C_UNIPHIER_F=y
|
||||
CONFIG_I2C_RCAR=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_PL022=y
|
||||
CONFIG_SPI_QUP=y
|
||||
CONFIG_SPMI=y
|
||||
CONFIG_PINCTRL_SINGLE=y
|
||||
CONFIG_PINCTRL_MSM8916=y
|
||||
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
|
@ -196,6 +199,7 @@ CONFIG_USB_EHCI_HCD_PLATFORM=y
|
|||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_DWC2=y
|
||||
CONFIG_USB_CHIPIDEA=y
|
||||
CONFIG_USB_CHIPIDEA_UDC=y
|
||||
CONFIG_USB_CHIPIDEA_HOST=y
|
||||
|
@ -205,19 +209,20 @@ CONFIG_USB_MSM_OTG=y
|
|||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK_MINORS=16
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
CONFIG_MMC_ARMMMCI=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMC_SDHCI_TEGRA=y
|
||||
CONFIG_MMC_SDHCI_MSM=y
|
||||
CONFIG_MMC_SPI=y
|
||||
CONFIG_MMC_SUNXI=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_EXYNOS=y
|
||||
CONFIG_MMC_BLOCK_MINORS=16
|
||||
CONFIG_MMC_DW_K3=y
|
||||
CONFIG_MMC_SUNXI=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_SYSCON=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
|
@ -229,8 +234,8 @@ CONFIG_RTC_DRV_PL031=y
|
|||
CONFIG_RTC_DRV_SUN6I=y
|
||||
CONFIG_RTC_DRV_XGENE=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_QCOM_BAM_DMA=y
|
||||
CONFIG_TEGRA20_APB_DMA=y
|
||||
CONFIG_QCOM_BAM_DMA=y
|
||||
CONFIG_RCAR_DMAC=y
|
||||
CONFIG_VFIO=y
|
||||
CONFIG_VFIO_PCI=y
|
||||
|
@ -239,20 +244,26 @@ CONFIG_VIRTIO_BALLOON=y
|
|||
CONFIG_VIRTIO_MMIO=y
|
||||
CONFIG_XEN_GNTDEV=y
|
||||
CONFIG_XEN_GRANT_DEV_ALLOC=y
|
||||
CONFIG_COMMON_CLK_SCPI=y
|
||||
CONFIG_COMMON_CLK_CS2000_CP=y
|
||||
CONFIG_COMMON_CLK_QCOM=y
|
||||
CONFIG_MSM_GCC_8916=y
|
||||
CONFIG_HWSPINLOCK_QCOM=y
|
||||
CONFIG_MAILBOX=y
|
||||
CONFIG_ARM_MHU=y
|
||||
CONFIG_HI6220_MBOX=y
|
||||
CONFIG_ARM_SMMU=y
|
||||
CONFIG_QCOM_SMEM=y
|
||||
CONFIG_QCOM_SMD=y
|
||||
CONFIG_QCOM_SMD_RPM=y
|
||||
CONFIG_ARCH_TEGRA_132_SOC=y
|
||||
CONFIG_ARCH_TEGRA_210_SOC=y
|
||||
CONFIG_HISILICON_IRQ_MBIGEN=y
|
||||
CONFIG_EXTCON_USB_GPIO=y
|
||||
CONFIG_COMMON_RESET_HI6220=y
|
||||
CONFIG_PHY_RCAR_GEN3_USB2=y
|
||||
CONFIG_PHY_HI6220_USB=y
|
||||
CONFIG_PHY_XGENE=y
|
||||
CONFIG_ARM_SCPI_PROTOCOL=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_FANOTIFY=y
|
||||
|
@ -264,6 +275,7 @@ CONFIG_CUSE=y
|
|||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
CONFIG_EFIVAR_FS=y
|
||||
CONFIG_SQUASHFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
|
|
|
@ -124,7 +124,9 @@
|
|||
#define VTCR_EL2_SL0_LVL1 (1 << 6)
|
||||
#define VTCR_EL2_T0SZ_MASK 0x3f
|
||||
#define VTCR_EL2_T0SZ_40B 24
|
||||
#define VTCR_EL2_VS 19
|
||||
#define VTCR_EL2_VS_SHIFT 19
|
||||
#define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT)
|
||||
#define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT)
|
||||
|
||||
/*
|
||||
* We configure the Stage-2 page tables to always restrict the IPA space to be
|
||||
|
|
|
@ -27,7 +27,6 @@
|
|||
#include <asm/kvm.h>
|
||||
#include <asm/kvm_asm.h>
|
||||
#include <asm/kvm_mmio.h>
|
||||
#include <asm/kvm_perf_event.h>
|
||||
|
||||
#define __KVM_HAVE_ARCH_INTC_INITIALIZED
|
||||
|
||||
|
|
|
@ -21,7 +21,6 @@
|
|||
#include <linux/compiler.h>
|
||||
#include <linux/kvm_host.h>
|
||||
#include <asm/kvm_mmu.h>
|
||||
#include <asm/kvm_perf_event.h>
|
||||
#include <asm/sysreg.h>
|
||||
|
||||
#define __hyp_text __section(.hyp.text) notrace
|
||||
|
|
|
@ -1,68 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2012 ARM Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_KVM_PERF_EVENT_H
|
||||
#define __ASM_KVM_PERF_EVENT_H
|
||||
|
||||
#define ARMV8_PMU_MAX_COUNTERS 32
|
||||
#define ARMV8_PMU_COUNTER_MASK (ARMV8_PMU_MAX_COUNTERS - 1)
|
||||
|
||||
/*
|
||||
* Per-CPU PMCR: config reg
|
||||
*/
|
||||
#define ARMV8_PMU_PMCR_E (1 << 0) /* Enable all counters */
|
||||
#define ARMV8_PMU_PMCR_P (1 << 1) /* Reset all counters */
|
||||
#define ARMV8_PMU_PMCR_C (1 << 2) /* Cycle counter reset */
|
||||
#define ARMV8_PMU_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
|
||||
#define ARMV8_PMU_PMCR_X (1 << 4) /* Export to ETM */
|
||||
#define ARMV8_PMU_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
|
||||
/* Determines which bit of PMCCNTR_EL0 generates an overflow */
|
||||
#define ARMV8_PMU_PMCR_LC (1 << 6)
|
||||
#define ARMV8_PMU_PMCR_N_SHIFT 11 /* Number of counters supported */
|
||||
#define ARMV8_PMU_PMCR_N_MASK 0x1f
|
||||
#define ARMV8_PMU_PMCR_MASK 0x7f /* Mask for writable bits */
|
||||
|
||||
/*
|
||||
* PMOVSR: counters overflow flag status reg
|
||||
*/
|
||||
#define ARMV8_PMU_OVSR_MASK 0xffffffff /* Mask for writable bits */
|
||||
#define ARMV8_PMU_OVERFLOWED_MASK ARMV8_PMU_OVSR_MASK
|
||||
|
||||
/*
|
||||
* PMXEVTYPER: Event selection reg
|
||||
*/
|
||||
#define ARMV8_PMU_EVTYPE_MASK 0xc80003ff /* Mask for writable bits */
|
||||
#define ARMV8_PMU_EVTYPE_EVENT 0x3ff /* Mask for EVENT bits */
|
||||
|
||||
#define ARMV8_PMU_EVTYPE_EVENT_SW_INCR 0 /* Software increment event */
|
||||
|
||||
/*
|
||||
* Event filters for PMUv3
|
||||
*/
|
||||
#define ARMV8_PMU_EXCLUDE_EL1 (1 << 31)
|
||||
#define ARMV8_PMU_EXCLUDE_EL0 (1 << 30)
|
||||
#define ARMV8_PMU_INCLUDE_EL2 (1 << 27)
|
||||
|
||||
/*
|
||||
* PMUSERENR: user enable reg
|
||||
*/
|
||||
#define ARMV8_PMU_USERENR_MASK 0xf /* Mask for writable bits */
|
||||
#define ARMV8_PMU_USERENR_EN (1 << 0) /* PMU regs can be accessed at EL0 */
|
||||
#define ARMV8_PMU_USERENR_SW (1 << 1) /* PMSWINC can be written at EL0 */
|
||||
#define ARMV8_PMU_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */
|
||||
#define ARMV8_PMU_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */
|
||||
|
||||
#endif
|
|
@ -1 +1,5 @@
|
|||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
#define CONFIG_CPU_ENDIAN_BE8 CONFIG_CPU_BIG_ENDIAN
|
||||
#endif
|
||||
|
||||
#include <../../arm/include/asm/opcodes.h>
|
||||
|
|
|
@ -17,6 +17,53 @@
|
|||
#ifndef __ASM_PERF_EVENT_H
|
||||
#define __ASM_PERF_EVENT_H
|
||||
|
||||
#define ARMV8_PMU_MAX_COUNTERS 32
|
||||
#define ARMV8_PMU_COUNTER_MASK (ARMV8_PMU_MAX_COUNTERS - 1)
|
||||
|
||||
/*
|
||||
* Per-CPU PMCR: config reg
|
||||
*/
|
||||
#define ARMV8_PMU_PMCR_E (1 << 0) /* Enable all counters */
|
||||
#define ARMV8_PMU_PMCR_P (1 << 1) /* Reset all counters */
|
||||
#define ARMV8_PMU_PMCR_C (1 << 2) /* Cycle counter reset */
|
||||
#define ARMV8_PMU_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
|
||||
#define ARMV8_PMU_PMCR_X (1 << 4) /* Export to ETM */
|
||||
#define ARMV8_PMU_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
|
||||
#define ARMV8_PMU_PMCR_LC (1 << 6) /* Overflow on 64 bit cycle counter */
|
||||
#define ARMV8_PMU_PMCR_N_SHIFT 11 /* Number of counters supported */
|
||||
#define ARMV8_PMU_PMCR_N_MASK 0x1f
|
||||
#define ARMV8_PMU_PMCR_MASK 0x7f /* Mask for writable bits */
|
||||
|
||||
/*
|
||||
* PMOVSR: counters overflow flag status reg
|
||||
*/
|
||||
#define ARMV8_PMU_OVSR_MASK 0xffffffff /* Mask for writable bits */
|
||||
#define ARMV8_PMU_OVERFLOWED_MASK ARMV8_PMU_OVSR_MASK
|
||||
|
||||
/*
|
||||
* PMXEVTYPER: Event selection reg
|
||||
*/
|
||||
#define ARMV8_PMU_EVTYPE_MASK 0xc800ffff /* Mask for writable bits */
|
||||
#define ARMV8_PMU_EVTYPE_EVENT 0xffff /* Mask for EVENT bits */
|
||||
|
||||
#define ARMV8_PMU_EVTYPE_EVENT_SW_INCR 0 /* Software increment event */
|
||||
|
||||
/*
|
||||
* Event filters for PMUv3
|
||||
*/
|
||||
#define ARMV8_PMU_EXCLUDE_EL1 (1 << 31)
|
||||
#define ARMV8_PMU_EXCLUDE_EL0 (1 << 30)
|
||||
#define ARMV8_PMU_INCLUDE_EL2 (1 << 27)
|
||||
|
||||
/*
|
||||
* PMUSERENR: user enable reg
|
||||
*/
|
||||
#define ARMV8_PMU_USERENR_MASK 0xf /* Mask for writable bits */
|
||||
#define ARMV8_PMU_USERENR_EN (1 << 0) /* PMU regs can be accessed at EL0 */
|
||||
#define ARMV8_PMU_USERENR_SW (1 << 1) /* PMSWINC can be written at EL0 */
|
||||
#define ARMV8_PMU_USERENR_CR (1 << 2) /* Cycle counter can be read at EL0 */
|
||||
#define ARMV8_PMU_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */
|
||||
|
||||
#ifdef CONFIG_PERF_EVENTS
|
||||
struct pt_regs;
|
||||
extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
|
||||
|
|
|
@ -141,6 +141,9 @@
|
|||
#define ID_AA64MMFR1_VMIDBITS_SHIFT 4
|
||||
#define ID_AA64MMFR1_HADBS_SHIFT 0
|
||||
|
||||
#define ID_AA64MMFR1_VMIDBITS_8 0
|
||||
#define ID_AA64MMFR1_VMIDBITS_16 2
|
||||
|
||||
/* id_aa64mmfr2 */
|
||||
#define ID_AA64MMFR2_UAO_SHIFT 4
|
||||
|
||||
|
|
|
@ -20,6 +20,7 @@
|
|||
*/
|
||||
|
||||
#include <asm/irq_regs.h>
|
||||
#include <asm/perf_event.h>
|
||||
#include <asm/virt.h>
|
||||
|
||||
#include <linux/of.h>
|
||||
|
@ -384,9 +385,6 @@ static const struct attribute_group *armv8_pmuv3_attr_groups[] = {
|
|||
#define ARMV8_IDX_COUNTER_LAST(cpu_pmu) \
|
||||
(ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
|
||||
|
||||
#define ARMV8_MAX_COUNTERS 32
|
||||
#define ARMV8_COUNTER_MASK (ARMV8_MAX_COUNTERS - 1)
|
||||
|
||||
/*
|
||||
* ARMv8 low level PMU access
|
||||
*/
|
||||
|
@ -395,40 +393,7 @@ static const struct attribute_group *armv8_pmuv3_attr_groups[] = {
|
|||
* Perf Event to low level counters mapping
|
||||
*/
|
||||
#define ARMV8_IDX_TO_COUNTER(x) \
|
||||
(((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK)
|
||||
|
||||
/*
|
||||
* Per-CPU PMCR: config reg
|
||||
*/
|
||||
#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */
|
||||
#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */
|
||||
#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */
|
||||
#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
|
||||
#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */
|
||||
#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
|
||||
#define ARMV8_PMCR_LC (1 << 6) /* Overflow on 64 bit cycle counter */
|
||||
#define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */
|
||||
#define ARMV8_PMCR_N_MASK 0x1f
|
||||
#define ARMV8_PMCR_MASK 0x7f /* Mask for writable bits */
|
||||
|
||||
/*
|
||||
* PMOVSR: counters overflow flag status reg
|
||||
*/
|
||||
#define ARMV8_OVSR_MASK 0xffffffff /* Mask for writable bits */
|
||||
#define ARMV8_OVERFLOWED_MASK ARMV8_OVSR_MASK
|
||||
|
||||
/*
|
||||
* PMXEVTYPER: Event selection reg
|
||||
*/
|
||||
#define ARMV8_EVTYPE_MASK 0xc800ffff /* Mask for writable bits */
|
||||
#define ARMV8_EVTYPE_EVENT 0xffff /* Mask for EVENT bits */
|
||||
|
||||
/*
|
||||
* Event filters for PMUv3
|
||||
*/
|
||||
#define ARMV8_EXCLUDE_EL1 (1 << 31)
|
||||
#define ARMV8_EXCLUDE_EL0 (1 << 30)
|
||||
#define ARMV8_INCLUDE_EL2 (1 << 27)
|
||||
(((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
|
||||
|
||||
static inline u32 armv8pmu_pmcr_read(void)
|
||||
{
|
||||
|
@ -439,14 +404,14 @@ static inline u32 armv8pmu_pmcr_read(void)
|
|||
|
||||
static inline void armv8pmu_pmcr_write(u32 val)
|
||||
{
|
||||
val &= ARMV8_PMCR_MASK;
|
||||
val &= ARMV8_PMU_PMCR_MASK;
|
||||
isb();
|
||||
asm volatile("msr pmcr_el0, %0" :: "r" (val));
|
||||
}
|
||||
|
||||
static inline int armv8pmu_has_overflowed(u32 pmovsr)
|
||||
{
|
||||
return pmovsr & ARMV8_OVERFLOWED_MASK;
|
||||
return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
|
||||
}
|
||||
|
||||
static inline int armv8pmu_counter_valid(struct arm_pmu *cpu_pmu, int idx)
|
||||
|
@ -512,7 +477,7 @@ static inline void armv8pmu_write_counter(struct perf_event *event, u32 value)
|
|||
static inline void armv8pmu_write_evtype(int idx, u32 val)
|
||||
{
|
||||
if (armv8pmu_select_counter(idx) == idx) {
|
||||
val &= ARMV8_EVTYPE_MASK;
|
||||
val &= ARMV8_PMU_EVTYPE_MASK;
|
||||
asm volatile("msr pmxevtyper_el0, %0" :: "r" (val));
|
||||
}
|
||||
}
|
||||
|
@ -558,7 +523,7 @@ static inline u32 armv8pmu_getreset_flags(void)
|
|||
asm volatile("mrs %0, pmovsclr_el0" : "=r" (value));
|
||||
|
||||
/* Write to clear flags */
|
||||
value &= ARMV8_OVSR_MASK;
|
||||
value &= ARMV8_PMU_OVSR_MASK;
|
||||
asm volatile("msr pmovsclr_el0, %0" :: "r" (value));
|
||||
|
||||
return value;
|
||||
|
@ -696,7 +661,7 @@ static void armv8pmu_start(struct arm_pmu *cpu_pmu)
|
|||
|
||||
raw_spin_lock_irqsave(&events->pmu_lock, flags);
|
||||
/* Enable all counters */
|
||||
armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMCR_E);
|
||||
armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
|
||||
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
||||
}
|
||||
|
||||
|
@ -707,7 +672,7 @@ static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
|
|||
|
||||
raw_spin_lock_irqsave(&events->pmu_lock, flags);
|
||||
/* Disable all counters */
|
||||
armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMCR_E);
|
||||
armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
|
||||
raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
|
||||
}
|
||||
|
||||
|
@ -717,7 +682,7 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
|
|||
int idx;
|
||||
struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
|
||||
struct hw_perf_event *hwc = &event->hw;
|
||||
unsigned long evtype = hwc->config_base & ARMV8_EVTYPE_EVENT;
|
||||
unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
|
||||
|
||||
/* Always place a cycle counter into the cycle counter. */
|
||||
if (evtype == ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES) {
|
||||
|
@ -754,11 +719,11 @@ static int armv8pmu_set_event_filter(struct hw_perf_event *event,
|
|||
attr->exclude_kernel != attr->exclude_hv)
|
||||
return -EINVAL;
|
||||
if (attr->exclude_user)
|
||||
config_base |= ARMV8_EXCLUDE_EL0;
|
||||
config_base |= ARMV8_PMU_EXCLUDE_EL0;
|
||||
if (!is_kernel_in_hyp_mode() && attr->exclude_kernel)
|
||||
config_base |= ARMV8_EXCLUDE_EL1;
|
||||
config_base |= ARMV8_PMU_EXCLUDE_EL1;
|
||||
if (!attr->exclude_hv)
|
||||
config_base |= ARMV8_INCLUDE_EL2;
|
||||
config_base |= ARMV8_PMU_INCLUDE_EL2;
|
||||
|
||||
/*
|
||||
* Install the filter into config_base as this is used to
|
||||
|
@ -784,35 +749,36 @@ static void armv8pmu_reset(void *info)
|
|||
* Initialize & Reset PMNC. Request overflow interrupt for
|
||||
* 64 bit cycle counter but cheat in armv8pmu_write_counter().
|
||||
*/
|
||||
armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C | ARMV8_PMCR_LC);
|
||||
armv8pmu_pmcr_write(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C |
|
||||
ARMV8_PMU_PMCR_LC);
|
||||
}
|
||||
|
||||
static int armv8_pmuv3_map_event(struct perf_event *event)
|
||||
{
|
||||
return armpmu_map_event(event, &armv8_pmuv3_perf_map,
|
||||
&armv8_pmuv3_perf_cache_map,
|
||||
ARMV8_EVTYPE_EVENT);
|
||||
ARMV8_PMU_EVTYPE_EVENT);
|
||||
}
|
||||
|
||||
static int armv8_a53_map_event(struct perf_event *event)
|
||||
{
|
||||
return armpmu_map_event(event, &armv8_a53_perf_map,
|
||||
&armv8_a53_perf_cache_map,
|
||||
ARMV8_EVTYPE_EVENT);
|
||||
ARMV8_PMU_EVTYPE_EVENT);
|
||||
}
|
||||
|
||||
static int armv8_a57_map_event(struct perf_event *event)
|
||||
{
|
||||
return armpmu_map_event(event, &armv8_a57_perf_map,
|
||||
&armv8_a57_perf_cache_map,
|
||||
ARMV8_EVTYPE_EVENT);
|
||||
ARMV8_PMU_EVTYPE_EVENT);
|
||||
}
|
||||
|
||||
static int armv8_thunder_map_event(struct perf_event *event)
|
||||
{
|
||||
return armpmu_map_event(event, &armv8_thunder_perf_map,
|
||||
&armv8_thunder_perf_cache_map,
|
||||
ARMV8_EVTYPE_EVENT);
|
||||
ARMV8_PMU_EVTYPE_EVENT);
|
||||
}
|
||||
|
||||
static void armv8pmu_read_num_pmnc_events(void *info)
|
||||
|
@ -820,7 +786,7 @@ static void armv8pmu_read_num_pmnc_events(void *info)
|
|||
int *nb_cnt = info;
|
||||
|
||||
/* Read the nb of CNTx counters supported from PMNC */
|
||||
*nb_cnt = (armv8pmu_pmcr_read() >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
|
||||
*nb_cnt = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
|
||||
|
||||
/* Add the CPU cycles counter */
|
||||
*nb_cnt += 1;
|
||||
|
|
|
@ -36,8 +36,10 @@ void __hyp_text __init_stage2_translation(void)
|
|||
* Read the VMIDBits bits from ID_AA64MMFR1_EL1 and set the VS
|
||||
* bit in VTCR_EL2.
|
||||
*/
|
||||
tmp = (read_sysreg(id_aa64mmfr1_el1) >> 4) & 0xf;
|
||||
val |= (tmp == 2) ? VTCR_EL2_VS : 0;
|
||||
tmp = (read_sysreg(id_aa64mmfr1_el1) >> ID_AA64MMFR1_VMIDBITS_SHIFT) & 0xf;
|
||||
val |= (tmp == ID_AA64MMFR1_VMIDBITS_16) ?
|
||||
VTCR_EL2_VS_16BIT :
|
||||
VTCR_EL2_VS_8BIT;
|
||||
|
||||
write_sysreg(val, vtcr_el2);
|
||||
}
|
||||
|
|
|
@ -261,7 +261,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
|
|||
au1x_dma_chan_t *cp;
|
||||
|
||||
/*
|
||||
* We do the intialization on the first channel allocation.
|
||||
* We do the initialization on the first channel allocation.
|
||||
* We have to wait because of the interrupt handler initialization
|
||||
* which can't be done successfully during board set up.
|
||||
*/
|
||||
|
@ -964,7 +964,7 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
|
|||
dp->dscr_source1 = dscr->dscr_source1;
|
||||
dp->dscr_cmd1 = dscr->dscr_cmd1;
|
||||
nbytes = dscr->dscr_cmd1;
|
||||
/* Allow the caller to specifiy if an interrupt is generated */
|
||||
/* Allow the caller to specify if an interrupt is generated */
|
||||
dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
|
||||
dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
|
||||
ctp->chan_ptr->ddma_dbell = 0;
|
||||
|
|
|
@ -503,15 +503,15 @@ int __init db1000_dev_setup(void)
|
|||
if (board == BCSR_WHOAMI_DB1500) {
|
||||
c0 = AU1500_GPIO2_INT;
|
||||
c1 = AU1500_GPIO5_INT;
|
||||
d0 = AU1500_GPIO0_INT;
|
||||
d1 = AU1500_GPIO3_INT;
|
||||
d0 = 0; /* GPIO number, NOT irq! */
|
||||
d1 = 3; /* GPIO number, NOT irq! */
|
||||
s0 = AU1500_GPIO1_INT;
|
||||
s1 = AU1500_GPIO4_INT;
|
||||
} else if (board == BCSR_WHOAMI_DB1100) {
|
||||
c0 = AU1100_GPIO2_INT;
|
||||
c1 = AU1100_GPIO5_INT;
|
||||
d0 = AU1100_GPIO0_INT;
|
||||
d1 = AU1100_GPIO3_INT;
|
||||
d0 = 0; /* GPIO number, NOT irq! */
|
||||
d1 = 3; /* GPIO number, NOT irq! */
|
||||
s0 = AU1100_GPIO1_INT;
|
||||
s1 = AU1100_GPIO4_INT;
|
||||
|
||||
|
@ -545,15 +545,15 @@ int __init db1000_dev_setup(void)
|
|||
} else if (board == BCSR_WHOAMI_DB1000) {
|
||||
c0 = AU1000_GPIO2_INT;
|
||||
c1 = AU1000_GPIO5_INT;
|
||||
d0 = AU1000_GPIO0_INT;
|
||||
d1 = AU1000_GPIO3_INT;
|
||||
d0 = 0; /* GPIO number, NOT irq! */
|
||||
d1 = 3; /* GPIO number, NOT irq! */
|
||||
s0 = AU1000_GPIO1_INT;
|
||||
s1 = AU1000_GPIO4_INT;
|
||||
platform_add_devices(db1000_devs, ARRAY_SIZE(db1000_devs));
|
||||
} else if ((board == BCSR_WHOAMI_PB1500) ||
|
||||
(board == BCSR_WHOAMI_PB1500R2)) {
|
||||
c0 = AU1500_GPIO203_INT;
|
||||
d0 = AU1500_GPIO201_INT;
|
||||
d0 = 1; /* GPIO number, NOT irq! */
|
||||
s0 = AU1500_GPIO202_INT;
|
||||
twosocks = 0;
|
||||
flashsize = 64;
|
||||
|
@ -566,7 +566,7 @@ int __init db1000_dev_setup(void)
|
|||
*/
|
||||
} else if (board == BCSR_WHOAMI_PB1100) {
|
||||
c0 = AU1100_GPIO11_INT;
|
||||
d0 = AU1100_GPIO9_INT;
|
||||
d0 = 9; /* GPIO number, NOT irq! */
|
||||
s0 = AU1100_GPIO10_INT;
|
||||
twosocks = 0;
|
||||
flashsize = 64;
|
||||
|
@ -583,7 +583,6 @@ int __init db1000_dev_setup(void)
|
|||
} else
|
||||
return 0; /* unknown board, no further dev setup to do */
|
||||
|
||||
irq_set_irq_type(d0, IRQ_TYPE_EDGE_BOTH);
|
||||
irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW);
|
||||
|
||||
|
@ -597,7 +596,6 @@ int __init db1000_dev_setup(void)
|
|||
c0, d0, /*s0*/0, 0, 0);
|
||||
|
||||
if (twosocks) {
|
||||
irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH);
|
||||
irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW);
|
||||
irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW);
|
||||
|
||||
|
|
|
@ -514,7 +514,7 @@ static void __init db1550_devices(void)
|
|||
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
|
||||
AU1000_PCMCIA_IO_PHYS_ADDR,
|
||||
AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
|
||||
AU1550_GPIO3_INT, AU1550_GPIO0_INT,
|
||||
AU1550_GPIO3_INT, 0,
|
||||
/*AU1550_GPIO21_INT*/0, 0, 0);
|
||||
|
||||
db1x_register_pcmcia_socket(
|
||||
|
@ -524,7 +524,7 @@ static void __init db1550_devices(void)
|
|||
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
|
||||
AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
|
||||
AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
|
||||
AU1550_GPIO5_INT, AU1550_GPIO1_INT,
|
||||
AU1550_GPIO5_INT, 1,
|
||||
/*AU1550_GPIO22_INT*/0, 0, 1);
|
||||
|
||||
platform_device_register(&db1550_nand_dev);
|
||||
|
|
|
@ -26,8 +26,7 @@
|
|||
#include "common.h"
|
||||
|
||||
#define AR71XX_BASE_FREQ 40000000
|
||||
#define AR724X_BASE_FREQ 5000000
|
||||
#define AR913X_BASE_FREQ 5000000
|
||||
#define AR724X_BASE_FREQ 40000000
|
||||
|
||||
static struct clk *clks[3];
|
||||
static struct clk_onecell_data clk_data = {
|
||||
|
@ -103,8 +102,8 @@ static void __init ar724x_clocks_init(void)
|
|||
div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
|
||||
freq = div * ref_rate;
|
||||
|
||||
div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
|
||||
freq *= div;
|
||||
div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
|
||||
freq /= div;
|
||||
|
||||
cpu_rate = freq;
|
||||
|
||||
|
@ -123,39 +122,6 @@ static void __init ar724x_clocks_init(void)
|
|||
clk_add_alias("uart", NULL, "ahb", NULL);
|
||||
}
|
||||
|
||||
static void __init ar913x_clocks_init(void)
|
||||
{
|
||||
unsigned long ref_rate;
|
||||
unsigned long cpu_rate;
|
||||
unsigned long ddr_rate;
|
||||
unsigned long ahb_rate;
|
||||
u32 pll;
|
||||
u32 freq;
|
||||
u32 div;
|
||||
|
||||
ref_rate = AR913X_BASE_FREQ;
|
||||
pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);
|
||||
|
||||
div = ((pll >> AR913X_PLL_FB_SHIFT) & AR913X_PLL_FB_MASK);
|
||||
freq = div * ref_rate;
|
||||
|
||||
cpu_rate = freq;
|
||||
|
||||
div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;
|
||||
ddr_rate = freq / div;
|
||||
|
||||
div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;
|
||||
ahb_rate = cpu_rate / div;
|
||||
|
||||
ath79_add_sys_clkdev("ref", ref_rate);
|
||||
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
|
||||
clk_add_alias("wdt", NULL, "ahb", NULL);
|
||||
clk_add_alias("uart", NULL, "ahb", NULL);
|
||||
}
|
||||
|
||||
static void __init ar933x_clocks_init(void)
|
||||
{
|
||||
unsigned long ref_rate;
|
||||
|
@ -443,10 +409,8 @@ void __init ath79_clocks_init(void)
|
|||
{
|
||||
if (soc_is_ar71xx())
|
||||
ar71xx_clocks_init();
|
||||
else if (soc_is_ar724x())
|
||||
else if (soc_is_ar724x() || soc_is_ar913x())
|
||||
ar724x_clocks_init();
|
||||
else if (soc_is_ar913x())
|
||||
ar913x_clocks_init();
|
||||
else if (soc_is_ar933x())
|
||||
ar933x_clocks_init();
|
||||
else if (soc_is_ar934x())
|
||||
|
|
|
@ -714,11 +714,11 @@ void bcm47xx_sprom_register_fallbacks(void)
|
|||
{
|
||||
#if defined(CONFIG_BCM47XX_SSB)
|
||||
if (ssb_arch_register_fallback_sprom(&bcm47xx_get_sprom_ssb))
|
||||
pr_warn("Failed to registered ssb SPROM handler\n");
|
||||
pr_warn("Failed to register ssb SPROM handler\n");
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BCM47XX_BCMA)
|
||||
if (bcma_arch_register_fallback_sprom(&bcm47xx_get_sprom_bcma))
|
||||
pr_warn("Failed to registered bcma SPROM handler\n");
|
||||
pr_warn("Failed to register bcma SPROM handler\n");
|
||||
#endif
|
||||
}
|
||||
|
|
|
@ -39,10 +39,11 @@ vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM) += $(obj)/uart-prom.o
|
|||
vmlinuzobjs-$(CONFIG_MIPS_ALCHEMY) += $(obj)/uart-alchemy.o
|
||||
endif
|
||||
|
||||
vmlinuzobjs-$(CONFIG_KERNEL_XZ) += $(obj)/ashldi3.o
|
||||
vmlinuzobjs-$(CONFIG_KERNEL_XZ) += $(obj)/ashldi3.o $(obj)/bswapsi.o
|
||||
|
||||
$(obj)/ashldi3.o: KBUILD_CFLAGS += -I$(srctree)/arch/mips/lib
|
||||
$(obj)/ashldi3.c: $(srctree)/arch/mips/lib/ashldi3.c
|
||||
extra-y += ashldi3.c bswapsi.c
|
||||
$(obj)/ashldi3.o $(obj)/bswapsi.o: KBUILD_CFLAGS += -I$(srctree)/arch/mips/lib
|
||||
$(obj)/ashldi3.c $(obj)/bswapsi.c: $(obj)/%.c: $(srctree)/arch/mips/lib/%.c
|
||||
$(call cmd,shipped)
|
||||
|
||||
targets := $(notdir $(vmlinuzobjs-y))
|
||||
|
|
|
@ -82,7 +82,7 @@
|
|||
};
|
||||
|
||||
gisb-arb@400000 {
|
||||
compatible = "brcm,bcm7400-gisb-arb";
|
||||
compatible = "brcm,bcm7435-gisb-arb";
|
||||
reg = <0x400000 0xdc>;
|
||||
native-endian;
|
||||
interrupt-parent = <&sun_l2_intc>;
|
||||
|
|
|
@ -83,7 +83,7 @@
|
|||
};
|
||||
|
||||
pll: pll-controller@18050000 {
|
||||
compatible = "qca,ar9132-ppl",
|
||||
compatible = "qca,ar9132-pll",
|
||||
"qca,ar9130-pll";
|
||||
reg = <0x18050000 0x20>;
|
||||
|
||||
|
|
|
@ -18,7 +18,7 @@
|
|||
reg = <0x0 0x2000000>;
|
||||
};
|
||||
|
||||
extosc: oscillator {
|
||||
extosc: ref {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <40000000>;
|
||||
|
|
|
@ -68,7 +68,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
|
|||
gmx_rx_int_en.s.pause_drp = 1;
|
||||
/* Skipping gmx_rx_int_en.s.reserved_16_18 */
|
||||
/*gmx_rx_int_en.s.ifgerr = 1; */
|
||||
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
|
||||
/*gmx_rx_int_en.s.coldet = 1; // Collision detect */
|
||||
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
|
||||
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
|
||||
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
|
||||
|
@ -89,7 +89,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
|
|||
/*gmx_rx_int_en.s.phy_spd = 1; */
|
||||
/*gmx_rx_int_en.s.phy_link = 1; */
|
||||
/*gmx_rx_int_en.s.ifgerr = 1; */
|
||||
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
|
||||
/*gmx_rx_int_en.s.coldet = 1; // Collision detect */
|
||||
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
|
||||
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
|
||||
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
|
||||
|
@ -112,7 +112,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
|
|||
/*gmx_rx_int_en.s.phy_spd = 1; */
|
||||
/*gmx_rx_int_en.s.phy_link = 1; */
|
||||
/*gmx_rx_int_en.s.ifgerr = 1; */
|
||||
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
|
||||
/*gmx_rx_int_en.s.coldet = 1; // Collision detect */
|
||||
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
|
||||
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
|
||||
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
|
||||
|
@ -134,7 +134,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
|
|||
/*gmx_rx_int_en.s.phy_spd = 1; */
|
||||
/*gmx_rx_int_en.s.phy_link = 1; */
|
||||
/*gmx_rx_int_en.s.ifgerr = 1; */
|
||||
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
|
||||
/*gmx_rx_int_en.s.coldet = 1; // Collision detect */
|
||||
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
|
||||
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
|
||||
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
|
||||
|
@ -156,7 +156,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
|
|||
/*gmx_rx_int_en.s.phy_spd = 1; */
|
||||
/*gmx_rx_int_en.s.phy_link = 1; */
|
||||
/*gmx_rx_int_en.s.ifgerr = 1; */
|
||||
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
|
||||
/*gmx_rx_int_en.s.coldet = 1; // Collision detect */
|
||||
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
|
||||
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
|
||||
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
|
||||
|
@ -179,7 +179,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
|
|||
/*gmx_rx_int_en.s.phy_spd = 1; */
|
||||
/*gmx_rx_int_en.s.phy_link = 1; */
|
||||
/*gmx_rx_int_en.s.ifgerr = 1; */
|
||||
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
|
||||
/*gmx_rx_int_en.s.coldet = 1; // Collision detect */
|
||||
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
|
||||
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
|
||||
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
|
||||
|
@ -209,7 +209,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
|
|||
gmx_rx_int_en.s.pause_drp = 1;
|
||||
/* Skipping gmx_rx_int_en.s.reserved_16_18 */
|
||||
/*gmx_rx_int_en.s.ifgerr = 1; */
|
||||
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
|
||||
/*gmx_rx_int_en.s.coldet = 1; // Collision detect */
|
||||
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
|
||||
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
|
||||
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
|
||||
|
|
|
@ -189,7 +189,7 @@ void cvmx_pko_initialize_global(void)
|
|||
/*
|
||||
* Set the size of the PKO command buffers to an odd number of
|
||||
* 64bit words. This allows the normal two word send to stay
|
||||
* aligned and never span a comamnd word buffer.
|
||||
* aligned and never span a command word buffer.
|
||||
*/
|
||||
config.u64 = 0;
|
||||
config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
|
||||
|
|
|
@ -331,7 +331,7 @@ static int octeon_update_boot_vector(unsigned int cpu)
|
|||
}
|
||||
|
||||
if (!(avail_coremask & (1 << coreid))) {
|
||||
/* core not available, assume, that catched by simple-executive */
|
||||
/* core not available, assume, that caught by simple-executive */
|
||||
cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
|
||||
cvmx_write_csr(CVMX_CIU_PP_RST, 0);
|
||||
}
|
||||
|
|
|
@ -17,13 +17,12 @@ CONFIG_IKCONFIG=y
|
|||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CGROUP_DEVICE=y
|
||||
CONFIG_CPUSETS=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_MEMCG=y
|
||||
CONFIG_MEMCG_KMEM=y
|
||||
CONFIG_CGROUP_SCHED=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CPUSETS=y
|
||||
CONFIG_CGROUP_DEVICE=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_NAMESPACES=y
|
||||
CONFIG_USER_NS=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
|
@ -52,6 +51,11 @@ CONFIG_DEVTMPFS=y
|
|||
# CONFIG_ALLOW_DEV_COREDUMP is not set
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_CMA_SIZE_MBYTES=32
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_JZ4780=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_FASTMAP=y
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_VENDOR_ARC is not set
|
||||
# CONFIG_NET_CADENCE is not set
|
||||
|
@ -103,7 +107,7 @@ CONFIG_PROC_KCORE=y
|
|||
# CONFIG_PROC_PAGE_MONITOR is not set
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
CONFIG_UBIFS_FS=y
|
||||
# CONFIG_NETWORK_FILESYSTEMS is not set
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
|
|
|
@ -5,7 +5,7 @@
|
|||
* Written by Ralf Baechle and Andreas Busse, modified for DECstation
|
||||
* support by Paul Antoine and Harald Koerfgen.
|
||||
*
|
||||
* completly rewritten:
|
||||
* completely rewritten:
|
||||
* Copyright (C) 1998 Harald Koerfgen
|
||||
*
|
||||
* Rewritten extensively for controller-driven IRQ support
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
* PROM library functions for acquiring/using memory descriptors given to us
|
||||
* from the ARCS firmware. This is only used when CONFIG_ARC_MEMORY is set
|
||||
* because on some machines like SGI IP27 the ARC memory configuration data
|
||||
* completly bogus and alternate easier to use mechanisms are available.
|
||||
* completely bogus and alternate easier to use mechanisms are available.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
|
|
|
@ -102,7 +102,7 @@ extern void cpu_probe(void);
|
|||
extern void cpu_report(void);
|
||||
|
||||
extern const char *__cpu_name[];
|
||||
#define cpu_name_string() __cpu_name[smp_processor_id()]
|
||||
#define cpu_name_string() __cpu_name[raw_smp_processor_id()]
|
||||
|
||||
struct seq_file;
|
||||
struct notifier_block;
|
||||
|
|
|
@ -141,7 +141,7 @@ octeon_main_processor:
|
|||
.endm
|
||||
|
||||
/*
|
||||
* Do SMP slave processor setup necessary before we can savely execute C code.
|
||||
* Do SMP slave processor setup necessary before we can safely execute C code.
|
||||
*/
|
||||
.macro smp_slave_setup
|
||||
.endm
|
||||
|
|
|
@ -16,7 +16,7 @@
|
|||
.endm
|
||||
|
||||
/*
|
||||
* Do SMP slave processor setup necessary before we can savely execute C code.
|
||||
* Do SMP slave processor setup necessary before we can safely execute C code.
|
||||
*/
|
||||
.macro smp_slave_setup
|
||||
.endm
|
||||
|
|
|
@ -11,7 +11,7 @@
|
|||
#define __ASM_MACH_IP27_IRQ_H
|
||||
|
||||
/*
|
||||
* A hardwired interrupt number is completly stupid for this system - a
|
||||
* A hardwired interrupt number is completely stupid for this system - a
|
||||
* large configuration might have thousands if not tenthousands of
|
||||
* interrupts.
|
||||
*/
|
||||
|
|
|
@ -81,7 +81,7 @@
|
|||
.endm
|
||||
|
||||
/*
|
||||
* Do SMP slave processor setup necessary before we can savely execute C code.
|
||||
* Do SMP slave processor setup necessary before we can safely execute C code.
|
||||
*/
|
||||
.macro smp_slave_setup
|
||||
GET_NASID_ASM t1
|
||||
|
|
|
@ -27,7 +27,7 @@ enum jz_gpio_function {
|
|||
|
||||
/*
|
||||
Usually a driver for a SoC component has to request several gpio pins and
|
||||
configure them as funcion pins.
|
||||
configure them as function pins.
|
||||
jz_gpio_bulk_request can be used to ease this process.
|
||||
Usually one would do something like:
|
||||
|
||||
|
|
|
@ -28,7 +28,7 @@ extern void __iomem *mips_cm_l2sync_base;
|
|||
* This function returns the physical base address of the Coherence Manager
|
||||
* global control block, or 0 if no Coherence Manager is present. It provides
|
||||
* a default implementation which reads the CMGCRBase register where available,
|
||||
* and may be overriden by platforms which determine this address in a
|
||||
* and may be overridden by platforms which determine this address in a
|
||||
* different way by defining a function with the same prototype except for the
|
||||
* name mips_cm_phys_base (without underscores).
|
||||
*/
|
||||
|
|
|
@ -79,7 +79,7 @@ struct r2_decoder_table {
|
|||
};
|
||||
|
||||
|
||||
extern void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
|
||||
extern void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
|
||||
const char *str);
|
||||
|
||||
#ifndef CONFIG_MIPSR2_TO_R6_EMULATOR
|
||||
|
|
|
@ -33,7 +33,7 @@
|
|||
/* Packet buffers */
|
||||
#define CVMX_FPA_PACKET_POOL (0)
|
||||
#define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE
|
||||
/* Work queue entrys */
|
||||
/* Work queue entries */
|
||||
#define CVMX_FPA_WQE_POOL (1)
|
||||
#define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE
|
||||
/* PKO queue command buffers */
|
||||
|
|
|
@ -189,7 +189,7 @@ static inline uint64_t cvmx_ptr_to_phys(void *ptr)
|
|||
static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
|
||||
{
|
||||
if (sizeof(void *) == 8) {
|
||||
/* Just set the top bit, avoiding any TLB uglyness */
|
||||
/* Just set the top bit, avoiding any TLB ugliness */
|
||||
return CASTPTR(void,
|
||||
CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
|
||||
physical_address));
|
||||
|
|
|
@ -269,16 +269,16 @@ typedef struct bridge_err_cmdword_s {
|
|||
union {
|
||||
u32 cmd_word;
|
||||
struct {
|
||||
u32 didn:4, /* Destination ID */
|
||||
sidn:4, /* Source ID */
|
||||
pactyp:4, /* Packet type */
|
||||
tnum:5, /* Trans Number */
|
||||
coh:1, /* Coh Transacti */
|
||||
ds:2, /* Data size */
|
||||
gbr:1, /* GBR enable */
|
||||
vbpm:1, /* VBPM message */
|
||||
u32 didn:4, /* Destination ID */
|
||||
sidn:4, /* Source ID */
|
||||
pactyp:4, /* Packet type */
|
||||
tnum:5, /* Trans Number */
|
||||
coh:1, /* Coh Transaction */
|
||||
ds:2, /* Data size */
|
||||
gbr:1, /* GBR enable */
|
||||
vbpm:1, /* VBPM message */
|
||||
error:1, /* Error occurred */
|
||||
barr:1, /* Barrier op */
|
||||
barr:1, /* Barrier op */
|
||||
rsvd:8;
|
||||
} berr_st;
|
||||
} berr_un;
|
||||
|
|
|
@ -147,7 +147,7 @@ struct hpc3_ethregs {
|
|||
#define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */
|
||||
#define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */
|
||||
#define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */
|
||||
#define HPC3_EPCFG_TST 0x1000 /* Diagnistic ram test feature bit */
|
||||
#define HPC3_EPCFG_TST 0x1000 /* Diagnostic ram test feature bit */
|
||||
|
||||
u32 _unused2[0x1000/4 - 8]; /* padding */
|
||||
|
||||
|
|
|
@ -144,7 +144,7 @@ struct linux_tinfo {
|
|||
struct linux_vdirent {
|
||||
ULONG namelen;
|
||||
unsigned char attr;
|
||||
char fname[32]; /* XXX imperical, should be a define */
|
||||
char fname[32]; /* XXX empirical, should be a define */
|
||||
};
|
||||
|
||||
/* Other stuff for files. */
|
||||
|
@ -179,7 +179,7 @@ struct linux_finfo {
|
|||
enum linux_devtypes dtype;
|
||||
unsigned long namelen;
|
||||
unsigned char attr;
|
||||
char name[32]; /* XXX imperical, should be define */
|
||||
char name[32]; /* XXX empirical, should be define */
|
||||
};
|
||||
|
||||
/* This describes the vector containing function pointers to the ARC
|
||||
|
|
|
@ -355,7 +355,7 @@ struct ioc3_etxd {
|
|||
#define SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */
|
||||
#define SSCR_RESET 0x80000000 /* reset DMA channels */
|
||||
|
||||
/* all producer/comsumer pointers are the same bitfield */
|
||||
/* all producer/consumer pointers are the same bitfield */
|
||||
#define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */
|
||||
#define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */
|
||||
#define PROD_CONS_PTR_OFF 3
|
||||
|
|
|
@ -628,7 +628,7 @@ typedef union h1_icrbb_u {
|
|||
/*
|
||||
* Values for field imsgtype
|
||||
*/
|
||||
#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */
|
||||
#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Message from Xtalk */
|
||||
#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */
|
||||
#define IIO_ICRB_IMSGT_SN0NET 2 /* Incoming message from SN0 net */
|
||||
#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */
|
||||
|
|
|
@ -95,7 +95,7 @@ static inline bool eva_kernel_access(void)
|
|||
}
|
||||
|
||||
/*
|
||||
* Is a address valid? This does a straighforward calculation rather
|
||||
* Is a address valid? This does a straightforward calculation rather
|
||||
* than tests.
|
||||
*
|
||||
* Address valid if:
|
||||
|
|
|
@ -381,16 +381,18 @@
|
|||
#define __NR_membarrier (__NR_Linux + 358)
|
||||
#define __NR_mlock2 (__NR_Linux + 359)
|
||||
#define __NR_copy_file_range (__NR_Linux + 360)
|
||||
#define __NR_preadv2 (__NR_Linux + 361)
|
||||
#define __NR_pwritev2 (__NR_Linux + 362)
|
||||
|
||||
/*
|
||||
* Offset of the last Linux o32 flavoured syscall
|
||||
*/
|
||||
#define __NR_Linux_syscalls 360
|
||||
#define __NR_Linux_syscalls 362
|
||||
|
||||
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
|
||||
|
||||
#define __NR_O32_Linux 4000
|
||||
#define __NR_O32_Linux_syscalls 360
|
||||
#define __NR_O32_Linux_syscalls 362
|
||||
|
||||
#if _MIPS_SIM == _MIPS_SIM_ABI64
|
||||
|
||||
|
@ -719,16 +721,18 @@
|
|||
#define __NR_membarrier (__NR_Linux + 318)
|
||||
#define __NR_mlock2 (__NR_Linux + 319)
|
||||
#define __NR_copy_file_range (__NR_Linux + 320)
|
||||
#define __NR_preadv2 (__NR_Linux + 321)
|
||||
#define __NR_pwritev2 (__NR_Linux + 322)
|
||||
|
||||
/*
|
||||
* Offset of the last Linux 64-bit flavoured syscall
|
||||
*/
|
||||
#define __NR_Linux_syscalls 320
|
||||
#define __NR_Linux_syscalls 322
|
||||
|
||||
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
|
||||
|
||||
#define __NR_64_Linux 5000
|
||||
#define __NR_64_Linux_syscalls 320
|
||||
#define __NR_64_Linux_syscalls 322
|
||||
|
||||
#if _MIPS_SIM == _MIPS_SIM_NABI32
|
||||
|
||||
|
@ -1061,15 +1065,17 @@
|
|||
#define __NR_membarrier (__NR_Linux + 322)
|
||||
#define __NR_mlock2 (__NR_Linux + 323)
|
||||
#define __NR_copy_file_range (__NR_Linux + 324)
|
||||
#define __NR_preadv2 (__NR_Linux + 325)
|
||||
#define __NR_pwritev2 (__NR_Linux + 326)
|
||||
|
||||
/*
|
||||
* Offset of the last N32 flavoured syscall
|
||||
*/
|
||||
#define __NR_Linux_syscalls 324
|
||||
#define __NR_Linux_syscalls 326
|
||||
|
||||
#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
|
||||
|
||||
#define __NR_N32_Linux 6000
|
||||
#define __NR_N32_Linux_syscalls 324
|
||||
#define __NR_N32_Linux_syscalls 326
|
||||
|
||||
#endif /* _UAPI_ASM_UNISTD_H */
|
||||
|
|
|
@ -24,7 +24,7 @@ static char *cm2_tr[8] = {
|
|||
"0x04", "cpc", "0x06", "0x07"
|
||||
};
|
||||
|
||||
/* CM3 Tag ECC transation type */
|
||||
/* CM3 Tag ECC transaction type */
|
||||
static char *cm3_tr[16] = {
|
||||
[0x0] = "ReqNoData",
|
||||
[0x1] = "0x1",
|
||||
|
|
|
@ -940,42 +940,42 @@ repeat:
|
|||
switch (rt) {
|
||||
case tgei_op:
|
||||
if ((long)regs->regs[rs] >= MIPSInst_SIMM(inst))
|
||||
do_trap_or_bp(regs, 0, "TGEI");
|
||||
do_trap_or_bp(regs, 0, 0, "TGEI");
|
||||
|
||||
MIPS_R2_STATS(traps);
|
||||
|
||||
break;
|
||||
case tgeiu_op:
|
||||
if (regs->regs[rs] >= MIPSInst_UIMM(inst))
|
||||
do_trap_or_bp(regs, 0, "TGEIU");
|
||||
do_trap_or_bp(regs, 0, 0, "TGEIU");
|
||||
|
||||
MIPS_R2_STATS(traps);
|
||||
|
||||
break;
|
||||
case tlti_op:
|
||||
if ((long)regs->regs[rs] < MIPSInst_SIMM(inst))
|
||||
do_trap_or_bp(regs, 0, "TLTI");
|
||||
do_trap_or_bp(regs, 0, 0, "TLTI");
|
||||
|
||||
MIPS_R2_STATS(traps);
|
||||
|
||||
break;
|
||||
case tltiu_op:
|
||||
if (regs->regs[rs] < MIPSInst_UIMM(inst))
|
||||
do_trap_or_bp(regs, 0, "TLTIU");
|
||||
do_trap_or_bp(regs, 0, 0, "TLTIU");
|
||||
|
||||
MIPS_R2_STATS(traps);
|
||||
|
||||
break;
|
||||
case teqi_op:
|
||||
if (regs->regs[rs] == MIPSInst_SIMM(inst))
|
||||
do_trap_or_bp(regs, 0, "TEQI");
|
||||
do_trap_or_bp(regs, 0, 0, "TEQI");
|
||||
|
||||
MIPS_R2_STATS(traps);
|
||||
|
||||
break;
|
||||
case tnei_op:
|
||||
if (regs->regs[rs] != MIPSInst_SIMM(inst))
|
||||
do_trap_or_bp(regs, 0, "TNEI");
|
||||
do_trap_or_bp(regs, 0, 0, "TNEI");
|
||||
|
||||
MIPS_R2_STATS(traps);
|
||||
|
||||
|
|
|
@ -109,9 +109,10 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
|
|||
struct module *me)
|
||||
{
|
||||
Elf_Mips_Rela *rel = (void *) sechdrs[relsec].sh_addr;
|
||||
int (*handler)(struct module *me, u32 *location, Elf_Addr v);
|
||||
Elf_Sym *sym;
|
||||
u32 *location;
|
||||
unsigned int i;
|
||||
unsigned int i, type;
|
||||
Elf_Addr v;
|
||||
int res;
|
||||
|
||||
|
@ -134,9 +135,21 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab,
|
|||
return -ENOENT;
|
||||
}
|
||||
|
||||
v = sym->st_value + rel[i].r_addend;
|
||||
type = ELF_MIPS_R_TYPE(rel[i]);
|
||||
|
||||
res = reloc_handlers_rela[ELF_MIPS_R_TYPE(rel[i])](me, location, v);
|
||||
if (type < ARRAY_SIZE(reloc_handlers_rela))
|
||||
handler = reloc_handlers_rela[type];
|
||||
else
|
||||
handler = NULL;
|
||||
|
||||
if (!handler) {
|
||||
pr_err("%s: Unknown relocation type %u\n",
|
||||
me->name, type);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
v = sym->st_value + rel[i].r_addend;
|
||||
res = handler(me, location, v);
|
||||
if (res)
|
||||
return res;
|
||||
}
|
||||
|
|
|
@ -197,9 +197,10 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
|
|||
struct module *me)
|
||||
{
|
||||
Elf_Mips_Rel *rel = (void *) sechdrs[relsec].sh_addr;
|
||||
int (*handler)(struct module *me, u32 *location, Elf_Addr v);
|
||||
Elf_Sym *sym;
|
||||
u32 *location;
|
||||
unsigned int i;
|
||||
unsigned int i, type;
|
||||
Elf_Addr v;
|
||||
int res;
|
||||
|
||||
|
@ -223,9 +224,21 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
|
|||
return -ENOENT;
|
||||
}
|
||||
|
||||
v = sym->st_value;
|
||||
type = ELF_MIPS_R_TYPE(rel[i]);
|
||||
|
||||
res = reloc_handlers_rel[ELF_MIPS_R_TYPE(rel[i])](me, location, v);
|
||||
if (type < ARRAY_SIZE(reloc_handlers_rel))
|
||||
handler = reloc_handlers_rel[type];
|
||||
else
|
||||
handler = NULL;
|
||||
|
||||
if (!handler) {
|
||||
pr_err("%s: Unknown relocation type %u\n",
|
||||
me->name, type);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
v = sym->st_value;
|
||||
res = handler(me, location, v);
|
||||
if (res)
|
||||
return res;
|
||||
}
|
||||
|
|
|
@ -530,7 +530,7 @@ static void mipspmu_enable(struct pmu *pmu)
|
|||
|
||||
/*
|
||||
* MIPS performance counters can be per-TC. The control registers can
|
||||
* not be directly accessed accross CPUs. Hence if we want to do global
|
||||
* not be directly accessed across CPUs. Hence if we want to do global
|
||||
* control, we need cross CPU calls. on_each_cpu() can help us, but we
|
||||
* can not make sure this function is called with interrupts enabled. So
|
||||
* here we pause local counters and then grab a rwlock and leave the
|
||||
|
|
|
@ -472,7 +472,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
|
|||
/*
|
||||
* Disable all but self interventions. The load from COHCTL is defined
|
||||
* by the interAptiv & proAptiv SUMs as ensuring that the operation
|
||||
* resulting from the preceeding store is complete.
|
||||
* resulting from the preceding store is complete.
|
||||
*/
|
||||
uasm_i_addiu(&p, t0, zero, 1 << cpu_data[cpu].core);
|
||||
uasm_i_sw(&p, t0, 0, r_pcohctl);
|
||||
|
|
|
@ -615,7 +615,7 @@ int mips_set_process_fp_mode(struct task_struct *task, unsigned int value)
|
|||
* allows us to only worry about whether an FP mode switch is in
|
||||
* progress when FP is first used in a tasks time slice. Pretty much all
|
||||
* of the mode switch overhead can thus be confined to cases where mode
|
||||
* switches are actually occuring. That is, to here. However for the
|
||||
* switches are actually occurring. That is, to here. However for the
|
||||
* thread performing the mode switch it may take a while...
|
||||
*/
|
||||
if (num_online_cpus() > 1) {
|
||||
|
|
|
@ -596,3 +596,5 @@ EXPORT(sys_call_table)
|
|||
PTR sys_membarrier
|
||||
PTR sys_mlock2
|
||||
PTR sys_copy_file_range /* 4360 */
|
||||
PTR sys_preadv2
|
||||
PTR sys_pwritev2
|
||||
|
|
|
@ -434,4 +434,6 @@ EXPORT(sys_call_table)
|
|||
PTR sys_membarrier
|
||||
PTR sys_mlock2
|
||||
PTR sys_copy_file_range /* 5320 */
|
||||
PTR sys_preadv2
|
||||
PTR sys_pwritev2
|
||||
.size sys_call_table,.-sys_call_table
|
||||
|
|
|
@ -424,4 +424,6 @@ EXPORT(sysn32_call_table)
|
|||
PTR sys_membarrier
|
||||
PTR sys_mlock2
|
||||
PTR sys_copy_file_range
|
||||
PTR compat_sys_preadv2 /* 6325 */
|
||||
PTR compat_sys_pwritev2
|
||||
.size sysn32_call_table,.-sysn32_call_table
|
||||
|
|
|
@ -579,4 +579,6 @@ EXPORT(sys32_call_table)
|
|||
PTR sys_membarrier
|
||||
PTR sys_mlock2
|
||||
PTR sys_copy_file_range /* 4360 */
|
||||
PTR compat_sys_preadv2
|
||||
PTR compat_sys_pwritev2
|
||||
.size sys32_call_table,.-sys32_call_table
|
||||
|
|
|
@ -243,6 +243,18 @@ static int __init mips_smp_ipi_init(void)
|
|||
struct irq_domain *ipidomain;
|
||||
struct device_node *node;
|
||||
|
||||
/*
|
||||
* In some cases like qemu-malta, it is desired to try SMP with
|
||||
* a single core. Qemu-malta has no GIC, so an attempt to set any IPIs
|
||||
* would cause a BUG_ON() to be triggered since there's no ipidomain.
|
||||
*
|
||||
* Since for a single core system IPIs aren't required really, skip the
|
||||
* initialisation which should generally keep any such configurations
|
||||
* happy and only fail hard when trying to truely run SMP.
|
||||
*/
|
||||
if (cpumask_weight(cpu_possible_mask) == 1)
|
||||
return 0;
|
||||
|
||||
node = of_irq_find_parent(of_root);
|
||||
ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI);
|
||||
|
||||
|
|
|
@ -56,6 +56,7 @@
|
|||
#include <asm/pgtable.h>
|
||||
#include <asm/ptrace.h>
|
||||
#include <asm/sections.h>
|
||||
#include <asm/siginfo.h>
|
||||
#include <asm/tlbdebug.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
@ -871,7 +872,7 @@ out:
|
|||
exception_exit(prev_state);
|
||||
}
|
||||
|
||||
void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
|
||||
void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
|
||||
const char *str)
|
||||
{
|
||||
siginfo_t info = { 0 };
|
||||
|
@ -928,7 +929,13 @@ void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
|
|||
default:
|
||||
scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
|
||||
die_if_kernel(b, regs);
|
||||
force_sig(SIGTRAP, current);
|
||||
if (si_code) {
|
||||
info.si_signo = SIGTRAP;
|
||||
info.si_code = si_code;
|
||||
force_sig_info(SIGTRAP, &info, current);
|
||||
} else {
|
||||
force_sig(SIGTRAP, current);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1012,7 +1019,7 @@ asmlinkage void do_bp(struct pt_regs *regs)
|
|||
break;
|
||||
}
|
||||
|
||||
do_trap_or_bp(regs, bcode, "Break");
|
||||
do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
|
||||
|
||||
out:
|
||||
set_fs(seg);
|
||||
|
@ -1054,7 +1061,7 @@ asmlinkage void do_tr(struct pt_regs *regs)
|
|||
tcode = (opcode >> 6) & ((1 << 10) - 1);
|
||||
}
|
||||
|
||||
do_trap_or_bp(regs, tcode, "Trap");
|
||||
do_trap_or_bp(regs, tcode, 0, "Trap");
|
||||
|
||||
out:
|
||||
set_fs(seg);
|
||||
|
@ -1115,19 +1122,7 @@ no_r2_instr:
|
|||
if (unlikely(compute_return_epc(regs) < 0))
|
||||
goto out;
|
||||
|
||||
if (get_isa16_mode(regs->cp0_epc)) {
|
||||
unsigned short mmop[2] = { 0 };
|
||||
|
||||
if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
|
||||
status = SIGSEGV;
|
||||
if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
|
||||
status = SIGSEGV;
|
||||
opcode = mmop[0];
|
||||
opcode = (opcode << 16) | mmop[1];
|
||||
|
||||
if (status < 0)
|
||||
status = simulate_rdhwr_mm(regs, opcode);
|
||||
} else {
|
||||
if (!get_isa16_mode(regs->cp0_epc)) {
|
||||
if (unlikely(get_user(opcode, epc) < 0))
|
||||
status = SIGSEGV;
|
||||
|
||||
|
@ -1142,6 +1137,18 @@ no_r2_instr:
|
|||
|
||||
if (status < 0)
|
||||
status = simulate_fp(regs, opcode, old_epc, old31);
|
||||
} else if (cpu_has_mmips) {
|
||||
unsigned short mmop[2] = { 0 };
|
||||
|
||||
if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
|
||||
status = SIGSEGV;
|
||||
if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
|
||||
status = SIGSEGV;
|
||||
opcode = mmop[0];
|
||||
opcode = (opcode << 16) | mmop[1];
|
||||
|
||||
if (status < 0)
|
||||
status = simulate_rdhwr_mm(regs, opcode);
|
||||
}
|
||||
|
||||
if (status < 0)
|
||||
|
@ -1492,6 +1499,7 @@ asmlinkage void do_mdmx(struct pt_regs *regs)
|
|||
*/
|
||||
asmlinkage void do_watch(struct pt_regs *regs)
|
||||
{
|
||||
siginfo_t info = { .si_signo = SIGTRAP, .si_code = TRAP_HWBKPT };
|
||||
enum ctx_state prev_state;
|
||||
u32 cause;
|
||||
|
||||
|
@ -1512,7 +1520,7 @@ asmlinkage void do_watch(struct pt_regs *regs)
|
|||
if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
|
||||
mips_read_watch_registers();
|
||||
local_irq_enable();
|
||||
force_sig(SIGTRAP, current);
|
||||
force_sig_info(SIGTRAP, &info, current);
|
||||
} else {
|
||||
mips_clear_watch_registers();
|
||||
local_irq_enable();
|
||||
|
@ -2214,7 +2222,7 @@ void __init trap_init(void)
|
|||
|
||||
/*
|
||||
* Copy the generic exception handlers to their final destination.
|
||||
* This will be overriden later as suitable for a particular
|
||||
* This will be overridden later as suitable for a particular
|
||||
* configuration.
|
||||
*/
|
||||
set_handler(0x180, &except_vec3_generic, 0x80);
|
||||
|
|
|
@ -885,7 +885,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
|
|||
{
|
||||
union mips_instruction insn;
|
||||
unsigned long value;
|
||||
unsigned int res;
|
||||
unsigned int res, preempted;
|
||||
unsigned long origpc;
|
||||
unsigned long orig31;
|
||||
void __user *fault_addr = NULL;
|
||||
|
@ -1226,27 +1226,36 @@ static void emulate_load_store_insn(struct pt_regs *regs,
|
|||
if (!access_ok(VERIFY_READ, addr, sizeof(*fpr)))
|
||||
goto sigbus;
|
||||
|
||||
/*
|
||||
* Disable preemption to avoid a race between copying
|
||||
* state from userland, migrating to another CPU and
|
||||
* updating the hardware vector register below.
|
||||
*/
|
||||
preempt_disable();
|
||||
do {
|
||||
/*
|
||||
* If we have live MSA context keep track of
|
||||
* whether we get preempted in order to avoid
|
||||
* the register context we load being clobbered
|
||||
* by the live context as it's saved during
|
||||
* preemption. If we don't have live context
|
||||
* then it can't be saved to clobber the value
|
||||
* we load.
|
||||
*/
|
||||
preempted = test_thread_flag(TIF_USEDMSA);
|
||||
|
||||
res = __copy_from_user_inatomic(fpr, addr,
|
||||
sizeof(*fpr));
|
||||
if (res)
|
||||
goto fault;
|
||||
res = __copy_from_user_inatomic(fpr, addr,
|
||||
sizeof(*fpr));
|
||||
if (res)
|
||||
goto fault;
|
||||
|
||||
/*
|
||||
* Update the hardware register if it is in use by the
|
||||
* task in this quantum, in order to avoid having to
|
||||
* save & restore the whole vector context.
|
||||
*/
|
||||
if (test_thread_flag(TIF_USEDMSA))
|
||||
write_msa_wr(wd, fpr, df);
|
||||
|
||||
preempt_enable();
|
||||
/*
|
||||
* Update the hardware register if it is in use
|
||||
* by the task in this quantum, in order to
|
||||
* avoid having to save & restore the whole
|
||||
* vector context.
|
||||
*/
|
||||
preempt_disable();
|
||||
if (test_thread_flag(TIF_USEDMSA)) {
|
||||
write_msa_wr(wd, fpr, df);
|
||||
preempted = 0;
|
||||
}
|
||||
preempt_enable();
|
||||
} while (preempted);
|
||||
break;
|
||||
|
||||
case msa_st_op:
|
||||
|
|
|
@ -632,7 +632,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
|
|||
|
||||
kvm_debug("%s: vcpu %p, cpu: %d\n", __func__, vcpu, cpu);
|
||||
|
||||
/* Alocate new kernel and user ASIDs if needed */
|
||||
/* Allocate new kernel and user ASIDs if needed */
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
|
|
|
@ -500,7 +500,7 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
|
|||
kvm_write_c0_guest_config7(cop0, (MIPS_CONF7_WII) | (1 << 10));
|
||||
|
||||
/*
|
||||
* Setup IntCtl defaults, compatibilty mode for timer interrupts (HW5)
|
||||
* Setup IntCtl defaults, compatibility mode for timer interrupts (HW5)
|
||||
*/
|
||||
kvm_write_c0_guest_intctl(cop0, 0xFC000000);
|
||||
|
||||
|
|
|
@ -97,7 +97,7 @@ union ieee754dp ieee754dp_format(int sn, int xe, u64 xm)
|
|||
{
|
||||
assert(xm); /* we don't gen exact zeros (probably should) */
|
||||
|
||||
assert((xm >> (DP_FBITS + 1 + 3)) == 0); /* no execess */
|
||||
assert((xm >> (DP_FBITS + 1 + 3)) == 0); /* no excess */
|
||||
assert(xm & (DP_HIDDEN_BIT << 3));
|
||||
|
||||
if (xe < DP_EMIN) {
|
||||
|
@ -165,7 +165,7 @@ union ieee754dp ieee754dp_format(int sn, int xe, u64 xm)
|
|||
/* strip grs bits */
|
||||
xm >>= 3;
|
||||
|
||||
assert((xm >> (DP_FBITS + 1)) == 0); /* no execess */
|
||||
assert((xm >> (DP_FBITS + 1)) == 0); /* no excess */
|
||||
assert(xe >= DP_EMIN);
|
||||
|
||||
if (xe > DP_EMAX) {
|
||||
|
@ -198,7 +198,7 @@ union ieee754dp ieee754dp_format(int sn, int xe, u64 xm)
|
|||
ieee754_setcx(IEEE754_UNDERFLOW);
|
||||
return builddp(sn, DP_EMIN - 1 + DP_EBIAS, xm);
|
||||
} else {
|
||||
assert((xm >> (DP_FBITS + 1)) == 0); /* no execess */
|
||||
assert((xm >> (DP_FBITS + 1)) == 0); /* no excess */
|
||||
assert(xm & DP_HIDDEN_BIT);
|
||||
|
||||
return builddp(sn, xe + DP_EBIAS, xm & ~DP_HIDDEN_BIT);
|
||||
|
|
|
@ -97,7 +97,7 @@ union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
|
|||
{
|
||||
assert(xm); /* we don't gen exact zeros (probably should) */
|
||||
|
||||
assert((xm >> (SP_FBITS + 1 + 3)) == 0); /* no execess */
|
||||
assert((xm >> (SP_FBITS + 1 + 3)) == 0); /* no excess */
|
||||
assert(xm & (SP_HIDDEN_BIT << 3));
|
||||
|
||||
if (xe < SP_EMIN) {
|
||||
|
@ -163,7 +163,7 @@ union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
|
|||
/* strip grs bits */
|
||||
xm >>= 3;
|
||||
|
||||
assert((xm >> (SP_FBITS + 1)) == 0); /* no execess */
|
||||
assert((xm >> (SP_FBITS + 1)) == 0); /* no excess */
|
||||
assert(xe >= SP_EMIN);
|
||||
|
||||
if (xe > SP_EMAX) {
|
||||
|
@ -196,7 +196,7 @@ union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
|
|||
ieee754_setcx(IEEE754_UNDERFLOW);
|
||||
return buildsp(sn, SP_EMIN - 1 + SP_EBIAS, xm);
|
||||
} else {
|
||||
assert((xm >> (SP_FBITS + 1)) == 0); /* no execess */
|
||||
assert((xm >> (SP_FBITS + 1)) == 0); /* no excess */
|
||||
assert(xm & SP_HIDDEN_BIT);
|
||||
|
||||
return buildsp(sn, xe + SP_EBIAS, xm & ~SP_HIDDEN_BIT);
|
||||
|
|
|
@ -158,7 +158,7 @@ static inline int __init indy_sc_probe(void)
|
|||
return 1;
|
||||
}
|
||||
|
||||
/* XXX Check with wje if the Indy caches can differenciate between
|
||||
/* XXX Check with wje if the Indy caches can differentiate between
|
||||
writeback + invalidate and just invalidate. */
|
||||
static struct bcache_ops indy_sc_ops = {
|
||||
.bc_enable = indy_sc_enable,
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
#include <asm/cpu.h>
|
||||
#include <asm/cpu-type.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/hazards.h>
|
||||
#include <asm/mmu_context.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/tlb.h>
|
||||
|
@ -486,6 +487,10 @@ static void r4k_tlb_configure(void)
|
|||
* be set to fixed-size pages.
|
||||
*/
|
||||
write_c0_pagemask(PM_DEFAULT_MASK);
|
||||
back_to_back_c0_hazard();
|
||||
if (read_c0_pagemask() != PM_DEFAULT_MASK)
|
||||
panic("MMU doesn't support PAGE_SIZE=0x%lx", PAGE_SIZE);
|
||||
|
||||
write_c0_wired(0);
|
||||
if (current_cpu_type() == CPU_R10000 ||
|
||||
current_cpu_type() == CPU_R12000 ||
|
||||
|
|
|
@ -12,7 +12,7 @@
|
|||
* Copyright (C) 2011 MIPS Technologies, Inc.
|
||||
*
|
||||
* ... and the days got worse and worse and now you see
|
||||
* I've gone completly out of my mind.
|
||||
* I've gone completely out of my mind.
|
||||
*
|
||||
* They're coming to take me a away haha
|
||||
* they're coming to take me a away hoho hihi haha
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue