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MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT 

Commit 930beb5ac0 ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
coherent DMA because of a wrong allocation alignment.

Fixes: 930beb5ac0 ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
zero-sugar-mainline-defconfig
Thomas Bogendoerfer 2020-09-14 18:05:00 +02:00
parent baf5cb30fb
commit 564c836fd9
1 changed files with 1 additions and 0 deletions
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arch/mips/Kconfig
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@ -877,6 +877,7 @@ config SNI_RM
select I8253
select I8259
select ISA
select MIPS_L1_CACHE_SHIFT_6
select SWAP_IO_SPACE if CPU_BIG_ENDIAN
select SYS_HAS_CPU_R4X00
select SYS_HAS_CPU_R5000