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alistair23-linux
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Merge branch 'next-s3c64xx-device' into next-merged 

Conflicts:

	arch/arm/mach-s3c2440/mach-at2440evb.c
hifive-unleashed-5.1
Ben Dooks 2008-12-18 16:17:37 +00:00
parent 7f2754378f 438a5d42e0
commit 56c035c9ce
81 changed files with 4027 additions and 218 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

130
arch/arm/configs/s3c6400_defconfig
View File

@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.27
# Fri Oct 17 09:20:54 2008
# Linux kernel version: 2.6.28-rc3
# Mon Nov 3 10:10:30 2008
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@ -116,6 +116,7 @@ CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_CLASSIC_RCU=y
# CONFIG_FREEZER is not set
#
# System Type
@ -152,16 +153,17 @@ CONFIG_CLASSIC_RCU=y
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_S3C24A0 is not set
CONFIG_ARCH_S3C64XX=y
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_MSM7X00A is not set
# CONFIG_ARCH_MSM is not set
CONFIG_PLAT_S3C64XX=y
CONFIG_CPU_S3C6400_INIT=y
CONFIG_CPU_S3C6400_CLOCK=y
CONFIG_S3C64XX_SETUP_I2C0=y
CONFIG_S3C64XX_SETUP_I2C1=y
CONFIG_PLAT_S3C=y
#
@ -173,8 +175,19 @@ CONFIG_S3C_BOOT_ERROR_RESET=y
# Power management
#
CONFIG_S3C_LOWLEVEL_UART_PORT=0
CONFIG_S3C_GPIO_SPACE=0
CONFIG_S3C_GPIO_TRACK=y
CONFIG_S3C_GPIO_PULL_UPDOWN=y
CONFIG_S3C_GPIO_CFG_S3C24XX=y
CONFIG_S3C_GPIO_CFG_S3C64XX=y
CONFIG_S3C_DEV_HSMMC=y
CONFIG_S3C_DEV_HSMMC1=y
CONFIG_S3C_DEV_I2C1=y
CONFIG_CPU_S3C6410=y
CONFIG_S3C6410_SETUP_SDHCI=y
CONFIG_MACH_SMDK6410=y
CONFIG_SMDK6410_SD_CH0=y
# CONFIG_SMDK6410_SD_CH1 is not set
#
# Processor Type
@ -233,8 +246,10 @@ CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
CONFIG_UNEVICTABLE_LRU=y
CONFIG_ALIGNMENT_TRAP=y
#
@ -266,6 +281,7 @@ CONFIG_VFP=y
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_HAVE_AOUT=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
@ -356,6 +372,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_LIFEBOOK=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_APPLETOUCH is not set
@ -400,6 +417,7 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
# Non-8250 serial port support
#
CONFIG_SERIAL_SAMSUNG=y
CONFIG_SERIAL_SAMSUNG_UARTS=4
# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
CONFIG_SERIAL_S3C6400=y
@ -414,7 +432,52 @@ CONFIG_HW_RANDOM=y
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
#
# I2C Hardware Bus support
#
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
CONFIG_I2C_S3C2410=y
# CONFIG_I2C_SIMTEC is not set
#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_TAOS_EVM is not set
#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
CONFIG_AT24=y
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_PCF8575 is not set
# CONFIG_SENSORS_PCA9539 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_TPS65010 is not set
# CONFIG_SENSORS_MAX6875 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
# CONFIG_SPI is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
@ -424,6 +487,9 @@ CONFIG_GPIOLIB=y
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
@ -436,14 +502,52 @@ CONFIG_GPIOLIB=y
# CONFIG_POWER_SUPPLY is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7473 is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
@ -465,12 +569,13 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_MFD_ASIC3 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_UCB1400_CORE is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM8350_I2C is not set
#
# Multimedia devices
@ -546,6 +651,7 @@ CONFIG_SDIO_UART=y
# MMC/SD/SDIO Host Controller Drivers
#
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S3C=y
# CONFIG_MEMSTICK is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_NEW_LEDS is not set
@ -691,11 +797,17 @@ CONFIG_FRAME_POINTER=y
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_HAVE_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
# CONFIG_FTRACE is not set
CONFIG_HAVE_FUNCTION_TRACER=y
#
# Tracers
#
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_CONTEXT_SWITCH_TRACER is not set
# CONFIG_BOOT_TRACER is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set

34
arch/arm/mach-s3c2410/include/mach/gpio-core.h 100644
View File

@ -0,0 +1,34 @@
/* arch/arm/mach-s3c24100/include/mach/gpio-core.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C2410 - GPIO core support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_CORE_H
#define __ASM_ARCH_GPIO_CORE_H __FILE__
#include <plat/gpio-core.h>
#include <mach/regs-gpio.h>
extern struct s3c_gpio_chip s3c24xx_gpios[];
static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
{
struct s3c_gpio_chip *chip;
if (pin > S3C2410_GPG10)
return NULL;
chip = &s3c24xx_gpios[pin/32];
return (S3C2410_GPIO_OFFSET(pin) > chip->chip.ngpio) ? chip : NULL;
}
#endif /* __ASM_ARCH_GPIO_CORE_H */

2
arch/arm/mach-s3c2410/include/mach/irqs.h
View File

@ -134,6 +134,8 @@
#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
#define IRQ_HSMMC0 IRQ_S3C2443_HSMMC
#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15)
#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16)

3
arch/arm/mach-s3c2410/include/mach/map.h
View File

@ -92,7 +92,6 @@
#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
#define S3C24XX_PA_IIC S3C2410_PA_IIC
#define S3C24XX_PA_IIS S3C2410_PA_IIS
#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
#define S3C24XX_PA_RTC S3C2410_PA_RTC
@ -101,6 +100,8 @@
#define S3C24XX_PA_SDI S3C2410_PA_SDI
#define S3C24XX_PA_NAND S3C2410_PA_NAND
#define S3C_PA_IIC S3C2410_PA_IIC
#define S3C_PA_UART S3C24XX_PA_UART
#define S3C_PA_HSMMC0 S3C2443_PA_HSMMC
#endif /* __ASM_ARCH_MAP_H */

4
arch/arm/mach-s3c2410/mach-amlm5900.c
View File

@ -52,6 +52,7 @@
#include <mach/regs-lcd.h>
#include <mach/regs-gpio.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
@ -150,7 +151,7 @@ static struct platform_device *amlm5900_devices[] __initdata = {
#endif
&s3c_device_adc,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_usb,
&s3c_device_rtc,
&s3c_device_usbgadget,
@ -233,6 +234,7 @@ static void __init amlm5900_init(void)
#ifdef CONFIG_FB_S3C2410
s3c24xx_fb_set_platdata(&amlm5900_fb_info);
#endif
s3c_i2c0_set_platdata(NULL);
platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices));
}

7
arch/arm/mach-s3c2410/mach-bast.c
View File

@ -406,7 +406,7 @@ static struct platform_device bast_sio = {
* standard 100KHz i2c bus frequency
*/
static struct s3c2410_platform_i2c bast_i2c_info = {
static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
.flags = 0,
.slave_addr = 0x10,
.bus_freq = 100*1000,
@ -553,7 +553,7 @@ static struct platform_device *bast_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_rtc,
&s3c_device_nand,
&bast_device_dm9k,
@ -588,7 +588,8 @@ static void __init bast_map_io(void)
s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
s3c_device_nand.dev.platform_data = &bast_nand_info;
s3c_device_i2c.dev.platform_data = &bast_i2c_info;
s3c_i2c0_set_platdata(&bast_i2c_info);
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
s3c24xx_init_clocks(0);

4
arch/arm/mach-s3c2410/mach-h1940.c
View File

@ -39,6 +39,7 @@
#include <mach/h1940-latch.h>
#include <mach/fb.h>
#include <plat/udc.h>
#include <plat/iic.h>
#include <plat/clock.h>
#include <plat/devs.h>
@ -184,7 +185,7 @@ static struct platform_device *h1940_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usbgadget,
&s3c_device_leds,
@ -216,6 +217,7 @@ static void __init h1940_init(void)
s3c24xx_fb_set_platdata(&h1940_fb_info);
s3c24xx_udc_set_platdata(&h1940_udc_cfg);
s3c_i2c0_set_platdata(NULL);
/* Turn off suspend on both USB ports, and switch the
* selectable USB port to USB device mode. */

6
arch/arm/mach-s3c2410/mach-n30.c
View File

@ -320,7 +320,7 @@ static struct s3c2410fb_mach_info n30_fb_info __initdata = {
static struct platform_device *n30_devices[] __initdata = {
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usb,
&s3c_device_usbgadget,
@ -332,7 +332,7 @@ static struct platform_device *n30_devices[] __initdata = {
static struct platform_device *n35_devices[] __initdata = {
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usbgadget,
&n35_button_device,
@ -501,7 +501,7 @@ static void __init n30_init_irq(void)
static void __init n30_init(void)
{
s3c24xx_fb_set_platdata(&n30_fb_info);
s3c_device_i2c.dev.platform_data = &n30_i2ccfg;
s3c_device_i2c0.dev.platform_data = &n30_i2ccfg;
s3c24xx_udc_set_platdata(&n30_udc_cfg);
/* Turn off suspend on both USB ports, and switch the

4
arch/arm/mach-s3c2410/mach-otom.c
View File

@ -35,6 +35,7 @@
#include <plat/s3c2410.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/iic.h>
#include <plat/cpu.h>
static struct map_desc otom11_iodesc[] __initdata = {
@ -94,7 +95,7 @@ static struct platform_device *otom11_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_rtc,
&otom_device_nor,
@ -109,6 +110,7 @@ static void __init otom11_map_io(void)
static void __init otom11_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices));
}

4
arch/arm/mach-s3c2410/mach-qt2410.c
View File

@ -54,6 +54,7 @@
#include <plat/udc.h>
#include <mach/spi.h>
#include <mach/spi-gpio.h>
#include <plat/iic.h>
#include <plat/common-smdk.h>
#include <plat/devs.h>
@ -247,7 +248,7 @@ static struct platform_device *qt2410_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_sdi,
&s3c_device_usbgadget,
@ -349,6 +350,7 @@ static void __init qt2410_machine_init(void)
s3c2410_gpio_setpin(S3C2410_GPB0, 1);
s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
s3c_i2c0_set_platdata(NULL);
s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);

4
arch/arm/mach-s3c2410/mach-smdk2410.c
View File

@ -47,6 +47,7 @@
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
@ -89,7 +90,7 @@ static struct platform_device *smdk2410_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
};
@ -102,6 +103,7 @@ static void __init smdk2410_map_io(void)
static void __init smdk2410_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(smdk2410_devices, ARRAY_SIZE(smdk2410_devices));
smdk_machine_init();
}

4
arch/arm/mach-s3c2410/mach-tct_hammer.c
View File

@ -45,6 +45,7 @@
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
@ -127,7 +128,7 @@ static struct s3c2410_uartcfg tct_hammer_uartcfgs[] = {
static struct platform_device *tct_hammer_devices[] __initdata = {
&s3c_device_adc,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_usb,
&s3c_device_rtc,
&s3c_device_usbgadget,
@ -146,6 +147,7 @@ static void __init tct_hammer_map_io(void)
static void __init tct_hammer_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices));
}

4
arch/arm/mach-s3c2410/mach-vr1000.c
View File

@ -47,6 +47,7 @@
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#include <plat/iic.h>
#include "usb-simtec.h"
#include "nor-simtec.h"
@ -334,7 +335,7 @@ static struct platform_device *vr1000_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_adc,
&serial_device,
&vr1000_dm9k0,
@ -384,6 +385,7 @@ static void __init vr1000_map_io(void)
static void __init vr1000_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices));
i2c_register_board_info(0, vr1000_i2c_devs,

9
arch/arm/mach-s3c2412/mach-jive.c
View File

@ -53,6 +53,7 @@
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/udc.h>
#include <plat/iic.h>
static struct map_desc jive_iodesc[] __initdata = {
};
@ -452,14 +453,14 @@ static struct spi_board_info __initdata jive_spi_devs[] = {
/* I2C bus and device configuration. */
static struct s3c2410_platform_i2c jive_i2c_cfg = {
static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
.max_freq = 80 * 1000,
.bus_freq = 50 * 1000,
.flags = S3C_IICFLG_FILTER,
.sda_delay = 2,
};
static struct i2c_board_info jive_i2c_devs[] = {
static struct i2c_board_info jive_i2c_devs[] __initdata = {
[0] = {
I2C_BOARD_INFO("lis302dl", 0x1c),
.irq = IRQ_EINT14,
@ -472,7 +473,7 @@ static struct platform_device *jive_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_rtc,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_lcd,
&jive_device_lcdspi,
&jive_device_wm8750,
@ -665,7 +666,7 @@ static void __init jive_machine_init(void)
spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
s3c_device_i2c.dev.platform_data = &jive_i2c_cfg;
s3c_i2c0_set_platdata(&jive_i2c_cfg);
i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
pm_power_off = jive_power_off;

4
arch/arm/mach-s3c2412/mach-smdk2413.c
View File

@ -38,6 +38,7 @@
#include <mach/idle.h>
#include <plat/udc.h>
#include <plat/iic.h>
#include <mach/fb.h>
#include <plat/s3c2410.h>
@ -105,7 +106,7 @@ static struct platform_device *smdk2413_devices[] __initdata = {
&s3c_device_usb,
//&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_usbgadget,
};
@ -142,6 +143,7 @@ static void __init smdk2413_machine_init(void)
s3c24xx_udc_set_platdata(&smdk2413_udc_cfg);
s3c_i2c0_set_platdata(NULL);
platform_add_devices(smdk2413_devices, ARRAY_SIZE(smdk2413_devices));
smdk_machine_init();

4
arch/arm/mach-s3c2412/mach-vstms.c
View File

@ -39,6 +39,7 @@
#include <mach/idle.h>
#include <mach/fb.h>
#include <plat/iic.h>
#include <plat/nand.h>
#include <plat/s3c2410.h>
@ -122,7 +123,7 @@ static struct s3c2410_platform_nand vstms_nand_info = {
static struct platform_device *vstms_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_rtc,
&s3c_device_nand,
@ -151,6 +152,7 @@ static void __init vstms_map_io(void)
static void __init vstms_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices));
}

4
arch/arm/mach-s3c2440/mach-anubis.c
View File

@ -40,6 +40,7 @@
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <plat/nand.h>
#include <plat/iic.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
@ -409,7 +410,7 @@ static struct platform_device *anubis_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_wdt,
&s3c_device_adc,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_rtc,
&s3c_device_nand,
&anubis_device_ide0,
@ -473,6 +474,7 @@ static void __init anubis_map_io(void)
static void __init anubis_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
i2c_register_board_info(0, anubis_i2c_devs,

5
arch/arm/mach-s3c2440/mach-at2440evb.c
View File

@ -37,6 +37,7 @@
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <plat/nand.h>
#include <plat/iic.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
@ -205,7 +206,7 @@ static struct platform_device *at2440evb_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_wdt,
&s3c_device_adc,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_rtc,
&s3c_device_nand,
&s3c_device_sdi,
@ -227,6 +228,8 @@ static void __init at2440evb_map_io(void)
static void __init at2440evb_init(void)
{
s3c24xx_fb_set_platdata(&at2440evb_fb_info);
s3c_i2c0_set_platdata(NULL);
platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
}

4
arch/arm/mach-s3c2440/mach-nexcoder.c
View File

@ -37,6 +37,7 @@
//#include <asm/debug-ll.h>
#include <mach/regs-gpio.h>
#include <plat/regs-serial.h>
#include <plat/iic.h>
#include <plat/s3c2410.h>
#include <plat/s3c2440.h>
@ -107,7 +108,7 @@ static struct platform_device *nexcoder_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_rtc,
&s3c_device_camif,
@ -142,6 +143,7 @@ static void __init nexcoder_map_io(void)
static void __init nexcoder_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(nexcoder_devices, ARRAY_SIZE(nexcoder_devices));
};

5
arch/arm/mach-s3c2440/mach-osiris.c
View File

@ -38,6 +38,7 @@
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <plat/nand.h>
#include <plat/iic.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
@ -335,7 +336,7 @@ static struct i2c_board_info osiris_i2c_devs[] __initdata = {
/* Standard Osiris devices */
static struct platform_device *osiris_devices[] __initdata = {
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_wdt,
&s3c_device_nand,
&osiris_pcmcia,
@ -398,6 +399,8 @@ static void __init osiris_init(void)
sysdev_class_register(&osiris_pm_sysclass);
sysdev_register(&osiris_pm_sysdev);
s3c_i2c0_set_platdata(NULL);
i2c_register_board_info(0, osiris_i2c_devs,
ARRAY_SIZE(osiris_i2c_devs));

2
arch/arm/mach-s3c2440/mach-rx3715.c
View File

@ -179,7 +179,7 @@ static struct platform_device *rx3715_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
&s3c_device_nand,
};

4
arch/arm/mach-s3c2440/mach-smdk2440.c
View File

@ -37,6 +37,7 @@
#include <mach/idle.h>
#include <mach/fb.h>
#include <plat/iic.h>
#include <plat/s3c2410.h>
#include <plat/s3c2440.h>
@ -152,7 +153,7 @@ static struct platform_device *smdk2440_devices[] __initdata = {
&s3c_device_usb,
&s3c_device_lcd,
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_i2c0,
&s3c_device_iis,
};
@ -166,6 +167,7 @@ static void __init smdk2440_map_io(void)
static void __init smdk2440_machine_init(void)
{
s3c24xx_fb_set_platdata(&smdk2440_fb_info);
s3c_i2c0_set_platdata(NULL);
platform_add_devices(smdk2440_devices, ARRAY_SIZE(smdk2440_devices));
smdk_machine_init();

1
arch/arm/mach-s3c2443/Kconfig
View File

@ -24,6 +24,7 @@ config MACH_SMDK2443
bool "SMDK2443"
select CPU_S3C2443
select MACH_SMDK
select S3C_DEV_HSMMC
help
Say Y here if you are using an SMDK2443

6
arch/arm/mach-s3c2443/mach-smdk2443.c
View File

@ -37,6 +37,7 @@
#include <mach/idle.h>
#include <mach/fb.h>
#include <plat/iic.h>
#include <plat/s3c2410.h>
#include <plat/s3c2440.h>
@ -103,8 +104,8 @@ static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = {
static struct platform_device *smdk2443_devices[] __initdata = {
&s3c_device_wdt,
&s3c_device_i2c,
&s3c_device_hsmmc,
&s3c_device_i2c0,
&s3c_device_hsmmc0,
};
static void __init smdk2443_map_io(void)
@ -116,6 +117,7 @@ static void __init smdk2443_map_io(void)
static void __init smdk2443_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices));
smdk_machine_init();
}

2
arch/arm/mach-s3c24a0/include/mach/map.h
View File

@ -71,7 +71,6 @@
#define S3C24XX_PA_TIMER S3C24A0_PA_TIMER
#define S3C24XX_PA_USBDEV S3C24A0_PA_USBDEV
#define S3C24XX_PA_WATCHDOG S3C24A0_PA_WATCHDOG
#define S3C24XX_PA_IIC S3C24A0_PA_IIC
#define S3C24XX_PA_IIS S3C24A0_PA_IIS
#define S3C24XX_PA_GPIO S3C24A0_PA_GPIO
#define S3C24XX_PA_RTC S3C24A0_PA_RTC
@ -81,5 +80,6 @@
#define S3C24XX_PA_NAND S3C24A0_PA_NAND
#define S3C_PA_UART S3C24A0_PA_UART
#define S3C_PA_IIC S3C24A0_PA_IIC
#endif /* __ASM_ARCH_24A0_MAP_H */

21
arch/arm/mach-s3c6400/include/mach/gpio-core.h 100644
View File

@ -0,0 +1,21 @@
/* arch/arm/mach-s3c6400/include/mach/gpio-core.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX - GPIO core support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_CORE_H
#define __ASM_ARCH_GPIO_CORE_H __FILE__
/* currently we just include the platform support */
#include <plat/gpio-core.h>
#endif /* __ASM_ARCH_GPIO_CORE_H */

76
arch/arm/mach-s3c6400/include/mach/gpio.h
View File

@ -17,6 +17,80 @@
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
#define ARCH_NR_GPIOS 188
/* GPIO bank sizes */
#define S3C64XX_GPIO_A_NR (8)
#define S3C64XX_GPIO_B_NR (7)
#define S3C64XX_GPIO_C_NR (8)
#define S3C64XX_GPIO_D_NR (5)
#define S3C64XX_GPIO_E_NR (5)
#define S3C64XX_GPIO_F_NR (16)
#define S3C64XX_GPIO_G_NR (7)
#define S3C64XX_GPIO_H_NR (10)
#define S3C64XX_GPIO_I_NR (16)
#define S3C64XX_GPIO_J_NR (12)
#define S3C64XX_GPIO_K_NR (16)
#define S3C64XX_GPIO_L_NR (15)
#define S3C64XX_GPIO_M_NR (6)
#define S3C64XX_GPIO_N_NR (16)
#define S3C64XX_GPIO_O_NR (16)
#define S3C64XX_GPIO_P_NR (15)
#define S3C64XX_GPIO_Q_NR (9)
/* GPIO bank numbes */
/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
* space for debugging purposes so that any accidental
* change from one gpio bank to another can be caught.
*/
#define S3C64XX_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
enum s3c_gpio_number {
S3C64XX_GPIO_A_START = 0,
S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A),
S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B),
S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C),
S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D),
S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E),
S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F),
S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G),
S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H),
S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I),
S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J),
S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K),
S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L),
S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M),
S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N),
S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O),
S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P),
};
/* S3C64XX GPIO number definitions. */
#define S3C64XX_GPA(_nr) (S3C64XX_GPIO_A_START + (_nr))
#define S3C64XX_GPB(_nr) (S3C64XX_GPIO_B_START + (_nr))
#define S3C64XX_GPC(_nr) (S3C64XX_GPIO_C_START + (_nr))
#define S3C64XX_GPD(_nr) (S3C64XX_GPIO_D_START + (_nr))
#define S3C64XX_GPE(_nr) (S3C64XX_GPIO_E_START + (_nr))
#define S3C64XX_GPF(_nr) (S3C64XX_GPIO_F_START + (_nr))
#define S3C64XX_GPG(_nr) (S3C64XX_GPIO_G_START + (_nr))
#define S3C64XX_GPH(_nr) (S3C64XX_GPIO_H_START + (_nr))
#define S3C64XX_GPI(_nr) (S3C64XX_GPIO_I_START + (_nr))
#define S3C64XX_GPJ(_nr) (S3C64XX_GPIO_J_START + (_nr))
#define S3C64XX_GPK(_nr) (S3C64XX_GPIO_K_START + (_nr))
#define S3C64XX_GPL(_nr) (S3C64XX_GPIO_L_START + (_nr))
#define S3C64XX_GPM(_nr) (S3C64XX_GPIO_M_START + (_nr))
#define S3C64XX_GPN(_nr) (S3C64XX_GPIO_N_START + (_nr))
#define S3C64XX_GPO(_nr) (S3C64XX_GPIO_O_START + (_nr))
#define S3C64XX_GPP(_nr) (S3C64XX_GPIO_P_START + (_nr))
#define S3C64XX_GPQ(_nr) (S3C64XX_GPIO_Q_START + (_nr))
/* the end of the S3C64XX specific gpios */
#define S3C64XX_GPIO_END (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
#define S3C_GPIO_END S3C64XX_GPIO_END
/* define the number of gpios we need to the one after the GPQ() range */
#define ARCH_NR_GPIOS (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
#include <asm-generic/gpio.h>

15
arch/arm/mach-s3c6400/include/mach/map.h
View File

@ -17,6 +17,12 @@
#include <plat/map-base.h>
/* HSMMC units */
#define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
#define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
#define S3C64XX_PA_HSMMC1 S3C64XX_PA_HSMMC(1)
#define S3C64XX_PA_HSMMC2 S3C64XX_PA_HSMMC(2)
#define S3C_PA_UART (0x7F005000)
#define S3C_PA_UART0 (S3C_PA_UART + 0x00)
#define S3C_PA_UART1 (S3C_PA_UART + 0x400)
@ -32,8 +38,11 @@
#define S3C_VA_UART2 S3C_VA_UARTx(2)
#define S3C_VA_UART3 S3C_VA_UARTx(3)
#define S3C64XX_PA_FB (0x77100000)
#define S3C64XX_PA_SYSCON (0x7E00F000)
#define S3C64XX_PA_TIMER (0x7F006000)
#define S3C64XX_PA_IIC0 (0x7F004000)
#define S3C64XX_PA_IIC1 (0x7F00F000)
#define S3C64XX_PA_GPIO (0x7F008000)
#define S3C64XX_VA_GPIO S3C_ADDR(0x00500000)
@ -49,5 +58,11 @@
/* compatibiltiy defines. */
#define S3C_PA_TIMER S3C64XX_PA_TIMER
#define S3C_PA_HSMMC0 S3C64XX_PA_HSMMC0
#define S3C_PA_HSMMC1 S3C64XX_PA_HSMMC1
#define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2
#define S3C_PA_IIC S3C64XX_PA_IIC0
#define S3C_PA_IIC1 S3C64XX_PA_IIC1
#define S3C_PA_FB S3C64XX_PA_FB
#endif /* __ASM_ARCH_6400_MAP_H */

259
arch/arm/mach-s3c6400/include/mach/regs-fb.h 100644
View File

@ -0,0 +1,259 @@
/* arch/arm/mach-s3c6400/include/mach/regs-fb.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C64XX - new-style framebuffer register definitions
*
* This is the register set for the new style framebuffer interface
* found from the S3C2443 onwards and specifically the S3C64XX series
* S3C6400 and S3C6410.
*
* The file contains the cpu specific items which change between whichever
* architecture is selected. See <plat/regs-fb.h> for the core definitions
* that are the same.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* include the core definitions here, in case we really do need to
* override them at a later date.
*/
#include <plat/regs-fb.h>
#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
#define VIDCON1_FSTATUS_EVEN (1 << 15)
/* Video timing controls */
#define VIDTCON0 (0x10)
#define VIDTCON1 (0x14)
#define VIDTCON2 (0x18)
/* Window position controls */
#define WINCON(_win) (0x20 + ((_win) * 4))
/* OSD1 and OSD4 do not have register D */
#define VIDOSD_A(_win) (0x40 + ((_win) * 16))
#define VIDOSD_B(_win) (0x44 + ((_win) * 16))
#define VIDOSD_C(_win) (0x48 + ((_win) * 16))
#define VIDOSD_D(_win) (0x4C + ((_win) * 16))
/* Video buffer addresses */
#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
#define VIDINTCON0 (0x130)
#define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4))
/* WINCONx */
#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
#define WINCONx_CSCWIDTH_SHIFT (26)
#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
#define WINCONx_ENLOCAL (1 << 22)
#define WINCONx_BUFSTATUS (1 << 21)
#define WINCONx_BUFSEL (1 << 20)
#define WINCONx_BUFAUTOEN (1 << 19)
#define WINCONx_YCbCr (1 << 13)
#define WINCON1_LOCALSEL_CAMIF (1 << 23)
#define WINCON2_LOCALSEL_CAMIF (1 << 23)
#define WINCON2_BLD_PIX (1 << 6)
#define WINCON2_ALPHA_SEL (1 << 1)
#define WINCON2_BPPMODE_MASK (0xf << 2)
#define WINCON2_BPPMODE_SHIFT (2)
#define WINCON2_BPPMODE_1BPP (0x0 << 2)
#define WINCON2_BPPMODE_2BPP (0x1 << 2)
#define WINCON2_BPPMODE_4BPP (0x2 << 2)
#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
#define WINCON3_BLD_PIX (1 << 6)
#define WINCON3_ALPHA_SEL (1 << 1)
#define WINCON3_BPPMODE_MASK (0xf << 2)
#define WINCON3_BPPMODE_SHIFT (2)
#define WINCON3_BPPMODE_1BPP (0x0 << 2)
#define WINCON3_BPPMODE_2BPP (0x1 << 2)
#define WINCON3_BPPMODE_4BPP (0x2 << 2)
#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
#define DITHMODE (0x170)
#define WINxMAP(_win) (0x180 + ((_win) * 4))
#define DITHMODE_R_POS_MASK (0x3 << 5)
#define DITHMODE_R_POS_SHIFT (5)
#define DITHMODE_R_POS_8BIT (0x0 << 5)
#define DITHMODE_R_POS_6BIT (0x1 << 5)
#define DITHMODE_R_POS_5BIT (0x2 << 5)
#define DITHMODE_G_POS_MASK (0x3 << 3)
#define DITHMODE_G_POS_SHIFT (3)
#define DITHMODE_G_POS_8BIT (0x0 << 3)
#define DITHMODE_G_POS_6BIT (0x1 << 3)
#define DITHMODE_G_POS_5BIT (0x2 << 3)
#define DITHMODE_B_POS_MASK (0x3 << 1)
#define DITHMODE_B_POS_SHIFT (1)
#define DITHMODE_B_POS_8BIT (0x0 << 1)
#define DITHMODE_B_POS_6BIT (0x1 << 1)
#define DITHMODE_B_POS_5BIT (0x2 << 1)
#define DITHMODE_DITH_EN (1 << 0)
#define WPALCON (0x1A0)
#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
/* Palette registers */
#define WIN2_PAL(_entry) (0x300 + ((_entry) * 2))
#define WIN3_PAL(_entry) (0x320 + ((_entry) * 2))
#define WIN4_PAL(_entry) (0x340 + ((_entry) * 2))
#define WIN0_PAL(_entry) (0x400 + ((_entry) * 4))
#define WIN1_PAL(_entry) (0x800 + ((_entry) * 4))
/* system specific implementation code for palette sizes, and other
* information that changes depending on which architecture is being
* compiled.
*/
/* return true if window _win has OSD register D */
#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
{
if (win < 2)
return 256;
if (win < 4)
return 16;
if (win == 4)
return 4;
BUG(); /* shouldn't get here */
}
static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
{
/* all windows can do 1/2 bpp */
if ((bpp == 25 || bpp == 19) && win == 0)
return 0; /* win 0 does not have 19 or 25bpp modes */
if (bpp == 4 && win == 4)
return 0;
if (bpp == 8 && (win >= 3))
return 0; /* win 3/4 cannot do 8bpp in any mode */
return 1;
}
static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
{
switch (window) {
case 0: return WIN0_PAL(reg);
case 1: return WIN1_PAL(reg);
case 2: return WIN2_PAL(reg);
case 3: return WIN3_PAL(reg);
case 4: return WIN4_PAL(reg);
}
BUG();
}
static inline int s3c_fb_pal_is16(unsigned int window)
{
return window > 1;
}
struct s3c_fb_palette {
struct fb_bitfield r;
struct fb_bitfield g;
struct fb_bitfield b;
struct fb_bitfield a;
};
static inline void s3c_fb_init_palette(unsigned int window,
struct s3c_fb_palette *palette)
{
if (window < 2) {
/* Windows 0/1 are 8/8/8 or A/8/8/8 */
palette->r.offset = 16;
palette->r.length = 8;
palette->g.offset = 8;
palette->g.length = 8;
palette->b.offset = 0;
palette->b.length = 8;
} else {
/* currently we assume RGB 5/6/5 */
palette->r.offset = 11;
palette->r.length = 5;
palette->g.offset = 5;
palette->g.length = 6;
palette->b.offset = 0;
palette->b.length = 5;
}
}
/* Notes on per-window bpp settings
*
* Value Win0 Win1 Win2 Win3 Win 4
* 0000 1(P) 1(P) 1(P) 1(P) 1(P)
* 0001 2(P) 2(P) 2(P) 2(P) 2(P)
* 0010 4(P) 4(P) 4(P) 4(P) -none-
* 0011 8(P) 8(P) -none- -none- -none-
* 0100 -none- 8(A232) 8(A232) -none- -none-
* 0101 16(565) 16(565) 16(565) 16(565) 16(565)
* 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
* 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
* 1000 18(666) 18(666) 18(666) 18(666) 18(666)
* 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
* 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
* 1011 24(888) 24(888) 24(888) 24(888) 24(888)
* 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
* 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
* 1110 -none- -none- -none- -none- -none-
* 1111 -none- -none- -none- -none- -none-
*/

41
arch/arm/mach-s3c6410/Kconfig
View File

@ -14,8 +14,49 @@ config CPU_S3C6410
help
Enable S3C6410 CPU support
config S3C6410_SETUP_SDHCI
bool
help
Internal helper functions for S3C6410 based SDHCI systems
config MACH_SMDK6410
bool "SMDK6410"
select CPU_S3C6410
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_I2C1
select S3C_DEV_FB
select S3C6410_SETUP_SDHCI
select S3C64XX_SETUP_I2C1
select S3C64XX_SETUP_FB_24BPP
help
Machine support for the Samsung SMDK6410
# At least some of the SMDK6410s were shipped with the card detect
# for the MMC/SD slots connected to the same input. This means that
# either the boards need to be altered to have channel0 to an alternate
# configuration or that only one slot can be used.
choice
prompt "SMDK6410 MMC/SD slot setup"
depends on MACH_SMDK6410
config SMDK6410_SD_CH0
bool "Use channel 0 only"
depends on MACH_SMDK6410
help
Select CON7 (channel 0) as the MMC/SD slot, as
at least some SMDK6410 boards come with the
resistors fitted so that the card detects for
channels 0 and 1 are the same.
config SMDK6410_SD_CH1
bool "Use channel 1 only"
depends on MACH_SMDK6410
help
Select CON6 (channel 1) as the MMC/SD slot, as
at least some SMDK6410 boards come with the
resistors fitted so that the card detects for
channels 0 and 1 are the same.
endchoice

4
arch/arm/mach-s3c6410/Makefile
View File

@ -14,6 +14,10 @@ obj- :=
obj-$(CONFIG_CPU_S3C6410) += cpu.o
# Helper and device support
obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o
# machine support
obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o

10
arch/arm/mach-s3c6410/cpu.c
View File

@ -35,6 +35,8 @@
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
#include <plat/sdhci.h>
#include <plat/iic-core.h>
#include <plat/s3c6400.h>
#include <plat/s3c6410.h>
@ -51,6 +53,14 @@ static struct map_desc s3c6410_iodesc[] __initdata = {
void __init s3c6410_map_io(void)
{
iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc));
/* initialise device information early */
s3c6410_default_sdhci0();
s3c6410_default_sdhci1();
/* the i2c devices are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
}
void __init s3c6410_init_clocks(int xtal)

96
arch/arm/mach-s3c6410/mach-smdk6410.c
View File

@ -20,18 +20,27 @@
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/fb.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <video/platform_lcd.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/regs-fb.h>
#include <mach/map.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/iic.h>
#include <plat/fb.h>
#include <plat/s3c6410.h>
#include <plat/clock.h>
@ -59,9 +68,89 @@ static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
},
};
/* framebuffer and LCD setup. */
/* GPF15 = LCD backlight control
* GPF13 => Panel power
* GPN5 = LCD nRESET signal
* PWM_TOUT1 => backlight brightness
*/
static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
unsigned int power)
{
if (power) {
gpio_direction_output(S3C64XX_GPF(13), 1);
gpio_direction_output(S3C64XX_GPF(15), 1);
/* fire nRESET on power up */
gpio_direction_output(S3C64XX_GPN(5), 0);
msleep(10);
gpio_direction_output(S3C64XX_GPN(5), 1);
msleep(1);
} else {
gpio_direction_output(S3C64XX_GPF(15), 0);
gpio_direction_output(S3C64XX_GPF(13), 0);
}
}
static struct plat_lcd_data smdk6410_lcd_power_data = {
.set_power = smdk6410_lcd_power_set,
};
static struct platform_device smdk6410_lcd_powerdev = {
.name = "platform-lcd",
.dev.parent = &s3c_device_fb.dev,
.dev.platform_data = &smdk6410_lcd_power_data,
};
static struct s3c_fb_pd_win smdk6410_fb_win0 = {
/* this is to ensure we use win0 */
.win_mode = {
.pixclock = 41094,
.left_margin = 8,
.right_margin = 13,
.upper_margin = 7,
.lower_margin = 5,
.hsync_len = 3,
.vsync_len = 1,
.xres = 800,
.yres = 480,
},
.max_bpp = 32,
.default_bpp = 16,
};
/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
.setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
.win[0] = &smdk6410_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};
struct map_desc smdk6410_iodesc[] = {};
static struct platform_device *smdk6410_devices[] __initdata = {
#ifdef CONFIG_SMDK6410_SD_CH0
&s3c_device_hsmmc0,
#endif
#ifdef CONFIG_SMDK6410_SD_CH1
&s3c_device_hsmmc1,
#endif
&s3c_device_i2c0,
&s3c_device_i2c1,
&s3c_device_fb,
&smdk6410_lcd_powerdev,
};
static struct i2c_board_info i2c_devs0[] __initdata = {
{ I2C_BOARD_INFO("24c08", 0x50), },
{ I2C_BOARD_INFO("WM8580", 0X1b), },
};
static struct i2c_board_info i2c_devs1[] __initdata = {
{ I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */
};
static void __init smdk6410_map_io(void)
@ -73,6 +162,13 @@ static void __init smdk6410_map_io(void)
static void __init smdk6410_machine_init(void)
{
s3c_i2c0_set_platdata(NULL);
s3c_i2c1_set_platdata(NULL);
s3c_fb_set_platdata(&smdk6410_lcd_pdata);
i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
}

102
arch/arm/mach-s3c6410/setup-sdhci.c 100644
View File

@ -0,0 +1,102 @@
/* linux/arch/arm/mach-s3c6410/setup-sdhci.c
*
* Copyright 2008 Simtec Electronics
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <mach/gpio.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-sdhci.h>
#include <plat/sdhci.h>
/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
char *s3c6410_hsmmc_clksrcs[4] = {
[0] = "hsmmc",
[1] = "hsmmc",
[2] = "mmc_bus",
/* [3] = "48m", - note not succesfully used yet */
};
void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
{
unsigned int gpio;
unsigned int end;
end = S3C64XX_GPG(2 + width);
/* Set all the necessary GPG pins to special-function 0 */
for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
}
void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card)
{
u32 ctrl2, ctrl3;
/* don't need to alter anything acording to card-type */
writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
S3C_SDHCI_CTRL2_ENFBCLKRX |
S3C_SDHCI_CTRL2_DFCNT_NONE |
S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
if (ios->clock < 25 * 1000000)
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
S3C_SDHCI_CTRL3_FCSEL2 |
S3C_SDHCI_CTRL3_FCSEL1 |
S3C_SDHCI_CTRL3_FCSEL0);
else
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
writel(ctrl2, r + S3C_SDHCI_CONTROL2);
writel(ctrl3, r + S3C_SDHCI_CONTROL3);
}
void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
{
unsigned int gpio;
unsigned int end;
end = S3C64XX_GPH(2 + width);
/* Set all the necessary GPG pins to special-function 0 */
for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
}

70
arch/arm/plat-s3c/Kconfig
View File

@ -110,3 +110,73 @@ config S3C_LOWLEVEL_UART_PORT
such as the `Uncompressing...` at start time. The value of
this configuration should be between zero and two. The port
must have been initialised by the boot-loader before use.
# options for gpiolib support
config S3C_GPIO_SPACE
int "Space between gpio banks"
default 0
help
Add a number of spare GPIO entries between each bank for debugging
purposes. This allows any problems where an counter overflows from
one bank to another to be caught, at the expense of using a little
more memory.
config S3C_GPIO_TRACK
bool
help
Internal configuration option to enable the s3c specific gpio
chip tracking if the platform requires it.
config S3C_GPIO_PULL_UPDOWN
bool
help
Internal configuration to enable the correct GPIO pull helper
config S3C_GPIO_PULL_DOWN
bool
help
Internal configuration to enable the correct GPIO pull helper
config S3C_GPIO_PULL_UP
bool
help
Internal configuration to enable the correct GPIO pull helper
config S3C_GPIO_CFG_S3C24XX
bool
help
Internal configuration to enable S3C24XX style GPIO configuration
functions.
config S3C_GPIO_CFG_S3C64XX
bool
help
Internal configuration to enable S3C64XX style GPIO configuration
functions.
# device definitions to compile in
config S3C_DEV_HSMMC
bool
depends on PLAT_S3C
help
Compile in platform device definitions for HSMMC code
config S3C_DEV_HSMMC1
bool
depends on PLAT_S3C
help
Compile in platform device definitions for HSMMC channel 1
config S3C_DEV_I2C1
bool
depends on PLAT_S3C
help
Compile in platform device definitions for I2C channel 1
config S3C_DEV_FB
bool
depends on PLAT_S3C
help
Compile in platform device definition for framebuffer

12
arch/arm/plat-s3c/Makefile
View File

@ -14,4 +14,14 @@ obj- :=
obj-y += init.o
obj-y += time.o
obj-y += clock.o
obj-y += pwm-clock.o
obj-y += pwm-clock.o
obj-y += gpio.o
obj-y += gpio-config.o
# devices
obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o
obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o
obj-y += dev-i2c0.o
obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o

72
arch/arm/plat-s3c/dev-fb.c 100644
View File

@ -0,0 +1,72 @@
/* linux/arch/arm/plat-s3c/dev-fb.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for framebuffer device
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
#include <mach/map.h>
#include <mach/regs-fb.h>
#include <plat/fb.h>
#include <plat/devs.h>
#include <plat/cpu.h>
static struct resource s3c_fb_resource[] = {
[0] = {
.start = S3C_PA_FB,
.end = S3C_PA_FB + SZ_16K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_LCD_VSYNC,
.end = IRQ_LCD_VSYNC,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = IRQ_LCD_FIFO,
.end = IRQ_LCD_FIFO,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = IRQ_LCD_SYSTEM,
.end = IRQ_LCD_SYSTEM,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device s3c_device_fb = {
.name = "s3c-fb",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_fb_resource),
.resource = s3c_fb_resource,
.dev.dma_mask = &s3c_device_fb.dev.coherent_dma_mask,
.dev.coherent_dma_mask = 0xffffffffUL,
};
void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
{
struct s3c_fb_platdata *npd;
if (!pd) {
printk(KERN_ERR "%s: no platform data\n", __func__);
return;
}
npd = kmemdup(pd, sizeof(struct s3c_fb_platdata), GFP_KERNEL);
if (!npd)
printk(KERN_ERR "%s: no memory for platform data\n", __func__);
s3c_device_fb.dev.platform_data = npd;
}

68
arch/arm/plat-s3c/dev-hsmmc.c 100644
View File

@ -0,0 +1,68 @@
/* linux/arch/arm/plat-s3c/dev-hsmmc.c
*
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for hsmmc devices
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mmc/host.h>
#include <mach/map.h>
#include <plat/sdhci.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#define S3C_SZ_HSMMC (0x1000)
static struct resource s3c_hsmmc_resource[] = {
[0] = {
.start = S3C_PA_HSMMC0,
.end = S3C_PA_HSMMC0 + S3C_SZ_HSMMC - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_HSMMC0,
.end = IRQ_HSMMC0,
.flags = IORESOURCE_IRQ,
}
};
static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
};
struct platform_device s3c_device_hsmmc0 = {
.name = "s3c-sdhci",
.id = 0,
.num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
.resource = s3c_hsmmc_resource,
.dev = {
.dma_mask = &s3c_device_hsmmc_dmamask,
.coherent_dma_mask = 0xffffffffUL,
.platform_data = &s3c_hsmmc0_def_platdata,
},
};
void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
{
struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata;
set->max_width = pd->max_width;
if (pd->cfg_gpio)
set->cfg_gpio = pd->cfg_gpio;
if (pd->cfg_card)
set->cfg_card = pd->cfg_card;
}

68
arch/arm/plat-s3c/dev-hsmmc1.c 100644
View File

@ -0,0 +1,68 @@
/* linux/arch/arm/plat-s3c/dev-hsmmc1.c
*
* Copyright (c) 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for hsmmc device 1
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mmc/host.h>
#include <mach/map.h>
#include <plat/sdhci.h>
#include <plat/devs.h>
#include <plat/cpu.h>
#define S3C_SZ_HSMMC (0x1000)
static struct resource s3c_hsmmc1_resource[] = {
[0] = {
.start = S3C_PA_HSMMC1,
.end = S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_HSMMC1,
.end = IRQ_HSMMC1,
.flags = IORESOURCE_IRQ,
}
};
static u64 s3c_device_hsmmc1_dmamask = 0xffffffffUL;
struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
.max_width = 4,
.host_caps = (MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
};
struct platform_device s3c_device_hsmmc1 = {
.name = "s3c-sdhci",
.id = 1,
.num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
.resource = s3c_hsmmc1_resource,
.dev = {
.dma_mask = &s3c_device_hsmmc1_dmamask,
.coherent_dma_mask = 0xffffffffUL,
.platform_data = &s3c_hsmmc1_def_platdata,
},
};
void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
{
struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
set->max_width = pd->max_width;
if (pd->cfg_gpio)
set->cfg_gpio = pd->cfg_gpio;
if (pd->cfg_card)
set->cfg_card = pd->cfg_card;
}

71
arch/arm/plat-s3c/dev-i2c0.c 100644
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@ -0,0 +1,71 @@
/* linux/arch/arm/plat-s3c/dev-i2c0.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for i2c device 0
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <mach/map.h>
#include <plat/regs-iic.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
static struct resource s3c_i2c_resource[] = {
[0] = {
.start = S3C_PA_IIC,
.end = S3C_PA_IIC + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IIC,
.end = IRQ_IIC,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device s3c_device_i2c0 = {
.name = "s3c2410-i2c",
#ifdef CONFIG_S3C_DEV_I2C1
.id = 0,
#else
.id = -1,
#endif
.num_resources = ARRAY_SIZE(s3c_i2c_resource),
.resource = s3c_i2c_resource,
};
static struct s3c2410_platform_i2c default_i2c_data0 __initdata = {
.flags = 0,
.slave_addr = 0x10,
.bus_freq = 100*1000,
.max_freq = 400*1000,
.sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
};
void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
if (!pd)
pd = &default_i2c_data0;
npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
if (!npd)
printk(KERN_ERR "%s: no memory for platform data\n", __func__);
else if (!npd->cfg_gpio)
npd->cfg_gpio = s3c_i2c0_cfg_gpio;
s3c_device_i2c0.dev.platform_data = npd;
}

68
arch/arm/plat-s3c/dev-i2c1.c 100644
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@ -0,0 +1,68 @@
/* linux/arch/arm/plat-s3c/dev-i2c1.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series device definition for i2c device 1
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/platform_device.h>
#include <mach/map.h>
#include <plat/regs-iic.h>
#include <plat/iic.h>
#include <plat/devs.h>
#include <plat/cpu.h>
static struct resource s3c_i2c_resource[] = {
[0] = {
.start = S3C_PA_IIC1,
.end = S3C_PA_IIC1 + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IIC1,
.end = IRQ_IIC1,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device s3c_device_i2c1 = {
.name = "s3c2410-i2c",
.id = 1,
.num_resources = ARRAY_SIZE(s3c_i2c_resource),
.resource = s3c_i2c_resource,
};
static struct s3c2410_platform_i2c default_i2c_data1 __initdata = {
.flags = 0,
.bus_num = 1,
.slave_addr = 0x10,
.bus_freq = 100*1000,
.max_freq = 400*1000,
.sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
};
void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
if (!pd)
pd = &default_i2c_data1;
npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
if (!npd)
printk(KERN_ERR "%s: no memory for platform data\n", __func__);
else if (!npd->cfg_gpio)
npd->cfg_gpio = s3c_i2c1_cfg_gpio;
s3c_device_i2c1.dev.platform_data = npd;
}

163
arch/arm/plat-s3c/gpio-config.c 100644
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@ -0,0 +1,163 @@
/* linux/arch/arm/plat-s3c/gpio-config.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series GPIO configuration core
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <mach/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
{
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
unsigned long flags;
int offset;
int ret;
if (!chip)
return -EINVAL;
offset = pin - chip->chip.base;
local_irq_save(flags);
ret = s3c_gpio_do_setcfg(chip, offset, config);
local_irq_restore(flags);
return ret;
}
int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
{
struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
unsigned long flags;
int offset, ret;
if (!chip)
return -EINVAL;
offset = pin - chip->chip.base;
local_irq_save(flags);
ret = s3c_gpio_do_setpull(chip, offset, pull);
local_irq_restore(flags);
return ret;
}
#ifdef CONFIG_S3C_GPIO_CFG_S3C24XX
int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
void __iomem *reg = chip->base;
unsigned int shift = off;
u32 con;
if (s3c_gpio_is_cfg_special(cfg)) {
cfg &= 0xf;
/* Map output to 0, and SFN2 to 1 */
cfg -= 1;
if (cfg > 1)
return -EINVAL;
cfg <<= shift;
}
con = __raw_readl(reg);
con &= ~(0x1 << shift);
con |= cfg;
__raw_writel(con, reg);
return 0;
}
int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
void __iomem *reg = chip->base;
unsigned int shift = off * 2;
u32 con;
if (s3c_gpio_is_cfg_special(cfg)) {
cfg &= 0xf;
if (cfg > 3)
return -EINVAL;
cfg <<= shift;
}
con = __raw_readl(reg);
con &= ~(0x3 << shift);
con |= cfg;
__raw_writel(con, reg);
return 0;
}
#endif
#ifdef CONFIG_S3C_GPIO_CFG_S3C64XX
int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg)
{
void __iomem *reg = chip->base;
unsigned int shift = (off & 7) * 4;
u32 con;
if (off < 8 && chip->chip.ngpio >= 8)
reg -= 4;
if (s3c_gpio_is_cfg_special(cfg)) {
cfg &= 0xf;
cfg <<= shift;
}
con = __raw_readl(reg);
con &= ~(0xf << shift);
con |= cfg;
__raw_writel(con, reg);
return 0;
}
#endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */
#ifdef CONFIG_S3C_GPIO_PULL_UPDOWN
int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull)
{
void __iomem *reg = chip->base + 0x08;
int shift = off * 2;
u32 pup;
pup = __raw_readl(reg);
pup &= ~(3 << shift);
pup |= pull << shift;
__raw_writel(pup, reg);
return 0;
}
s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
unsigned int off)
{
void __iomem *reg = chip->base + 0x08;
int shift = off * 2;
u32 pup = __raw_readl(reg);
pup >>= shift;
pup &= 0x3;
return (__force s3c_gpio_pull_t)pup;
}
#endif

147
arch/arm/plat-s3c/gpio.c 100644
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@ -0,0 +1,147 @@
/* linux/arch/arm/plat-s3c/gpio.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C series GPIO core
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <plat/gpio-core.h>
#ifdef CONFIG_S3C_GPIO_TRACK
struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip)
{
unsigned int gpn;
int i;
gpn = chip->chip.base;
for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
BUG_ON(gpn > ARRAY_SIZE(s3c_gpios));
s3c_gpios[gpn] = chip;
}
}
#endif /* CONFIG_S3C_GPIO_TRACK */
/* Default routines for controlling GPIO, based on the original S3C24XX
* GPIO functions which deal with the case where each gpio bank of the
* chip is as following:
*
* base + 0x00: Control register, 2 bits per gpio
* gpio n: 2 bits starting at (2*n)
* 00 = input, 01 = output, others mean special-function
* base + 0x04: Data register, 1 bit per gpio
* bit n: data bit n
*/
static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long con;
local_irq_save(flags);
con = __raw_readl(base + 0x00);
con &= ~(3 << (offset * 2));
__raw_writel(con, base + 0x00);
local_irq_restore(flags);
return 0;
}
static int s3c_gpiolib_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long dat;
unsigned long con;
local_irq_save(flags);
dat = __raw_readl(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
__raw_writel(dat, base + 0x04);
con = __raw_readl(base + 0x00);
con &= ~(3 << (offset * 2));
con |= 1 << (offset * 2);
__raw_writel(con, base + 0x00);
__raw_writel(dat, base + 0x04);
local_irq_restore(flags);
return 0;
}
static void s3c_gpiolib_set(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long dat;
local_irq_save(flags);
dat = __raw_readl(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
__raw_writel(dat, base + 0x04);
local_irq_restore(flags);
}
static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
unsigned long val;
val = __raw_readl(ourchip->base + 0x04);
val >>= offset;
val &= 1;
return val;
}
__init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
{
struct gpio_chip *gc = &chip->chip;
int ret;
BUG_ON(!chip->base);
BUG_ON(!gc->label);
BUG_ON(!gc->ngpio);
if (!gc->direction_input)
gc->direction_input = s3c_gpiolib_input;
if (!gc->direction_output)
gc->direction_output = s3c_gpiolib_output;
if (!gc->set)
gc->set = s3c_gpiolib_set;
if (!gc->get)
gc->get = s3c_gpiolib_get;
/* gpiochip_add() prints own failure message on error. */
ret = gpiochip_add(gc);
if (ret >= 0)
s3c_gpiolib_track(chip);
}

8
arch/arm/plat-s3c/include/plat/devs.h
View File

@ -24,15 +24,19 @@ extern struct platform_device *s3c24xx_uart_src[];
extern struct platform_device s3c_device_timer[];
extern struct platform_device s3c_device_fb;
extern struct platform_device s3c_device_usb;
extern struct platform_device s3c_device_lcd;
extern struct platform_device s3c_device_wdt;
extern struct platform_device s3c_device_i2c;
extern struct platform_device s3c_device_i2c0;
extern struct platform_device s3c_device_i2c1;
extern struct platform_device s3c_device_iis;
extern struct platform_device s3c_device_rtc;
extern struct platform_device s3c_device_adc;
extern struct platform_device s3c_device_sdi;
extern struct platform_device s3c_device_hsmmc;
extern struct platform_device s3c_device_hsmmc0;
extern struct platform_device s3c_device_hsmmc1;
extern struct platform_device s3c_device_hsmmc2;
extern struct platform_device s3c_device_spi0;
extern struct platform_device s3c_device_spi1;

73
arch/arm/plat-s3c/include/plat/fb.h 100644
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@ -0,0 +1,73 @@
/* linux/arch/arm/plat-s3c/include/plat/fb.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C - FB platform data definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_S3C_FB_H
#define __PLAT_S3C_FB_H __FILE__
/**
* struct s3c_fb_pd_win - per window setup data
* @win_mode: The display parameters to initialise (not for window 0)
* @virtual_x: The virtual X size.
* @virtual_y: The virtual Y size.
*/
struct s3c_fb_pd_win {
struct fb_videomode win_mode;
unsigned short default_bpp;
unsigned short max_bpp;
unsigned short virtual_x;
unsigned short virtual_y;
};
/**
* struct s3c_fb_platdata - S3C driver platform specific information
* @setup_gpio: Setup the external GPIO pins to the right state to transfer
* the data from the display system to the connected display
* device.
* @vidcon0: The base vidcon0 values to control the panel data format.
* @vidcon1: The base vidcon1 values to control the panel data output.
* @win: The setup data for each hardware window, or NULL for unused.
* @display_mode: The LCD output display mode.
*
* The platform data supplies the video driver with all the information
* it requires to work with the display(s) attached to the machine. It
* controls the initial mode, the number of display windows (0 is always
* the base framebuffer) that are initialised etc.
*
*/
struct s3c_fb_platdata {
void (*setup_gpio)(void);
struct s3c_fb_pd_win *win[S3C_FB_MAX_WIN];
u32 vidcon0;
u32 vidcon1;
};
/**
* s3c_fb_set_platdata() - Setup the FB device with platform data.
* @pd: The platform data to set. The data is copied from the passed structure
* so the machine data can mark the data __initdata so that any unused
* machines will end up dumping their data at runtime.
*/
extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
/**
* s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
*
* Initialise the GPIO for an 24bpp LCD display on the RGB interface.
*/
extern void s3c64xx_fb_gpio_setup_24bpp(void);
#endif /* __PLAT_S3C_FB_H */

176
arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h 100644
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@ -0,0 +1,176 @@
/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - GPIO pin configuration helper definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* This is meant for core cpu support, machine or other driver files
* should not be including this header.
*/
#ifndef __PLAT_GPIO_CFG_HELPERS_H
#define __PLAT_GPIO_CFG_HELPERS_H __FILE__
/* As a note, all gpio configuration functions are entered exclusively, either
* with the relevant lock held or the system prevented from doing anything else
* by disabling interrupts.
*/
static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int config)
{
return (chip->config->set_config)(chip, off, config);
}
static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull)
{
return (chip->config->set_pull)(chip, off, pull);
}
/**
* s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @cfg: The configuration value to set.
*
* This helper deal with the GPIO cases where the control register
* has two bits of configuration per gpio, which have the following
* functions:
* 00 = input
* 01 = output
* 1x = special function
*/
extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg);
/**
* s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A)
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @cfg: The configuration value to set.
*
* This helper deal with the GPIO cases where the control register
* has one bit of configuration for the gpio, where setting the bit
* means the pin is in special function mode and unset means output.
*/
extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg);
/**
* s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @cfg: The configuration value to set.
*
* This helper deal with the GPIO cases where the control register has 4 bits
* of control per GPIO, generally in the form of:
* 0000 = Input
* 0001 = Output
* others = Special functions (dependant on bank)
*
* Note, since the code to deal with the case where there are two control
* registers instead of one, we do not have a seperate set of functions for
* each case.
*/
extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
unsigned int off, unsigned int cfg);
/* Pull-{up,down} resistor controls.
*
* S3C2410,S3C2440,S3C24A0 = Pull-UP,
* S3C2412,S3C2413 = Pull-Down
* S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef]
* S3C2443 = Pull-Both [not same as S3C6400]
*/
/**
* s3c_gpio_setpull_1up() - Pull configuration for choice of up or none.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @param: pull: The pull mode being requested.
*
* This is a helper function for the case where we have GPIOs with one
* bit configuring the presence of a pull-up resistor.
*/
extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull);
/**
* s3c_gpio_setpull_1down() - Pull configuration for choice of down or none
* @chip: The gpio chip that is being configured
* @off: The offset for the GPIO being configured
* @param: pull: The pull mode being requested
*
* This is a helper function for the case where we have GPIOs with one
* bit configuring the presence of a pull-down resistor.
*/
extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull);
/**
* s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @param: pull: The pull mode being requested.
*
* This is a helper function for the case where we have GPIOs with two
* bits configuring the presence of a pull resistor, in the following
* order:
* 00 = No pull resistor connected
* 01 = Pull-up resistor connected
* 10 = Pull-down resistor connected
*/
extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull);
/**
* s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none
* @chip: The gpio chip that the GPIO pin belongs to
* @off: The offset to the pin to get the configuration of.
*
* This helper function reads the state of the pull-{up,down} resistor for the
* given GPIO in the same case as s3c_gpio_setpull_upown.
*/
extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
unsigned int off);
/**
* s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443.
* @chip: The gpio chip that is being configured.
* @off: The offset for the GPIO being configured.
* @param: pull: The pull mode being requested.
*
* This is a helper function for the case where we have GPIOs with two
* bits configuring the presence of a pull resistor, in the following
* order:
* 00 = Pull-up resistor connected
* 10 = Pull-down resistor connected
* x1 = No pull up resistor
*/
extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip,
unsigned int off, s3c_gpio_pull_t pull);
/**
* s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors
* @chip: The gpio chip that the GPIO pin belongs to.
* @off: The offset to the pin to get the configuration of.
*
* This helper function reads the state of the pull-{up,down} resistor for the
* given GPIO in the same case as s3c_gpio_setpull_upown.
*/
extern s3c_gpio_pull_t s3c_gpio_getpull_s3c24xx(struct s3c_gpio_chip *chip,
unsigned int off);
#endif /* __PLAT_GPIO_CFG_HELPERS_H */

110
arch/arm/plat-s3c/include/plat/gpio-cfg.h 100644
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@ -0,0 +1,110 @@
/* linux/arch/arm/plat-s3c/include/plat/gpio-cfg.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - GPIO pin configuration
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* This file contains the necessary definitions to get the basic gpio
* pin configuration done such as setting a pin to input or output or
* changing the pull-{up,down} configurations.
*/
/* Note, this interface is being added to the s3c64xx arch first and will
* be added to the s3c24xx systems later.
*/
#ifndef __PLAT_GPIO_CFG_H
#define __PLAT_GPIO_CFG_H __FILE__
typedef unsigned int __bitwise__ s3c_gpio_pull_t;
/* forward declaration if gpio-core.h hasn't been included */
struct s3c_gpio_chip;
/**
* struct s3c_gpio_cfg GPIO configuration
* @cfg_eint: Configuration setting when used for external interrupt source
* @get_pull: Read the current pull configuration for the GPIO
* @set_pull: Set the current pull configuraiton for the GPIO
* @set_config: Set the current configuration for the GPIO
* @get_config: Read the current configuration for the GPIO
*
* Each chip can have more than one type of GPIO bank available and some
* have different capabilites even when they have the same control register
* layouts. Provide an point to vector control routine and provide any
* per-bank configuration information that other systems such as the
* external interrupt code will need.
*/
struct s3c_gpio_cfg {
unsigned int cfg_eint;
s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs);
int (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs,
s3c_gpio_pull_t pull);
unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs);
int (*set_config)(struct s3c_gpio_chip *chip, unsigned offs,
unsigned config);
};
#define S3C_GPIO_SPECIAL_MARK (0xfffffff0)
#define S3C_GPIO_SPECIAL(x) (S3C_GPIO_SPECIAL_MARK | (x))
/* Defines for generic pin configurations */
#define S3C_GPIO_INPUT (S3C_GPIO_SPECIAL(0))
#define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1))
#define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x))
#define s3c_gpio_is_cfg_special(_cfg) \
(((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK)
/**
* s3c_gpio_cfgpin() - Change the GPIO function of a pin.
* @pin pin The pin number to configure.
* @pin to The configuration for the pin's function.
*
* Configure which function is actually connected to the external
* pin, such as an gpio input, output or some form of special function
* connected to an internal peripheral block.
*/
extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to);
/* Define values for the pull-{up,down} available for each gpio pin.
*
* These values control the state of the weak pull-{up,down} resistors
* available on most pins on the S3C series. Not all chips support both
* up or down settings, and it may be dependant on the chip that is being
* used to whether the particular mode is available.
*/
#define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00)
#define S3C_GPIO_PULL_DOWN ((__force s3c_gpio_pull_t)0x01)
#define S3C_GPIO_PULL_UP ((__force s3c_gpio_pull_t)0x02)
/**
* s3c_gpio_setpull() - set the state of a gpio pin pull resistor
* @pin: The pin number to configure the pull resistor.
* @pull: The configuration for the pull resistor.
*
* This function sets the state of the pull-{up,down} resistor for the
* specified pin. It will return 0 if successfull, or a negative error
* code if the pin cannot support the requested pull setting.
*/
extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull);
/**
* s3c_gpio_getpull() - get the pull resistor state of a gpio pin
* @pin: The pin number to get the settings for
*
* Read the pull resistor value for the specified pin.
*/
extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
#endif /* __PLAT_GPIO_CFG_H */

77
arch/arm/plat-s3c/include/plat/gpio-core.h 100644
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@ -0,0 +1,77 @@
/* linux/arch/arm/plat-s3c/include/plat/gpio-core.h
*
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - GPIO core
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Define the core gpiolib support functions that the s3c platforms may
* need to extend or change depending on the hardware and the s3c chip
* selected at build or found at run time.
*
* These definitions are not intended for driver inclusion, there is
* nothing here that should not live outside the platform and core
* specific code.
*/
struct s3c_gpio_cfg;
/**
* struct s3c_gpio_chip - wrapper for specific implementation of gpio
* @chip: The chip structure to be exported via gpiolib.
* @base: The base pointer to the gpio configuration registers.
* @config: special function and pull-resistor control information.
*
* This wrapper provides the necessary information for the Samsung
* specific gpios being registered with gpiolib.
*/
struct s3c_gpio_chip {
struct gpio_chip chip;
struct s3c_gpio_cfg *config;
void __iomem *base;
};
static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc)
{
return container_of(gpc, struct s3c_gpio_chip, chip);
}
/** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip.
* @chip: The chip to register
*
* This is a wrapper to gpiochip_add() that takes our specific gpio chip
* information and makes the necessary alterations for the platform and
* notes the information for use with the configuration systems and any
* other parts of the system.
*/
extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip);
/* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
* for use with the configuration calls, and other parts of the s3c gpiolib
* support code.
*
* Not all s3c support code will need this, as some configurations of cpu
* may only support one or two different configuration options and have an
* easy gpio to s3c_gpio_chip mapping function. If this is the case, then
* the machine support file should provide its own s3c_gpiolib_getchip()
* and any other necessary functions.
*/
#ifdef CONFIG_S3C_GPIO_TRACK
extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip)
{
return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL;
}
#else
/* machine specific code should provide s3c_gpiolib_getchip */
static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { }
#endif

35
arch/arm/plat-s3c/include/plat/iic-core.h 100644
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@ -0,0 +1,35 @@
/* arch/arm/mach-s3c2410/include/mach/iic-core.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C - I2C Controller core functions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_IIC_CORE_H
#define __ASM_ARCH_IIC_CORE_H __FILE__
/* These functions are only for use with the core support code, such as
* the cpu specific initialisation code
*/
/* re-define device name depending on support. */
static inline void s3c_i2c0_setname(char *name)
{
/* currently this device is always compiled in */
s3c_device_i2c0.name = name;
}
static inline void s3c_i2c1_setname(char *name)
{
#ifdef CONFIG_S3C_DEV_I2C1
s3c_device_i2c1.name = name;
#endif
}
#endif /* __ASM_ARCH_IIC_H */

24
arch/arm/plat-s3c/include/plat/iic.h
View File

@ -28,6 +28,30 @@ struct s3c2410_platform_i2c {
unsigned long max_freq; /* max frequency for the bus */
unsigned long min_freq; /* min frequency for the bus */
unsigned int sda_delay; /* pclks (s3c2440 only) */
void (*cfg_gpio)(struct platform_device *dev);
};
/**
* s3c_i2c0_set_platdata - set platform data for i2c0 device
* @i2c: The platform data to set, or NULL for default data.
*
* Register the given platform data for use with the i2c0 device. This
* call copies the platform data, so the caller can use __initdata for
* their copy.
*
* This call will set cfg_gpio if is null to the default platform
* implementation.
*
* Any user of s3c_device_i2c0 should call this, even if it is with
* NULL to ensure that the device is given the default platform data
* as the driver will no longer carry defaults.
*/
extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c);
extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c);
/* defined by architecture to configure gpio */
extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c1_cfg_gpio(struct platform_device *dev);
#endif /* __ASM_ARCH_IIC_H */

366
arch/arm/plat-s3c/include/plat/regs-fb.h 100644
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@ -0,0 +1,366 @@
/* arch/arm/plat-s3c/include/plat/regs-fb.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - new-style framebuffer register definitions
*
* This is the register set for the new style framebuffer interface
* found from the S3C2443 onwards into the S3C2416, S3C2450 and the
* S3C64XX series such as the S3C6400 and S3C6410.
*
* The file does not contain the cpu specific items which are based on
* whichever architecture is selected, it only contains the core of the
* register set. See <mach/regs-fb.h> to get the specifics.
*
* Note, we changed to using regs-fb.h as it avoids any clashes with
* the original regs-lcd.h so out of the way of regs-lcd.h as well as
* indicating the newer block is much more than just an LCD interface.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Please do not include this file directly, use <mach/regs-fb.h> to
* ensure all the localised SoC support is included as necessary.
*/
/* VIDCON0 */
#define VIDCON0 (0x00)
#define VIDCON0_INTERLACE (1 << 29)
#define VIDCON0_VIDOUT_MASK (0x3 << 26)
#define VIDCON0_VIDOUT_SHIFT (26)
#define VIDCON0_VIDOUT_RGB (0x0 << 26)
#define VIDCON0_VIDOUT_TV (0x1 << 26)
#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
#define VIDCON0_L1_DATA_MASK (0x7 << 23)
#define VIDCON0_L1_DATA_SHIFT (23)
#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
#define VIDCON0_L0_DATA_MASK (0x7 << 20)
#define VIDCON0_L0_DATA_SHIFT (20)
#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
#define VIDCON0_PNRMODE_MASK (0x3 << 17)
#define VIDCON0_PNRMODE_SHIFT (17)
#define VIDCON0_PNRMODE_RGB (0x0 << 17)
#define VIDCON0_PNRMODE_BGR (0x1 << 17)
#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
#define VIDCON0_CLKVALUP (1 << 16)
#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
#define VIDCON0_CLKVAL_F_SHIFT (6)
#define VIDCON0_CLKVAL_F_LIMIT (0xff)
#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
#define VIDCON0_VLCKFREE (1 << 5)
#define VIDCON0_CLKDIR (1 << 4)
#define VIDCON0_CLKSEL_MASK (0x3 << 2)
#define VIDCON0_CLKSEL_SHIFT (2)
#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
#define VIDCON0_CLKSEL_LCD (0x1 << 2)
#define VIDCON0_CLKSEL_27M (0x3 << 2)
#define VIDCON0_ENVID (1 << 1)
#define VIDCON0_ENVID_F (1 << 0)
#define VIDCON1 (0x04)
#define VIDCON1_LINECNT_MASK (0x7ff << 16)
#define VIDCON1_LINECNT_SHIFT (16)
#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
#define VIDCON1_VSTATUS_MASK (0x3 << 13)
#define VIDCON1_VSTATUS_SHIFT (13)
#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
#define VIDCON1_INV_VCLK (1 << 7)
#define VIDCON1_INV_HSYNC (1 << 6)
#define VIDCON1_INV_VSYNC (1 << 5)
#define VIDCON1_INV_VDEN (1 << 4)
/* VIDCON2 */
#define VIDCON2 (0x08)
#define VIDCON2_EN601 (1 << 23)
#define VIDCON2_TVFMTSEL_SW (1 << 14)
#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
#define VIDCON2_TVFMTSEL1_SHIFT (12)
#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
#define VIDCON2_ORGYCbCr (1 << 8)
#define VIDCON2_YUVORDCrCb (1 << 7)
/* VIDTCON0 */
#define VIDTCON0_VBPDE_MASK (0xff << 24)
#define VIDTCON0_VBPDE_SHIFT (24)
#define VIDTCON0_VBPDE_LIMIT (0xff)
#define VIDTCON0_VBPDE(_x) ((_x) << 24)
#define VIDTCON0_VBPD_MASK (0xff << 16)
#define VIDTCON0_VBPD_SHIFT (16)
#define VIDTCON0_VBPD_LIMIT (0xff)
#define VIDTCON0_VBPD(_x) ((_x) << 16)
#define VIDTCON0_VFPD_MASK (0xff << 8)
#define VIDTCON0_VFPD_SHIFT (8)
#define VIDTCON0_VFPD_LIMIT (0xff)
#define VIDTCON0_VFPD(_x) ((_x) << 8)
#define VIDTCON0_VSPW_MASK (0xff << 0)
#define VIDTCON0_VSPW_SHIFT (0)
#define VIDTCON0_VSPW_LIMIT (0xff)
#define VIDTCON0_VSPW(_x) ((_x) << 0)
/* VIDTCON1 */
#define VIDTCON1_VFPDE_MASK (0xff << 24)
#define VIDTCON1_VFPDE_SHIFT (24)
#define VIDTCON1_VFPDE_LIMIT (0xff)
#define VIDTCON1_VFPDE(_x) ((_x) << 24)
#define VIDTCON1_HBPD_MASK (0xff << 16)
#define VIDTCON1_HBPD_SHIFT (16)
#define VIDTCON1_HBPD_LIMIT (0xff)
#define VIDTCON1_HBPD(_x) ((_x) << 16)
#define VIDTCON1_HFPD_MASK (0xff << 8)
#define VIDTCON1_HFPD_SHIFT (8)
#define VIDTCON1_HFPD_LIMIT (0xff)
#define VIDTCON1_HFPD(_x) ((_x) << 8)
#define VIDTCON1_HSPW_MASK (0xff << 0)
#define VIDTCON1_HSPW_SHIFT (0)
#define VIDTCON1_HSPW_LIMIT (0xff)
#define VIDTCON1_HSPW(_x) ((_x) << 0)
#define VIDTCON2 (0x18)
#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
#define VIDTCON2_LINEVAL_SHIFT (11)
#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
#define VIDTCON2_LINEVAL(_x) ((_x) << 11)
#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
#define VIDTCON2_HOZVAL_SHIFT (0)
#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
#define VIDTCON2_HOZVAL(_x) ((_x) << 0)
/* WINCONx */
#define WINCONx_BITSWP (1 << 18)
#define WINCONx_BYTSWP (1 << 17)
#define WINCONx_HAWSWP (1 << 16)
#define WINCONx_BURSTLEN_MASK (0x3 << 9)
#define WINCONx_BURSTLEN_SHIFT (9)
#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
#define WINCONx_ENWIN (1 << 0)
#define WINCON0_BPPMODE_MASK (0xf << 2)
#define WINCON0_BPPMODE_SHIFT (2)
#define WINCON0_BPPMODE_1BPP (0x0 << 2)
#define WINCON0_BPPMODE_2BPP (0x1 << 2)
#define WINCON0_BPPMODE_4BPP (0x2 << 2)
#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON1_BLD_PIX (1 << 6)
#define WINCON1_ALPHA_SEL (1 << 1)
#define WINCON1_BPPMODE_MASK (0xf << 2)
#define WINCON1_BPPMODE_SHIFT (2)
#define WINCON1_BPPMODE_1BPP (0x0 << 2)
#define WINCON1_BPPMODE_2BPP (0x1 << 2)
#define WINCON1_BPPMODE_4BPP (0x2 << 2)
#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
#define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11)
#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
#define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0)
#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
#define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11)
#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
#define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0)
/* For VIDOSD[1..4]C */
#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
#define VIDISD14C_ALPHA0_G_SHIFT (16)
#define VIDISD14C_ALPHA0_G_LIMIT (0xf)
#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
#define VIDISD14C_ALPHA0_B_SHIFT (12)
#define VIDISD14C_ALPHA0_B_LIMIT (0xf)
#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
#define VIDISD14C_ALPHA1_R_SHIFT (8)
#define VIDISD14C_ALPHA1_R_LIMIT (0xf)
#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
#define VIDISD14C_ALPHA1_G_SHIFT (4)
#define VIDISD14C_ALPHA1_G_LIMIT (0xf)
#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
#define VIDISD14C_ALPHA1_B_SHIFT (0)
#define VIDISD14C_ALPHA1_B_LIMIT (0xf)
#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
/* Video buffer addresses */
#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
#define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13)
#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
#define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0)
/* Interrupt controls and status */
#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
#define VIDINTCON0_INT_I80IFDONE (1 << 17)
#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
#define VIDINTCON0_FRAMESEL0_SHIFT (15)
#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
#define VIDINTCON0_FRAMESEL1 (1 << 14)
#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 14)
#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 14)
#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 14)
#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 14)
#define VIDINTCON0_INT_FRAME (1 << 12)
#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
#define VIDINTCON0_FIFIOSEL_SHIFT (5)
#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
#define VIDINTCON0_INT_FIFO_SHIFT (0)
#define VIDINTCON0_INT_ENABLE (1 << 0)
#define VIDINTCON1 (0x134)
#define VIDINTCON1_INT_I180 (1 << 2)
#define VIDINTCON1_INT_FRAME (1 << 1)
#define VIDINTCON1_INT_FIFO (1 << 0)
/* Window colour-key control registers */
#define WxKEYCON0_KEYBL_EN (1 << 26)
#define WxKEYCON0_KEYEN_F (1 << 25)
#define WxKEYCON0_DIRCON (1 << 24)
#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
#define WxKEYCON0_COMPKEY_SHIFT (0)
#define WxKEYCON0_COMPKEY_LIMIT (0xffffff)
#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
#define WxKEYCON1_COLVAL_SHIFT (0)
#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
/* Window blanking (MAP) */
#define WINxMAP_MAP (1 << 24)
#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
#define WINxMAP_MAP_COLOUR_SHIFT (0)
#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
#define WPALCON_PAL_UPDATE (1 << 9)
#define WPALCON_W1PAL_MASK (0x7 << 3)
#define WPALCON_W1PAL_SHIFT (3)
#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
#define WPALCON_W1PAL_24BPP (0x1 << 3)
#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
#define WPALCON_W1PAL_18BPP (0x4 << 3)
#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
#define WPALCON_W0PAL_MASK (0x7 << 0)
#define WPALCON_W0PAL_SHIFT (0)
#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
#define WPALCON_W0PAL_24BPP (0x1 << 0)
#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
#define WPALCON_W0PAL_18BPP (0x4 << 0)
#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)

87
arch/arm/plat-s3c/include/plat/regs-sdhci.h 100644
View File

@ -0,0 +1,87 @@
/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - SDHCI (HSMMC) register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_S3C_SDHCI_REGS_H
#define __PLAT_S3C_SDHCI_REGS_H __FILE__
#define S3C_SDHCI_CONTROL2 (0x80)
#define S3C_SDHCI_CONTROL3 (0x84)
#define S3C64XX_SDHCI_CONTROL4 (0x8C)
#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
#define S3C_SDHCI_CTRL2_CDINVRXD3 (1 << 29)
#define S3C_SDHCI_CTRL2_SLCARDOUT (1 << 28)
#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
#define S3C_SDHCI_CTRL2_ENFBCLKTX (1 << 15)
#define S3C_SDHCI_CTRL2_ENFBCLKRX (1 << 14)
#define S3C_SDHCI_CTRL2_SDCDSEL (1 << 13)
#define S3C_SDHCI_CTRL2_SDSIGPC (1 << 12)
#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
#define S3C_SDHCI_CTRL2_RWAITMODE (1 << 7)
#define S3C_SDHCI_CTRL2_DISBUFRD (1 << 6)
#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
#define S3C_SDHCI_CTRL2_PWRSYNC (1 << 3)
#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
#define S3C_SDHCI_CTRL2_HWINITFIN (1 << 0)
#define S3C_SDHCI_CTRL3_FCSEL3 (1 << 31)
#define S3C_SDHCI_CTRL3_FCSEL2 (1 << 23)
#define S3C_SDHCI_CTRL3_FCSEL1 (1 << 15)
#define S3C_SDHCI_CTRL3_FCSEL0 (1 << 7)
#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
#define S3C64XX_SDHCI_CONTROL4_BUSY (1)
#endif /* __PLAT_S3C_SDHCI_REGS_H */

108
arch/arm/plat-s3c/include/plat/sdhci.h 100644
View File

@ -0,0 +1,108 @@
/* linux/arch/arm/plat-s3c/include/plat/sdhci.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - SDHCI (HSMMC) platform data definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_S3C_SDHCI_H
#define __PLAT_S3C_SDHCI_H __FILE__
struct platform_device;
struct mmc_host;
struct mmc_card;
struct mmc_ios;
/**
* struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
* @max_width: The maximum number of data bits supported.
* @host_caps: Standard MMC host capabilities bit field.
* @cfg_gpio: Configure the GPIO for a specific card bit-width
* @cfg_card: Configure the interface for a specific card and speed. This
* is necessary the controllers and/or GPIO blocks require the
* changing of driver-strength and other controls dependant on
* the card and speed of operation.
*
* Initialisation data specific to either the machine or the platform
* for the device driver to use or call-back when configuring gpio or
* card speed information.
*/
struct s3c_sdhci_platdata {
unsigned int max_width;
unsigned int host_caps;
char **clocks; /* set of clock sources */
void (*cfg_gpio)(struct platform_device *dev, int width);
void (*cfg_card)(struct platform_device *dev,
void __iomem *regbase,
struct mmc_ios *ios,
struct mmc_card *card);
};
/**
* s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device.
* @pd: Platform data to register to device.
*
* Register the given platform data for use withe S3C SDHCI device.
* The call will copy the platform data, so the board definitions can
* make the structure itself __initdata.
*/
extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd);
extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
/* Default platform data, exported so that per-cpu initialisation can
* set the correct one when there are more than one cpu type selected.
*/
extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata;
extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
/* Helper function availablity */
#ifdef CONFIG_S3C6410_SETUP_SDHCI
extern char *s3c6410_hsmmc_clksrcs[4];
extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card);
#ifdef CONFIG_S3C_DEV_HSMMC
static inline void s3c6410_default_sdhci0(void)
{
s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio;
s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
}
#else
static inline void s3c6410_default_sdhci0(void) { }
#endif /* CONFIG_S3C_DEV_HSMMC */
#ifdef CONFIG_S3C_DEV_HSMMC1
static inline void s3c6410_default_sdhci1(void)
{
s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio;
s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
}
#else
static inline void s3c6410_default_sdhci1(void) { }
#endif /* CONFIG_S3C_DEV_HSMMC1 */
#else
static inline void s3c6410_default_sdhci0(void) { }
static inline void s3c6410_default_sdhci1(void) { }
#endif /* CONFIG_S3C6410_SETUP_SDHCI */
#endif /* __PLAT_S3C_SDHCI_H */

3
arch/arm/plat-s3c24xx/Makefile
View File

@ -33,6 +33,9 @@ obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o
obj-$(CONFIG_S3C2410_DMA) += dma.o
obj-$(CONFIG_S3C24XX_ADC) += adc.o
# device specific setup and/or initialisation
obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o
# SPI gpio central GPIO functions
obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o

55
arch/arm/plat-s3c24xx/devs.c
View File

@ -271,31 +271,6 @@ struct platform_device s3c_device_wdt = {
EXPORT_SYMBOL(s3c_device_wdt);
/* I2C */
static struct resource s3c_i2c_resource[] = {
[0] = {
.start = S3C24XX_PA_IIC,
.end = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_IIC,
.end = IRQ_IIC,
.flags = IORESOURCE_IRQ,
}
};
struct platform_device s3c_device_i2c = {
.name = "s3c2410-i2c",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_i2c_resource),
.resource = s3c_i2c_resource,
};
EXPORT_SYMBOL(s3c_device_i2c);
/* IIS */
static struct resource s3c_iis_resource[] = {
@ -411,36 +386,6 @@ struct platform_device s3c_device_sdi = {
EXPORT_SYMBOL(s3c_device_sdi);
/* High-speed MMC/SD */
static struct resource s3c_hsmmc_resource[] = {
[0] = {
.start = S3C2443_PA_HSMMC,
.end = S3C2443_PA_HSMMC + S3C2443_SZ_HSMMC - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_S3C2443_HSMMC,
.end = IRQ_S3C2443_HSMMC,
.flags = IORESOURCE_IRQ,
}
};
static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL;
struct platform_device s3c_device_hsmmc = {
.name = "s3c-sdhci",
.id = -1,
.num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
.resource = s3c_hsmmc_resource,
.dev = {
.dma_mask = &s3c_device_hsmmc_dmamask,
.coherent_dma_mask = 0xffffffffUL
}
};
/* SPI (0) */
static struct resource s3c_spi0_resource[] = {

125
arch/arm/plat-s3c24xx/gpiolib.c
View File

@ -19,104 +19,12 @@
#include <linux/io.h>
#include <linux/gpio.h>
#include <plat/gpio-core.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <mach/regs-gpio.h>
struct s3c24xx_gpio_chip {
struct gpio_chip chip;
void __iomem *base;
};
static inline struct s3c24xx_gpio_chip *to_s3c_chip(struct gpio_chip *gpc)
{
return container_of(gpc, struct s3c24xx_gpio_chip, chip);
}
/* these routines are exported for use by other parts of the platform
* and system support, but are not intended to be used directly by the
* drivers themsevles.
*/
static int s3c24xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
{
struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long con;
local_irq_save(flags);
con = __raw_readl(base + 0x00);
con &= ~(3 << (offset * 2));
con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
__raw_writel(con, base + 0x00);
local_irq_restore(flags);
return 0;
}
static int s3c24xx_gpiolib_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long dat;
unsigned long con;
local_irq_save(flags);
dat = __raw_readl(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
__raw_writel(dat, base + 0x04);
con = __raw_readl(base + 0x00);
con &= ~(3 << (offset * 2));
con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
__raw_writel(con, base + 0x00);
__raw_writel(dat, base + 0x04);
local_irq_restore(flags);
return 0;
}
static void s3c24xx_gpiolib_set(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long dat;
local_irq_save(flags);
dat = __raw_readl(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
__raw_writel(dat, base + 0x04);
local_irq_restore(flags);
}
static int s3c24xx_gpiolib_get(struct gpio_chip *chip, unsigned offset)
{
struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
unsigned long val;
val = __raw_readl(ourchip->base + 0x04);
val >>= offset;
val &= 1;
return val;
}
static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
{
return -EINVAL;
@ -125,7 +33,7 @@ static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long flags;
unsigned long dat;
@ -151,7 +59,7 @@ static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
return 0;
}
static struct s3c24xx_gpio_chip gpios[] = {
struct s3c_gpio_chip s3c24xx_gpios[] = {
[0] = {
.base = S3C24XX_GPIO_BASE(S3C2410_GPA0),
.chip = {
@ -219,34 +127,13 @@ static struct s3c24xx_gpio_chip gpios[] = {
},
};
static __init void s3c24xx_gpiolib_add(struct s3c24xx_gpio_chip *chip)
{
struct gpio_chip *gc = &chip->chip;
BUG_ON(!chip->base);
BUG_ON(!gc->label);
BUG_ON(!gc->ngpio);
if (!gc->direction_input)
gc->direction_input = s3c24xx_gpiolib_input;
if (!gc->direction_output)
gc->direction_output = s3c24xx_gpiolib_output;
if (!gc->set)
gc->set = s3c24xx_gpiolib_set;
if (!gc->get)
gc->get = s3c24xx_gpiolib_get;
/* gpiochip_add() prints own failure message on error. */
gpiochip_add(gc);
}
static __init int s3c24xx_gpiolib_init(void)
{
struct s3c24xx_gpio_chip *chip = gpios;
struct s3c_gpio_chip *chip = s3c24xx_gpios;
int gpn;
for (gpn = 0; gpn < ARRAY_SIZE(gpios); gpn++, chip++)
s3c24xx_gpiolib_add(chip);
for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++)
s3c_gpiolib_add(chip);
return 0;
}

1
arch/arm/plat-s3c24xx/include/plat/map.h
View File

@ -51,7 +51,6 @@
/* Standard size definitions for peripheral blocks. */
#define S3C24XX_SZ_IIC SZ_1M
#define S3C24XX_SZ_IIS SZ_1M
#define S3C24XX_SZ_ADC SZ_1M
#define S3C24XX_SZ_SPI SZ_1M

2
arch/arm/plat-s3c24xx/s3c244x.c
View File

@ -68,7 +68,7 @@ void __init s3c244x_map_io(void)
/* rename any peripherals used differing from the s3c2410 */
s3c_device_sdi.name = "s3c2440-sdi";
s3c_device_i2c.name = "s3c2440-i2c";
s3c_device_i2c0.name = "s3c2440-i2c";
s3c_device_nand.name = "s3c2440-nand";
s3c_device_usbgadget.name = "s3c2440-usbgadget";
}

25
arch/arm/plat-s3c24xx/setup-i2c.c 100644
View File

@ -0,0 +1,25 @@
/* linux/arch/arm/plat-s3c24xx/setup-i2c.c
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX Base setup for i2c device
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
struct platform_device;
#include <plat/iic.h>
#include <mach/hardware.h>
#include <mach/regs-gpio.h>
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
}

25
arch/arm/plat-s3c64xx/Kconfig
View File

@ -14,6 +14,10 @@ config PLAT_S3C64XX
default y
select NO_IOPORT
select ARCH_REQUIRE_GPIOLIB
select S3C_GPIO_TRACK
select S3C_GPIO_PULL_UPDOWN
select S3C_GPIO_CFG_S3C24XX
select S3C_GPIO_CFG_S3C64XX
help
Base platform code for any Samsung S3C64XX device
@ -33,4 +37,25 @@ config CPU_S3C6400_CLOCK
Common clock support code for the S3C6400 that is shared
by other CPUs in the series, such as the S3C6410.
# platform specific device setup
config S3C64XX_SETUP_I2C0
bool
default y
help
Common setup code for i2c bus 0.
Note, currently since i2c0 is always compiled, this setup helper
is always compiled with it.
config S3C64XX_SETUP_I2C1
bool
help
Common setup code for i2c bus 1.
config S3C64XX_SETUP_FB_24BPP
bool
help
Common setup code for S3C64XX with an 24bpp RGB display helper.
endif

7
arch/arm/plat-s3c64xx/Makefile
View File

@ -17,8 +17,15 @@ obj-y += cpu.o
obj-y += irq.o
obj-y += irq-eint.o
obj-y += clock.o
obj-y += gpiolib.o
# CPU support
obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o
obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o
# Device setup
obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o

420
arch/arm/plat-s3c64xx/gpiolib.c 100644
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@ -0,0 +1,420 @@
/* arch/arm/plat-s3c64xx/gpiolib.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX - GPIOlib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/map.h>
#include <mach/gpio.h>
#include <mach/gpio-core.h>
#include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h>
#include <plat/regs-gpio.h>
/* GPIO bank summary:
*
* Bank GPIOs Style SlpCon ExtInt Group
* A 8 4Bit Yes 1
* B 7 4Bit Yes 1
* C 8 4Bit Yes 2
* D 5 4Bit Yes 3
* E 5 4Bit Yes None
* F 16 2Bit Yes 4 [1]
* G 7 4Bit Yes 5
* H 10 4Bit[2] Yes 6
* I 16 2Bit Yes None
* J 12 2Bit Yes None
* K 16 4Bit[2] No None
* L 15 4Bit[2] No None
* M 6 4Bit No IRQ_EINT
* N 16 2Bit No IRQ_EINT
* O 16 2Bit Yes 7
* P 15 2Bit Yes 8
* Q 9 2Bit Yes 9
*
* [1] BANKF pins 14,15 do not form part of the external interrupt sources
* [2] BANK has two control registers, GPxCON0 and GPxCON1
*/
#define OFF_GPCON (0x00)
#define OFF_GPDAT (0x04)
#define con_4bit_shift(__off) ((__off) * 4)
#if 1
#define gpio_dbg(x...) do { } while(0)
#else
#define gpio_dbg(x...) printk(KERN_DEBUG ## x)
#endif
/* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where
* the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
* following example:
*
* base + 0x00: Control register, 4 bits per gpio
* gpio n: 4 bits starting at (4*n)
* 0000 = input, 0001 = output, others mean special-function
* base + 0x04: Data register, 1 bit per gpio
* bit n: data bit n
*
* Note, since the data register is one bit per gpio and is at base + 0x4
* we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
* the output.
*/
static int s3c64xx_gpiolib_4bit_input(struct gpio_chip *chip, unsigned offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long con;
con = __raw_readl(base + OFF_GPCON);
con &= ~(0xf << con_4bit_shift(offset));
__raw_writel(con, base + OFF_GPCON);
gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
return 0;
}
static int s3c64xx_gpiolib_4bit_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long con;
unsigned long dat;
con = __raw_readl(base + OFF_GPCON);
con &= ~(0xf << con_4bit_shift(offset));
con |= 0x1 << con_4bit_shift(offset);
dat = __raw_readl(base + OFF_GPDAT);
if (value)
dat |= 1 << offset;
else
dat &= ~(1 << offset);
__raw_writel(dat, base + OFF_GPDAT);
__raw_writel(con, base + OFF_GPCON);
__raw_writel(dat, base + OFF_GPDAT);
gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
return 0;
}
/* The next set of routines are for the case where the GPIO configuration
* registers are 4 bits per GPIO but there is more than one register (the
* bank has more than 8 GPIOs.
*
* This case is the similar to the 4 bit case, but the registers are as
* follows:
*
* base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
* gpio n: 4 bits starting at (4*n)
* 0000 = input, 0001 = output, others mean special-function
* base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
* gpio n: 4 bits starting at (4*n)
* 0000 = input, 0001 = output, others mean special-function
* base + 0x08: Data register, 1 bit per gpio
* bit n: data bit n
*
* To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we
* store the 'base + 0x4' address so that these routines see the data
* register at ourchip->base + 0x04.
*/
static int s3c64xx_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
void __iomem *regcon = base;
unsigned long con;
if (offset > 7)
offset -= 8;
else
regcon -= 4;
con = __raw_readl(regcon);
con &= ~(0xf << con_4bit_shift(offset));
__raw_writel(con, regcon);
gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
return 0;
}
static int s3c64xx_gpiolib_4bit2_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
void __iomem *regcon = base;
unsigned long con;
unsigned long dat;
if (offset > 7)
offset -= 8;
else
regcon -= 4;
con = __raw_readl(regcon);
con &= ~(0xf << con_4bit_shift(offset));
con |= 0x1 << con_4bit_shift(offset);
dat = __raw_readl(base + OFF_GPDAT);
if (value)
dat |= 1 << offset;
else
dat &= ~(1 << offset);
__raw_writel(dat, base + OFF_GPDAT);
__raw_writel(con, regcon);
__raw_writel(dat, base + OFF_GPDAT);
gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
return 0;
}
static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
.cfg_eint = 7,
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
.cfg_eint = 3,
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_chip gpio_4bit[] = {
{
.base = S3C64XX_GPA_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPA(0),
.ngpio = S3C64XX_GPIO_A_NR,
.label = "GPA",
},
}, {
.base = S3C64XX_GPB_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPB(0),
.ngpio = S3C64XX_GPIO_B_NR,
.label = "GPB",
},
}, {
.base = S3C64XX_GPC_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPC(0),
.ngpio = S3C64XX_GPIO_C_NR,
.label = "GPC",
},
}, {
.base = S3C64XX_GPD_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPD(0),
.ngpio = S3C64XX_GPIO_D_NR,
.label = "GPD",
},
}, {
.base = S3C64XX_GPE_BASE,
.config = &gpio_4bit_cfg_noint,
.chip = {
.base = S3C64XX_GPE(0),
.ngpio = S3C64XX_GPIO_E_NR,
.label = "GPE",
},
}, {
.base = S3C64XX_GPG_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPG(0),
.ngpio = S3C64XX_GPIO_G_NR,
.label = "GPG",
},
}, {
.base = S3C64XX_GPM_BASE,
.config = &gpio_4bit_cfg_eint0011,
.chip = {
.base = S3C64XX_GPM(0),
.ngpio = S3C64XX_GPIO_M_NR,
.label = "GPM",
},
},
};
static struct s3c_gpio_chip gpio_4bit2[] = {
{
.base = S3C64XX_GPH_BASE + 0x4,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPH(0),
.ngpio = S3C64XX_GPIO_H_NR,
.label = "GPH",
},
}, {
.base = S3C64XX_GPK_BASE + 0x4,
.config = &gpio_4bit_cfg_noint,
.chip = {
.base = S3C64XX_GPK(0),
.ngpio = S3C64XX_GPIO_K_NR,
.label = "GPK",
},
}, {
.base = S3C64XX_GPL_BASE + 0x4,
.config = &gpio_4bit_cfg_eint0011,
.chip = {
.base = S3C64XX_GPL(0),
.ngpio = S3C64XX_GPIO_L_NR,
.label = "GPL",
},
},
};
static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
.set_config = s3c_gpio_setcfg_s3c24xx,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
.cfg_eint = 2,
.set_config = s3c_gpio_setcfg_s3c24xx,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
.cfg_eint = 3,
.set_config = s3c_gpio_setcfg_s3c24xx,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
};
static struct s3c_gpio_chip gpio_2bit[] = {
{
.base = S3C64XX_GPF_BASE,
.config = &gpio_2bit_cfg_eint11,
.chip = {
.base = S3C64XX_GPF(0),
.ngpio = S3C64XX_GPIO_F_NR,
.label = "GPF",
},
}, {
.base = S3C64XX_GPI_BASE,
.config = &gpio_2bit_cfg_noint,
.chip = {
.base = S3C64XX_GPI(0),
.ngpio = S3C64XX_GPIO_I_NR,
.label = "GPI",
},
}, {
.base = S3C64XX_GPJ_BASE,
.config = &gpio_2bit_cfg_noint,
.chip = {
.base = S3C64XX_GPJ(0),
.ngpio = S3C64XX_GPIO_J_NR,
.label = "GPJ",
},
}, {
.base = S3C64XX_GPN_BASE,
.config = &gpio_2bit_cfg_eint10,
.chip = {
.base = S3C64XX_GPN(0),
.ngpio = S3C64XX_GPIO_N_NR,
.label = "GPN",
},
}, {
.base = S3C64XX_GPO_BASE,
.config = &gpio_2bit_cfg_eint11,
.chip = {
.base = S3C64XX_GPO(0),
.ngpio = S3C64XX_GPIO_O_NR,
.label = "GPO",
},
}, {
.base = S3C64XX_GPP_BASE,
.config = &gpio_2bit_cfg_eint11,
.chip = {
.base = S3C64XX_GPP(0),
.ngpio = S3C64XX_GPIO_P_NR,
.label = "GPP",
},
}, {
.base = S3C64XX_GPQ_BASE,
.config = &gpio_2bit_cfg_eint11,
.chip = {
.base = S3C64XX_GPQ(0),
.ngpio = S3C64XX_GPIO_Q_NR,
.label = "GPQ",
},
},
};
static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
{
chip->chip.direction_input = s3c64xx_gpiolib_4bit_input;
chip->chip.direction_output = s3c64xx_gpiolib_4bit_output;
}
static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
{
chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input;
chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output;
}
static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
int nr_chips,
void (*fn)(struct s3c_gpio_chip *))
{
for (; nr_chips > 0; nr_chips--, chips++) {
if (fn)
(fn)(chips);
s3c_gpiolib_add(chips);
}
}
static __init int s3c64xx_gpiolib_init(void)
{
s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
s3c64xx_gpiolib_add_4bit);
s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
s3c64xx_gpiolib_add_4bit2);
s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL);
return 0;
}
arch_initcall(s3c64xx_gpiolib_init);

48
arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h 100644
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@ -0,0 +1,48 @@
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank A register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPACON (S3C64XX_GPA_BASE + 0x00)
#define S3C64XX_GPADAT (S3C64XX_GPA_BASE + 0x04)
#define S3C64XX_GPAPUD (S3C64XX_GPA_BASE + 0x08)
#define S3C64XX_GPACONSLP (S3C64XX_GPA_BASE + 0x0c)
#define S3C64XX_GPAPUDSLP (S3C64XX_GPA_BASE + 0x10)
#define S3C64XX_GPA_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPA_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPA_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPA0_UART_RXD0 (0x02 << 0)
#define S3C64XX_GPA0_EINT_G1_0 (0x07 << 0)
#define S3C64XX_GPA1_UART_TXD0 (0x02 << 4)
#define S3C64XX_GPA1_EINT_G1_1 (0x07 << 4)
#define S3C64XX_GPA2_UART_nCTS0 (0x02 << 8)
#define S3C64XX_GPA2_EINT_G1_2 (0x07 << 8)
#define S3C64XX_GPA3_UART_nRTS0 (0x02 << 12)
#define S3C64XX_GPA3_EINT_G1_3 (0x07 << 12)
#define S3C64XX_GPA4_UART_RXD1 (0x02 << 16)
#define S3C64XX_GPA4_EINT_G1_4 (0x07 << 16)
#define S3C64XX_GPA5_UART_TXD1 (0x02 << 20)
#define S3C64XX_GPA5_EINT_G1_5 (0x07 << 20)
#define S3C64XX_GPA6_UART_nCTS1 (0x02 << 24)
#define S3C64XX_GPA6_EINT_G1_6 (0x07 << 24)
#define S3C64XX_GPA7_UART_nRTS1 (0x02 << 28)
#define S3C64XX_GPA7_EINT_G1_7 (0x07 << 28)

60
arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h 100644
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@ -0,0 +1,60 @@
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank B register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPBCON (S3C64XX_GPB_BASE + 0x00)
#define S3C64XX_GPBDAT (S3C64XX_GPB_BASE + 0x04)
#define S3C64XX_GPBPUD (S3C64XX_GPB_BASE + 0x08)
#define S3C64XX_GPBCONSLP (S3C64XX_GPB_BASE + 0x0c)
#define S3C64XX_GPBPUDSLP (S3C64XX_GPB_BASE + 0x10)
#define S3C64XX_GPB_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPB_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPB_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPB0_UART_RXD2 (0x02 << 0)
#define S3C64XX_GPB0_EXTDMA_REQ (0x03 << 0)
#define S3C64XX_GPB0_IrDA_RXD (0x04 << 0)
#define S3C64XX_GPB0_ADDR_CF0 (0x05 << 0)
#define S3C64XX_GPB0_EINT_G1_8 (0x07 << 0)
#define S3C64XX_GPB1_UART_TXD2 (0x02 << 4)
#define S3C64XX_GPB1_EXTDMA_ACK (0x03 << 4)
#define S3C64XX_GPB1_IrDA_TXD (0x04 << 4)
#define S3C64XX_GPB1_ADDR_CF1 (0x05 << 4)
#define S3C64XX_GPB1_EINT_G1_9 (0x07 << 4)
#define S3C64XX_GPB2_UART_RXD3 (0x02 << 8)
#define S3C64XX_GPB2_IrDA_RXD (0x03 << 8)
#define S3C64XX_GPB2_EXTDMA_REQ (0x04 << 8)
#define S3C64XX_GPB2_ADDR_CF2 (0x05 << 8)
#define S3C64XX_GPB2_I2C_SCL1 (0x06 << 8)
#define S3C64XX_GPB2_EINT_G1_10 (0x07 << 8)
#define S3C64XX_GPB3_UART_TXD3 (0x02 << 12)
#define S3C64XX_GPB3_IrDA_TXD (0x03 << 12)
#define S3C64XX_GPB3_EXTDMA_ACK (0x04 << 12)
#define S3C64XX_GPB3_I2C_SDA1 (0x06 << 12)
#define S3C64XX_GPB3_EINT_G1_11 (0x07 << 12)
#define S3C64XX_GPB4_IrDA_SDBW (0x02 << 16)
#define S3C64XX_GPB4_CAM_FIELD (0x03 << 16)
#define S3C64XX_GPB4_CF_DATA_DIR (0x04 << 16)
#define S3C64XX_GPB4_EINT_G1_12 (0x07 << 16)
#define S3C64XX_GPB5_I2C_SCL0 (0x02 << 20)
#define S3C64XX_GPB5_EINT_G1_13 (0x07 << 20)
#define S3C64XX_GPB6_I2C_SDA0 (0x02 << 24)
#define S3C64XX_GPB6_EINT_G1_14 (0x07 << 24)

53
arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h 100644
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@ -0,0 +1,53 @@
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank C register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPCCON (S3C64XX_GPC_BASE + 0x00)
#define S3C64XX_GPCDAT (S3C64XX_GPC_BASE + 0x04)
#define S3C64XX_GPCPUD (S3C64XX_GPC_BASE + 0x08)
#define S3C64XX_GPCCONSLP (S3C64XX_GPC_BASE + 0x0c)
#define S3C64XX_GPCPUDSLP (S3C64XX_GPC_BASE + 0x10)
#define S3C64XX_GPC_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPC_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPC_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPC0_SPI_MISO0 (0x02 << 0)
#define S3C64XX_GPC0_EINT_G2_0 (0x07 << 0)
#define S3C64XX_GPC1_SPI_CLKO (0x02 << 4)
#define S3C64XX_GPC1_EINT_G2_1 (0x07 << 4)
#define S3C64XX_GPC2_SPI_MOSIO (0x02 << 8)
#define S3C64XX_GPC2_EINT_G2_2 (0x07 << 8)
#define S3C64XX_GPC3_SPI_nCSO (0x02 << 12)
#define S3C64XX_GPC3_EINT_G2_3 (0x07 << 12)
#define S3C64XX_GPC4_SPI_MISO1 (0x02 << 16)
#define S3C64XX_GPC4_MMC2_CMD (0x03 << 16)
#define S3C64XX_GPC4_I2S0_V40_DO (0x05 << 16)
#define S3C64XX_GPC4_EINT_G2_4 (0x07 << 16)
#define S3C64XX_GPC5_SPI_CLK1 (0x02 << 20)
#define S3C64XX_GPC5_MMC2_CLK (0x03 << 20)
#define S3C64XX_GPC5_I2S1_V40_DO (0x05 << 20)
#define S3C64XX_GPC5_EINT_G2_5 (0x07 << 20)
#define S3C64XX_GPC6_SPI_MOSI1 (0x02 << 24)
#define S3C64XX_GPC6_EINT_G2_6 (0x07 << 24)
#define S3C64XX_GPC7_SPI_nCS1 (0x02 << 28)
#define S3C64XX_GPC7_I2S2_V40_DO (0x05 << 28)
#define S3C64XX_GPC7_EINT_G2_7 (0x07 << 28)

49
arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h 100644
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank D register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPDCON (S3C64XX_GPD_BASE + 0x00)
#define S3C64XX_GPDDAT (S3C64XX_GPD_BASE + 0x04)
#define S3C64XX_GPDPUD (S3C64XX_GPD_BASE + 0x08)
#define S3C64XX_GPDCONSLP (S3C64XX_GPD_BASE + 0x0c)
#define S3C64XX_GPDPUDSLP (S3C64XX_GPD_BASE + 0x10)
#define S3C64XX_GPD_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPD_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPD_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPD0_PCM0_SCLK (0x02 << 0)
#define S3C64XX_GPD0_I2S0_CLK (0x03 << 0)
#define S3C64XX_GPD0_AC97_BITCLK (0x04 << 0)
#define S3C64XX_GPD0_EINT_G3_0 (0x07 << 0)
#define S3C64XX_GPD1_PCM0_EXTCLK (0x02 << 4)
#define S3C64XX_GPD1_I2S0_CDCLK (0x03 << 4)
#define S3C64XX_GPD1_AC97_nRESET (0x04 << 4)
#define S3C64XX_GPD1_EINT_G3_1 (0x07 << 4)
#define S3C64XX_GPD2_PCM0_FSYNC (0x02 << 8)
#define S3C64XX_GPD2_I2S0_LRCLK (0x03 << 8)
#define S3C64XX_GPD2_AC97_SYNC (0x04 << 8)
#define S3C64XX_GPD2_EINT_G3_2 (0x07 << 8)
#define S3C64XX_GPD3_PCM0_SIN (0x02 << 12)
#define S3C64XX_GPD3_I2S0_DI (0x03 << 12)
#define S3C64XX_GPD3_AC97_SDI (0x04 << 12)
#define S3C64XX_GPD3_EINT_G3_3 (0x07 << 12)
#define S3C64XX_GPD4_PCM0_SOUT (0x02 << 16)
#define S3C64XX_GPD4_I2S0_D0 (0x03 << 16)
#define S3C64XX_GPD4_AC97_SDO (0x04 << 16)
#define S3C64XX_GPD4_EINT_G3_4 (0x07 << 16)

44
arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h 100644
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank E register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPECON (S3C64XX_GPE_BASE + 0x00)
#define S3C64XX_GPEDAT (S3C64XX_GPE_BASE + 0x04)
#define S3C64XX_GPEPUD (S3C64XX_GPE_BASE + 0x08)
#define S3C64XX_GPECONSLP (S3C64XX_GPE_BASE + 0x0c)
#define S3C64XX_GPEPUDSLP (S3C64XX_GPE_BASE + 0x10)
#define S3C64XX_GPE_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPE_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPE_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPE0_PCM1_SCLK (0x02 << 0)
#define S3C64XX_GPE0_I2S1_CLK (0x03 << 0)
#define S3C64XX_GPE0_AC97_BITCLK (0x04 << 0)
#define S3C64XX_GPE1_PCM1_EXTCLK (0x02 << 4)
#define S3C64XX_GPE1_I2S1_CDCLK (0x03 << 4)
#define S3C64XX_GPE1_AC97_nRESET (0x04 << 4)
#define S3C64XX_GPE2_PCM1_FSYNC (0x02 << 8)
#define S3C64XX_GPE2_I2S1_LRCLK (0x03 << 8)
#define S3C64XX_GPE2_AC97_SYNC (0x04 << 8)
#define S3C64XX_GPE3_PCM1_SIN (0x02 << 12)
#define S3C64XX_GPE3_I2S1_DI (0x03 << 12)
#define S3C64XX_GPE3_AC97_SDI (0x04 << 12)
#define S3C64XX_GPE4_PCM1_SOUT (0x02 << 16)
#define S3C64XX_GPE4_I2S1_D0 (0x03 << 16)
#define S3C64XX_GPE4_AC97_SDO (0x04 << 16)

71
arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h 100644
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank F register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPFCON (S3C64XX_GPF_BASE + 0x00)
#define S3C64XX_GPFDAT (S3C64XX_GPF_BASE + 0x04)
#define S3C64XX_GPFPUD (S3C64XX_GPF_BASE + 0x08)
#define S3C64XX_GPFCONSLP (S3C64XX_GPF_BASE + 0x0c)
#define S3C64XX_GPFPUDSLP (S3C64XX_GPF_BASE + 0x10)
#define S3C64XX_GPF_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPF_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPF_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPF0_CAMIF_CLK (0x02 << 0)
#define S3C64XX_GPF0_EINT_G4_0 (0x03 << 0)
#define S3C64XX_GPF1_CAMIF_HREF (0x02 << 2)
#define S3C64XX_GPF1_EINT_G4_1 (0x03 << 2)
#define S3C64XX_GPF2_CAMIF_PCLK (0x02 << 4)
#define S3C64XX_GPF2_EINT_G4_2 (0x03 << 4)
#define S3C64XX_GPF3_CAMIF_nRST (0x02 << 6)
#define S3C64XX_GPF3_EINT_G4_3 (0x03 << 6)
#define S3C64XX_GPF4_CAMIF_VSYNC (0x02 << 8)
#define S3C64XX_GPF4_EINT_G4_4 (0x03 << 8)
#define S3C64XX_GPF5_CAMIF_YDATA0 (0x02 << 10)
#define S3C64XX_GPF5_EINT_G4_5 (0x03 << 10)
#define S3C64XX_GPF6_CAMIF_YDATA1 (0x02 << 12)
#define S3C64XX_GPF6_EINT_G4_6 (0x03 << 12)
#define S3C64XX_GPF7_CAMIF_YDATA2 (0x02 << 14)
#define S3C64XX_GPF7_EINT_G4_7 (0x03 << 14)
#define S3C64XX_GPF8_CAMIF_YDATA3 (0x02 << 16)
#define S3C64XX_GPF8_EINT_G4_8 (0x03 << 16)
#define S3C64XX_GPF9_CAMIF_YDATA4 (0x02 << 18)
#define S3C64XX_GPF9_EINT_G4_9 (0x03 << 18)
#define S3C64XX_GPF10_CAMIF_YDATA5 (0x02 << 20)
#define S3C64XX_GPF10_EINT_G4_10 (0x03 << 20)
#define S3C64XX_GPF11_CAMIF_YDATA6 (0x02 << 22)
#define S3C64XX_GPF11_EINT_G4_11 (0x03 << 22)
#define S3C64XX_GPF12_CAMIF_YDATA7 (0x02 << 24)
#define S3C64XX_GPF12_EINT_G4_12 (0x03 << 24)
#define S3C64XX_GPF13_PWM_ECLK (0x02 << 26)
#define S3C64XX_GPF13_EINT_G4_13 (0x03 << 26)
#define S3C64XX_GPF14_PWM_TOUT0 (0x02 << 28)
#define S3C64XX_GPF14_CLKOUT0 (0x03 << 28)
#define S3C64XX_GPF15_PWM_TOUT1 (0x02 << 30)

42
arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h 100644
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank G register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPGCON (S3C64XX_GPG_BASE + 0x00)
#define S3C64XX_GPGDAT (S3C64XX_GPG_BASE + 0x04)
#define S3C64XX_GPGPUD (S3C64XX_GPG_BASE + 0x08)
#define S3C64XX_GPGCONSLP (S3C64XX_GPG_BASE + 0x0c)
#define S3C64XX_GPGPUDSLP (S3C64XX_GPG_BASE + 0x10)
#define S3C64XX_GPG_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPG_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPG_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPG0_MMC0_CLK (0x02 << 0)
#define S3C64XX_GPG0_EINT_G5_0 (0x07 << 0)
#define S3C64XX_GPG1_MMC0_CMD (0x02 << 4)
#define S3C64XX_GPG1_EINT_G5_1 (0x07 << 4)
#define S3C64XX_GPG2_MMC0_DATA0 (0x02 << 8)
#define S3C64XX_GPG2_EINT_G5_2 (0x07 << 8)
#define S3C64XX_GPG3_MMC0_DATA1 (0x02 << 12)
#define S3C64XX_GPG3_EINT_G5_3 (0x07 << 12)
#define S3C64XX_GPG4_MMC0_DATA2 (0x02 << 16)
#define S3C64XX_GPG4_EINT_G5_4 (0x07 << 16)
#define S3C64XX_GPG5_MMC0_DATA3 (0x02 << 20)
#define S3C64XX_GPG5_EINT_G5_5 (0x07 << 20)

74
arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h 100644
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank H register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPHCON0 (S3C64XX_GPH_BASE + 0x00)
#define S3C64XX_GPHCON1 (S3C64XX_GPH_BASE + 0x04)
#define S3C64XX_GPHDAT (S3C64XX_GPH_BASE + 0x08)
#define S3C64XX_GPHPUD (S3C64XX_GPH_BASE + 0x0c)
#define S3C64XX_GPHCONSLP (S3C64XX_GPH_BASE + 0x10)
#define S3C64XX_GPHPUDSLP (S3C64XX_GPH_BASE + 0x14)
#define S3C64XX_GPH_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#define S3C64XX_GPH_INPUT(__gpio) (0x0 << ((__gpio) * 4))
#define S3C64XX_GPH_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S3C64XX_GPH0_MMC1_CLK (0x02 << 0)
#define S3C64XX_GPH0_KP_COL0 (0x04 << 0)
#define S3C64XX_GPH0_EINT_G6_0 (0x07 << 0)
#define S3C64XX_GPH1_MMC1_CMD (0x02 << 4)
#define S3C64XX_GPH1_KP_COL1 (0x04 << 4)
#define S3C64XX_GPH1_EINT_G6_1 (0x07 << 4)
#define S3C64XX_GPH2_MMC1_DATA0 (0x02 << 8)
#define S3C64XX_GPH2_KP_COL2 (0x04 << 8)
#define S3C64XX_GPH2_EINT_G6_2 (0x07 << 8)
#define S3C64XX_GPH3_MMC1_DATA1 (0x02 << 12)
#define S3C64XX_GPH3_KP_COL3 (0x04 << 12)
#define S3C64XX_GPH3_EINT_G6_3 (0x07 << 12)
#define S3C64XX_GPH4_MMC1_DATA2 (0x02 << 16)
#define S3C64XX_GPH4_KP_COL4 (0x04 << 16)
#define S3C64XX_GPH4_EINT_G6_4 (0x07 << 16)
#define S3C64XX_GPH5_MMC1_DATA3 (0x02 << 20)
#define S3C64XX_GPH5_KP_COL5 (0x04 << 20)
#define S3C64XX_GPH5_EINT_G6_5 (0x07 << 20)
#define S3C64XX_GPH6_MMC1_DATA4 (0x02 << 24)
#define S3C64XX_GPH6_MMC2_DATA0 (0x03 << 24)
#define S3C64XX_GPH6_KP_COL6 (0x04 << 24)
#define S3C64XX_GPH6_I2S_V40_BCLK (0x05 << 24)
#define S3C64XX_GPH6_ADDR_CF0 (0x06 << 24)
#define S3C64XX_GPH6_EINT_G6_6 (0x07 << 24)
#define S3C64XX_GPH7_MMC1_DATA5 (0x02 << 28)
#define S3C64XX_GPH7_MMC2_DATA1 (0x03 << 28)
#define S3C64XX_GPH7_KP_COL7 (0x04 << 28)
#define S3C64XX_GPH7_I2S_V40_CDCLK (0x05 << 28)
#define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28)
#define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28)
#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 32)
#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 32)
#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 32)
#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 32)
#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 32)
#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 36)
#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 36)
#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 36)
#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 36)

40
arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h 100644
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank I register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPICON (S3C64XX_GPI_BASE + 0x00)
#define S3C64XX_GPIDAT (S3C64XX_GPI_BASE + 0x04)
#define S3C64XX_GPIPUD (S3C64XX_GPI_BASE + 0x08)
#define S3C64XX_GPICONSLP (S3C64XX_GPI_BASE + 0x0c)
#define S3C64XX_GPIPUDSLP (S3C64XX_GPI_BASE + 0x10)
#define S3C64XX_GPI_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPI_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPI_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPI0_VD0 (0x02 << 0)
#define S3C64XX_GPI1_VD1 (0x02 << 2)
#define S3C64XX_GPI2_VD2 (0x02 << 4)
#define S3C64XX_GPI3_VD3 (0x02 << 6)
#define S3C64XX_GPI4_VD4 (0x02 << 8)
#define S3C64XX_GPI5_VD5 (0x02 << 10)
#define S3C64XX_GPI6_VD6 (0x02 << 12)
#define S3C64XX_GPI7_VD7 (0x02 << 14)
#define S3C64XX_GPI8_VD8 (0x02 << 16)
#define S3C64XX_GPI9_VD9 (0x02 << 18)
#define S3C64XX_GPI10_VD10 (0x02 << 20)
#define S3C64XX_GPI11_VD11 (0x02 << 22)
#define S3C64XX_GPI12_VD12 (0x02 << 24)
#define S3C64XX_GPI13_VD13 (0x02 << 26)
#define S3C64XX_GPI14_VD14 (0x02 << 28)
#define S3C64XX_GPI15_VD15 (0x02 << 30)

36
arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h 100644
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank J register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPJCON (S3C64XX_GPJ_BASE + 0x00)
#define S3C64XX_GPJDAT (S3C64XX_GPJ_BASE + 0x04)
#define S3C64XX_GPJPUD (S3C64XX_GPJ_BASE + 0x08)
#define S3C64XX_GPJCONSLP (S3C64XX_GPJ_BASE + 0x0c)
#define S3C64XX_GPJPUDSLP (S3C64XX_GPJ_BASE + 0x10)
#define S3C64XX_GPJ_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPJ_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPJ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPJ0_VD16 (0x02 << 0)
#define S3C64XX_GPJ1_VD17 (0x02 << 2)
#define S3C64XX_GPJ2_VD18 (0x02 << 4)
#define S3C64XX_GPJ3_VD19 (0x02 << 6)
#define S3C64XX_GPJ4_VD20 (0x02 << 8)
#define S3C64XX_GPJ5_VD21 (0x02 << 10)
#define S3C64XX_GPJ6_VD22 (0x02 << 12)
#define S3C64XX_GPJ7_VD23 (0x02 << 14)
#define S3C64XX_GPJ8_LCD_HSYNC (0x02 << 16)
#define S3C64XX_GPJ9_LCD_VSYNC (0x02 << 18)
#define S3C64XX_GPJ10_LCD_VDEN (0x02 << 20)
#define S3C64XX_GPJ11_LCD_VCLK (0x02 << 22)

54
arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h 100644
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank N register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00)
#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04)
#define S3C64XX_GPNPUD (S3C64XX_GPN_BASE + 0x08)
#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPN_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPN0_EINT0 (0x02 << 0)
#define S3C64XX_GPN0_KP_ROW0 (0x03 << 0)
#define S3C64XX_GPN1_EINT1 (0x02 << 2)
#define S3C64XX_GPN1_KP_ROW1 (0x03 << 2)
#define S3C64XX_GPN2_EINT2 (0x02 << 4)
#define S3C64XX_GPN2_KP_ROW2 (0x03 << 4)
#define S3C64XX_GPN3_EINT3 (0x02 << 6)
#define S3C64XX_GPN3_KP_ROW3 (0x03 << 6)
#define S3C64XX_GPN4_EINT4 (0x02 << 8)
#define S3C64XX_GPN4_KP_ROW4 (0x03 << 8)
#define S3C64XX_GPN5_EINT5 (0x02 << 10)
#define S3C64XX_GPN5_KP_ROW5 (0x03 << 10)
#define S3C64XX_GPN6_EINT6 (0x02 << 12)
#define S3C64XX_GPN6_KP_ROW6 (0x03 << 12)
#define S3C64XX_GPN7_EINT7 (0x02 << 14)
#define S3C64XX_GPN7_KP_ROW7 (0x03 << 14)
#define S3C64XX_GPN8_EINT8 (0x02 << 16)
#define S3C64XX_GPN9_EINT9 (0x02 << 18)
#define S3C64XX_GPN10_EINT10 (0x02 << 20)
#define S3C64XX_GPN11_EINT11 (0x02 << 22)
#define S3C64XX_GPN12_EINT12 (0x02 << 24)
#define S3C64XX_GPN13_EINT13 (0x02 << 26)
#define S3C64XX_GPN14_EINT14 (0x02 << 28)
#define S3C64XX_GPN15_EINT15 (0x02 << 30)

70
arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h 100644
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/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank O register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPOCON (S3C64XX_GPO_BASE + 0x00)
#define S3C64XX_GPODAT (S3C64XX_GPO_BASE + 0x04)
#define S3C64XX_GPOPUD (S3C64XX_GPO_BASE + 0x08)
#define S3C64XX_GPOCONSLP (S3C64XX_GPO_BASE + 0x0c)
#define S3C64XX_GPOPUDSLP (S3C64XX_GPO_BASE + 0x10)
#define S3C64XX_GPO_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPO_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPO_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPO0_MEM0_nCS2 (0x02 << 0)
#define S3C64XX_GPO0_EINT_G7_0 (0x03 << 0)
#define S3C64XX_GPO1_MEM0_nCS3 (0x02 << 2)
#define S3C64XX_GPO1_EINT_G7_1 (0x03 << 2)
#define S3C64XX_GPO2_MEM0_nCS4 (0x02 << 4)
#define S3C64XX_GPO2_EINT_G7_2 (0x03 << 4)
#define S3C64XX_GPO3_MEM0_nCS5 (0x02 << 6)
#define S3C64XX_GPO3_EINT_G7_3 (0x03 << 6)
#define S3C64XX_GPO4_EINT_G7_4 (0x03 << 8)
#define S3C64XX_GPO5_EINT_G7_5 (0x03 << 10)
#define S3C64XX_GPO6_MEM0_ADDR6 (0x02 << 12)
#define S3C64XX_GPO6_EINT_G7_6 (0x03 << 12)
#define S3C64XX_GPO7_MEM0_ADDR7 (0x02 << 14)
#define S3C64XX_GPO7_EINT_G7_7 (0x03 << 14)
#define S3C64XX_GPO8_MEM0_ADDR8 (0x02 << 16)
#define S3C64XX_GPO8_EINT_G7_8 (0x03 << 16)
#define S3C64XX_GPO9_MEM0_ADDR9 (0x02 << 18)
#define S3C64XX_GPO9_EINT_G7_9 (0x03 << 18)
#define S3C64XX_GPO10_MEM0_ADDR10 (0x02 << 20)
#define S3C64XX_GPO10_EINT_G7_10 (0x03 << 20)
#define S3C64XX_GPO11_MEM0_ADDR11 (0x02 << 22)
#define S3C64XX_GPO11_EINT_G7_11 (0x03 << 22)
#define S3C64XX_GPO12_MEM0_ADDR12 (0x02 << 24)
#define S3C64XX_GPO12_EINT_G7_12 (0x03 << 24)
#define S3C64XX_GPO13_MEM0_ADDR13 (0x02 << 26)
#define S3C64XX_GPO13_EINT_G7_13 (0x03 << 26)
#define S3C64XX_GPO14_MEM0_ADDR14 (0x02 << 28)
#define S3C64XX_GPO14_EINT_G7_14 (0x03 << 28)
#define S3C64XX_GPO15_MEM0_ADDR15 (0x02 << 30)
#define S3C64XX_GPO15_EINT_G7_15 (0x03 << 30)

69
arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h 100644
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@ -0,0 +1,69 @@
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank P register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPPCON (S3C64XX_GPP_BASE + 0x00)
#define S3C64XX_GPPDAT (S3C64XX_GPP_BASE + 0x04)
#define S3C64XX_GPPPUD (S3C64XX_GPP_BASE + 0x08)
#define S3C64XX_GPPCONSLP (S3C64XX_GPP_BASE + 0x0c)
#define S3C64XX_GPPPUDSLP (S3C64XX_GPP_BASE + 0x10)
#define S3C64XX_GPP_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPP_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPP_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPP0_MEM0_ADDRV (0x02 << 0)
#define S3C64XX_GPP0_EINT_G8_0 (0x03 << 0)
#define S3C64XX_GPP1_MEM0_SMCLK (0x02 << 2)
#define S3C64XX_GPP1_EINT_G8_1 (0x03 << 2)
#define S3C64XX_GPP2_MEM0_nWAIT (0x02 << 4)
#define S3C64XX_GPP2_EINT_G8_2 (0x03 << 4)
#define S3C64XX_GPP3_MEM0_RDY0_ALE (0x02 << 6)
#define S3C64XX_GPP3_EINT_G8_3 (0x03 << 6)
#define S3C64XX_GPP4_MEM0_RDY1_CLE (0x02 << 8)
#define S3C64XX_GPP4_EINT_G8_4 (0x03 << 8)
#define S3C64XX_GPP5_MEM0_INTsm0_FWE (0x02 << 10)
#define S3C64XX_GPP5_EINT_G8_5 (0x03 << 10)
#define S3C64XX_GPP6_MEM0_(null) (0x02 << 12)
#define S3C64XX_GPP6_EINT_G8_6 (0x03 << 12)
#define S3C64XX_GPP7_MEM0_INTsm1_FRE (0x02 << 14)
#define S3C64XX_GPP7_EINT_G8_7 (0x03 << 14)
#define S3C64XX_GPP8_MEM0_RPn_RnB (0x02 << 16)
#define S3C64XX_GPP8_EINT_G8_8 (0x03 << 16)
#define S3C64XX_GPP9_MEM0_ATA_RESET (0x02 << 18)
#define S3C64XX_GPP9_EINT_G8_9 (0x03 << 18)
#define S3C64XX_GPP10_MEM0_ATA_INPACK (0x02 << 20)
#define S3C64XX_GPP10_EINT_G8_10 (0x03 << 20)
#define S3C64XX_GPP11_MEM0_ATA_REG (0x02 << 22)
#define S3C64XX_GPP11_EINT_G8_11 (0x03 << 22)
#define S3C64XX_GPP12_MEM0_ATA_WE (0x02 << 24)
#define S3C64XX_GPP12_EINT_G8_12 (0x03 << 24)
#define S3C64XX_GPP13_MEM0_ATA_OE (0x02 << 26)
#define S3C64XX_GPP13_EINT_G8_13 (0x03 << 26)
#define S3C64XX_GPP14_MEM0_ATA_CD (0x02 << 28)
#define S3C64XX_GPP14_EINT_G8_14 (0x03 << 28)

46
arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h 100644
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@ -0,0 +1,46 @@
/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* GPIO Bank Q register and configuration definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define S3C64XX_GPQCON (S3C64XX_GPQ_BASE + 0x00)
#define S3C64XX_GPQDAT (S3C64XX_GPQ_BASE + 0x04)
#define S3C64XX_GPQPUD (S3C64XX_GPQ_BASE + 0x08)
#define S3C64XX_GPQCONSLP (S3C64XX_GPQ_BASE + 0x0c)
#define S3C64XX_GPQPUDSLP (S3C64XX_GPQ_BASE + 0x10)
#define S3C64XX_GPQ_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
#define S3C64XX_GPQ_INPUT(__gpio) (0x0 << ((__gpio) * 2))
#define S3C64XX_GPQ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
#define S3C64XX_GPQ0_MEM0_ADDR18_RAS (0x02 << 0)
#define S3C64XX_GPQ0_EINT_G9_0 (0x03 << 0)
#define S3C64XX_GPQ1_MEM0_ADDR19_CAS (0x02 << 2)
#define S3C64XX_GPQ1_EINT_G9_1 (0x03 << 2)
#define S3C64XX_GPQ2_EINT_G9_2 (0x03 << 4)
#define S3C64XX_GPQ3_EINT_G9_3 (0x03 << 6)
#define S3C64XX_GPQ4_EINT_G9_4 (0x03 << 8)
#define S3C64XX_GPQ5_EINT_G9_5 (0x03 << 10)
#define S3C64XX_GPQ6_EINT_G9_6 (0x03 << 12)
#define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC (0x02 << 14)
#define S3C64XX_GPQ7_EINT_G9_7 (0x03 << 14)
#define S3C64XX_GPQ8_MEM0_ADDR16_APDMC (0x02 << 16)
#define S3C64XX_GPQ8_EINT_G9_8 (0x03 << 16)

5
arch/arm/plat-s3c64xx/include/plat/irqs.h
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@ -70,6 +70,7 @@
#define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3)
#define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4)
#define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5)
#define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5)
#define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6)
#define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6)
#define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7)
@ -144,6 +145,10 @@
#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3)
#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4)
/* compatibility for device defines */
#define IRQ_IIC1 IRQ_S3C6410_IIC1
/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
* we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
* which we place after the pair of VICs. */

35
arch/arm/plat-s3c64xx/include/plat/regs-gpio.h 100644
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@ -0,0 +1,35 @@
/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX - GPIO register definitions
*/
#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H
#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__
/* Base addresses for each of the banks */
#define S3C64XX_GPA_BASE (S3C64XX_VA_GPIO + 0x0000)
#define S3C64XX_GPB_BASE (S3C64XX_VA_GPIO + 0x0020)
#define S3C64XX_GPC_BASE (S3C64XX_VA_GPIO + 0x0040)
#define S3C64XX_GPD_BASE (S3C64XX_VA_GPIO + 0x0060)
#define S3C64XX_GPE_BASE (S3C64XX_VA_GPIO + 0x0080)
#define S3C64XX_GPF_BASE (S3C64XX_VA_GPIO + 0x00A0)
#define S3C64XX_GPG_BASE (S3C64XX_VA_GPIO + 0x00C0)
#define S3C64XX_GPH_BASE (S3C64XX_VA_GPIO + 0x00E0)
#define S3C64XX_GPI_BASE (S3C64XX_VA_GPIO + 0x0100)
#define S3C64XX_GPJ_BASE (S3C64XX_VA_GPIO + 0x0120)
#define S3C64XX_GPK_BASE (S3C64XX_VA_GPIO + 0x0800)
#define S3C64XX_GPL_BASE (S3C64XX_VA_GPIO + 0x0810)
#define S3C64XX_GPM_BASE (S3C64XX_VA_GPIO + 0x0820)
#define S3C64XX_GPN_BASE (S3C64XX_VA_GPIO + 0x0830)
#define S3C64XX_GPO_BASE (S3C64XX_VA_GPIO + 0x0140)
#define S3C64XX_GPP_BASE (S3C64XX_VA_GPIO + 0x0160)
#define S3C64XX_GPQ_BASE (S3C64XX_VA_GPIO + 0x0180)
#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */

37
arch/arm/plat-s3c64xx/setup-fb-24bpp.c 100644
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@ -0,0 +1,37 @@
/* linux/arch/arm/plat-s3c64xx/setup-fb-24bpp.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Base S3C64XX setup information for 24bpp LCD framebuffer
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/fb.h>
#include <mach/regs-fb.h>
#include <mach/gpio.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
extern void s3c64xx_fb_gpio_setup_24bpp(void)
{
unsigned int gpio;
for (gpio = S3C64XX_GPI(0); gpio <= S3C64XX_GPI(15); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
for (gpio = S3C64XX_GPJ(0); gpio <= S3C64XX_GPJ(11); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
}

31
arch/arm/plat-s3c64xx/setup-i2c0.c 100644
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@ -0,0 +1,31 @@
/* linux/arch/arm/plat-s3c64xx/setup-i2c0.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Base S3C64XX I2C bus 0 gpio configuration
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
struct platform_device; /* don't need the contents */
#include <mach/gpio.h>
#include <plat/iic.h>
#include <plat/gpio-bank-b.h>
#include <plat/gpio-cfg.h>
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(S3C64XX_GPB(5), S3C64XX_GPB5_I2C_SCL0);
s3c_gpio_cfgpin(S3C64XX_GPB(6), S3C64XX_GPB6_I2C_SDA0);
s3c_gpio_setpull(S3C64XX_GPB(5), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPB(6), S3C_GPIO_PULL_UP);
}

31
arch/arm/plat-s3c64xx/setup-i2c1.c 100644
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@ -0,0 +1,31 @@
/* linux/arch/arm/plat-s3c64xx/setup-i2c1.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Base S3C64XX I2C bus 1 gpio configuration
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
struct platform_device; /* don't need the contents */
#include <mach/gpio.h>
#include <plat/iic.h>
#include <plat/gpio-bank-b.h>
#include <plat/gpio-cfg.h>
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(S3C64XX_GPB(2), S3C64XX_GPB2_I2C_SCL1);
s3c_gpio_cfgpin(S3C64XX_GPB(3), S3C64XX_GPB3_I2C_SDA1);
s3c_gpio_setpull(S3C64XX_GPB(2), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPB(3), S3C_GPIO_PULL_UP);
}