MIPS: scache: Fix scache init with invalid line size.
In current scache init cache line_size is determined from cpu config register, however if there there no scache then mips_sc_probe_cm3 function populates a invalid line_size of 2. The invalid line_size can cause a NULL pointer deference during r4k_dma_cache_inv as r4k_blast_scache is populated based on line_size. Scache line_size of 2 is invalid option in r4k_blast_scache_setup. This issue was faced during a MIPS I6400 based virtual platform bring up where scache was not available in virtual platform model. Signed-off-by: Govindraj Raja <Govindraj.Raja@imgtec.com> Fixes: 7d53e9c4cd21("MIPS: CM3: Add support for CM3 L2 cache.") Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hartley <James.Hartley@imgtec.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org # v4.2+ Patchwork: https://patchwork.linux-mips.org/patch/12710/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -164,11 +164,13 @@ static int __init mips_sc_probe_cm3(void)
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sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE_MSK;
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sets >>= CM_GCR_L2_CONFIG_SET_SIZE_SHF;
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c->scache.sets = 64 << sets;
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if (sets)
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c->scache.sets = 64 << sets;
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line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE_MSK;
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line_sz >>= CM_GCR_L2_CONFIG_LINE_SIZE_SHF;
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c->scache.linesz = 2 << line_sz;
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if (line_sz)
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c->scache.linesz = 2 << line_sz;
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assoc = cfg & CM_GCR_L2_CONFIG_ASSOC_MSK;
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assoc >>= CM_GCR_L2_CONFIG_ASSOC_SHF;
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@ -176,9 +178,12 @@ static int __init mips_sc_probe_cm3(void)
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c->scache.waysize = c->scache.sets * c->scache.linesz;
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c->scache.waybit = __ffs(c->scache.waysize);
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c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
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if (c->scache.linesz) {
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c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
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return 1;
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}
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return 1;
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return 0;
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}
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static inline int __init mips_sc_probe(void)
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